spl.c 8.5 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364
  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * SPL specific code for Compulab CM-FX6 board
  4. *
  5. * Copyright (C) 2014, Compulab Ltd - http://compulab.co.il/
  6. *
  7. * Author: Nikita Kiryanov <nikita@compulab.co.il>
  8. */
  9. #include <common.h>
  10. #include <clock_legacy.h>
  11. #include <spl.h>
  12. #include <asm/io.h>
  13. #include <asm/gpio.h>
  14. #include <asm/arch/mx6-ddr.h>
  15. #include <asm/arch/clock.h>
  16. #include <asm/arch/sys_proto.h>
  17. #include <asm/arch/crm_regs.h>
  18. #include <asm/mach-imx/iomux-v3.h>
  19. #include <fsl_esdhc_imx.h>
  20. #include "common.h"
  21. enum ddr_config {
  22. DDR_16BIT_256MB,
  23. DDR_32BIT_512MB,
  24. DDR_32BIT_1GB,
  25. DDR_64BIT_1GB,
  26. DDR_64BIT_2GB,
  27. DDR_64BIT_4GB,
  28. DDR_UNKNOWN,
  29. };
  30. /*
  31. * Below DRAM_RESET[DDR_SEL] = 0 which is incorrect according to
  32. * Freescale QRM, but this is exactly the value used by the automatic
  33. * calibration script and it works also in all our tests, so we leave
  34. * it as is at this point.
  35. */
  36. #define CM_FX6_DDR_IOMUX_CFG \
  37. .dram_sdqs0 = 0x00000038, \
  38. .dram_sdqs1 = 0x00000038, \
  39. .dram_sdqs2 = 0x00000038, \
  40. .dram_sdqs3 = 0x00000038, \
  41. .dram_sdqs4 = 0x00000038, \
  42. .dram_sdqs5 = 0x00000038, \
  43. .dram_sdqs6 = 0x00000038, \
  44. .dram_sdqs7 = 0x00000038, \
  45. .dram_dqm0 = 0x00000038, \
  46. .dram_dqm1 = 0x00000038, \
  47. .dram_dqm2 = 0x00000038, \
  48. .dram_dqm3 = 0x00000038, \
  49. .dram_dqm4 = 0x00000038, \
  50. .dram_dqm5 = 0x00000038, \
  51. .dram_dqm6 = 0x00000038, \
  52. .dram_dqm7 = 0x00000038, \
  53. .dram_cas = 0x00000038, \
  54. .dram_ras = 0x00000038, \
  55. .dram_sdclk_0 = 0x00000038, \
  56. .dram_sdclk_1 = 0x00000038, \
  57. .dram_sdcke0 = 0x00003000, \
  58. .dram_sdcke1 = 0x00003000, \
  59. .dram_reset = 0x00000038, \
  60. .dram_sdba2 = 0x00000000, \
  61. .dram_sdodt0 = 0x00000038, \
  62. .dram_sdodt1 = 0x00000038,
  63. #define CM_FX6_GPR_IOMUX_CFG \
  64. .grp_b0ds = 0x00000038, \
  65. .grp_b1ds = 0x00000038, \
  66. .grp_b2ds = 0x00000038, \
  67. .grp_b3ds = 0x00000038, \
  68. .grp_b4ds = 0x00000038, \
  69. .grp_b5ds = 0x00000038, \
  70. .grp_b6ds = 0x00000038, \
  71. .grp_b7ds = 0x00000038, \
  72. .grp_addds = 0x00000038, \
  73. .grp_ddrmode_ctl = 0x00020000, \
  74. .grp_ddrpke = 0x00000000, \
  75. .grp_ddrmode = 0x00020000, \
  76. .grp_ctlds = 0x00000038, \
  77. .grp_ddr_type = 0x000C0000,
  78. static struct mx6sdl_iomux_ddr_regs ddr_iomux_s = { CM_FX6_DDR_IOMUX_CFG };
  79. static struct mx6sdl_iomux_grp_regs grp_iomux_s = { CM_FX6_GPR_IOMUX_CFG };
  80. static struct mx6dq_iomux_ddr_regs ddr_iomux_q = { CM_FX6_DDR_IOMUX_CFG };
  81. static struct mx6dq_iomux_grp_regs grp_iomux_q = { CM_FX6_GPR_IOMUX_CFG };
  82. static struct mx6_mmdc_calibration cm_fx6_calib_s = {
  83. .p0_mpwldectrl0 = 0x005B0061,
  84. .p0_mpwldectrl1 = 0x004F0055,
  85. .p0_mpdgctrl0 = 0x0314030C,
  86. .p0_mpdgctrl1 = 0x025C0268,
  87. .p0_mprddlctl = 0x42464646,
  88. .p0_mpwrdlctl = 0x36322C34,
  89. };
  90. static struct mx6_ddr_sysinfo cm_fx6_sysinfo_s = {
  91. .cs1_mirror = 1,
  92. .cs_density = 16,
  93. .bi_on = 1,
  94. .rtt_nom = 1,
  95. .rtt_wr = 0,
  96. .ralat = 5,
  97. .walat = 1,
  98. .mif3_mode = 3,
  99. .rst_to_cke = 0x23,
  100. .sde_to_rst = 0x10,
  101. };
  102. static struct mx6_ddr3_cfg cm_fx6_ddr3_cfg_s = {
  103. .mem_speed = 800,
  104. .density = 4,
  105. .rowaddr = 14,
  106. .coladdr = 10,
  107. .pagesz = 2,
  108. .trcd = 1800,
  109. .trcmin = 5200,
  110. .trasmin = 3600,
  111. .SRT = 0,
  112. };
  113. static void spl_mx6s_dram_init(enum ddr_config dram_config, bool reset)
  114. {
  115. if (reset)
  116. ((struct mmdc_p_regs *)MX6_MMDC_P0_MDCTL)->mdmisc = 2;
  117. switch (dram_config) {
  118. case DDR_16BIT_256MB:
  119. cm_fx6_sysinfo_s.dsize = 0;
  120. cm_fx6_sysinfo_s.ncs = 1;
  121. break;
  122. case DDR_32BIT_512MB:
  123. cm_fx6_sysinfo_s.dsize = 1;
  124. cm_fx6_sysinfo_s.ncs = 1;
  125. break;
  126. case DDR_32BIT_1GB:
  127. cm_fx6_sysinfo_s.dsize = 1;
  128. cm_fx6_sysinfo_s.ncs = 2;
  129. break;
  130. default:
  131. puts("Tried to setup invalid DDR configuration\n");
  132. hang();
  133. }
  134. mx6_dram_cfg(&cm_fx6_sysinfo_s, &cm_fx6_calib_s, &cm_fx6_ddr3_cfg_s);
  135. udelay(100);
  136. }
  137. static struct mx6_mmdc_calibration cm_fx6_calib_q = {
  138. .p0_mpwldectrl0 = 0x00630068,
  139. .p0_mpwldectrl1 = 0x0068005D,
  140. .p0_mpdgctrl0 = 0x04140428,
  141. .p0_mpdgctrl1 = 0x037C037C,
  142. .p0_mprddlctl = 0x3C30303A,
  143. .p0_mpwrdlctl = 0x3A344038,
  144. .p1_mpwldectrl0 = 0x0035004C,
  145. .p1_mpwldectrl1 = 0x00170026,
  146. .p1_mpdgctrl0 = 0x0374037C,
  147. .p1_mpdgctrl1 = 0x0350032C,
  148. .p1_mprddlctl = 0x30322A3C,
  149. .p1_mpwrdlctl = 0x48304A3E,
  150. };
  151. static struct mx6_ddr_sysinfo cm_fx6_sysinfo_q = {
  152. .cs_density = 16,
  153. .cs1_mirror = 1,
  154. .bi_on = 1,
  155. .rtt_nom = 1,
  156. .rtt_wr = 0,
  157. .ralat = 5,
  158. .walat = 1,
  159. .mif3_mode = 3,
  160. .rst_to_cke = 0x23,
  161. .sde_to_rst = 0x10,
  162. .refsel = 1, /* Refresh cycles at 32KHz */
  163. .refr = 7, /* 8 refresh commands per refresh cycle */
  164. };
  165. static struct mx6_ddr3_cfg cm_fx6_ddr3_cfg_q = {
  166. .mem_speed = 1066,
  167. .density = 4,
  168. .rowaddr = 14,
  169. .coladdr = 10,
  170. .pagesz = 2,
  171. .trcd = 1324,
  172. .trcmin = 59500,
  173. .trasmin = 9750,
  174. .SRT = 0,
  175. };
  176. static void spl_mx6q_dram_init(enum ddr_config dram_config, bool reset)
  177. {
  178. if (reset)
  179. ((struct mmdc_p_regs *)MX6_MMDC_P0_MDCTL)->mdmisc = 2;
  180. cm_fx6_ddr3_cfg_q.rowaddr = 14;
  181. switch (dram_config) {
  182. case DDR_16BIT_256MB:
  183. cm_fx6_sysinfo_q.dsize = 0;
  184. cm_fx6_sysinfo_q.ncs = 1;
  185. break;
  186. case DDR_32BIT_512MB:
  187. cm_fx6_sysinfo_q.dsize = 1;
  188. cm_fx6_sysinfo_q.ncs = 1;
  189. break;
  190. case DDR_64BIT_1GB:
  191. cm_fx6_sysinfo_q.dsize = 2;
  192. cm_fx6_sysinfo_q.ncs = 1;
  193. break;
  194. case DDR_64BIT_2GB:
  195. cm_fx6_sysinfo_q.dsize = 2;
  196. cm_fx6_sysinfo_q.ncs = 2;
  197. break;
  198. case DDR_64BIT_4GB:
  199. cm_fx6_sysinfo_q.dsize = 2;
  200. cm_fx6_sysinfo_q.ncs = 2;
  201. cm_fx6_ddr3_cfg_q.rowaddr = 15;
  202. break;
  203. default:
  204. puts("Tried to setup invalid DDR configuration\n");
  205. hang();
  206. }
  207. mx6_dram_cfg(&cm_fx6_sysinfo_q, &cm_fx6_calib_q, &cm_fx6_ddr3_cfg_q);
  208. udelay(100);
  209. }
  210. static int cm_fx6_spl_dram_init(void)
  211. {
  212. unsigned long bank1_size, bank2_size;
  213. switch (get_cpu_type()) {
  214. case MXC_CPU_MX6SOLO:
  215. mx6sdl_dram_iocfg(64, &ddr_iomux_s, &grp_iomux_s);
  216. spl_mx6s_dram_init(DDR_32BIT_1GB, false);
  217. bank1_size = get_ram_size((long int *)PHYS_SDRAM_1, 0x80000000);
  218. bank2_size = get_ram_size((long int *)PHYS_SDRAM_2, 0x80000000);
  219. if (bank1_size == 0x20000000) {
  220. if (bank2_size == 0x20000000)
  221. return 0;
  222. spl_mx6s_dram_init(DDR_32BIT_512MB, true);
  223. return 0;
  224. }
  225. spl_mx6s_dram_init(DDR_16BIT_256MB, true);
  226. bank1_size = get_ram_size((long int *)PHYS_SDRAM_1, 0x80000000);
  227. if (bank1_size == 0x10000000)
  228. return 0;
  229. break;
  230. case MXC_CPU_MX6D:
  231. case MXC_CPU_MX6Q:
  232. mx6dq_dram_iocfg(64, &ddr_iomux_q, &grp_iomux_q);
  233. spl_mx6q_dram_init(DDR_64BIT_4GB, false);
  234. bank1_size = get_ram_size((long int *)PHYS_SDRAM_1, 0x80000000);
  235. if (bank1_size == 0x80000000)
  236. return 0;
  237. if (bank1_size == 0x40000000) {
  238. bank2_size = get_ram_size((long int *)PHYS_SDRAM_2,
  239. 0x80000000);
  240. if (bank2_size == 0x40000000) {
  241. /* Don't do a full reset here */
  242. spl_mx6q_dram_init(DDR_64BIT_2GB, false);
  243. } else {
  244. spl_mx6q_dram_init(DDR_64BIT_1GB, true);
  245. }
  246. return 0;
  247. }
  248. spl_mx6q_dram_init(DDR_32BIT_512MB, true);
  249. bank1_size = get_ram_size((long int *)PHYS_SDRAM_1, 0x80000000);
  250. if (bank1_size == 0x20000000)
  251. return 0;
  252. spl_mx6q_dram_init(DDR_16BIT_256MB, true);
  253. bank1_size = get_ram_size((long int *)PHYS_SDRAM_1, 0x80000000);
  254. if (bank1_size == 0x10000000)
  255. return 0;
  256. break;
  257. }
  258. return -1;
  259. }
  260. static iomux_v3_cfg_t const uart4_pads[] = {
  261. IOMUX_PADS(PAD_KEY_COL0__UART4_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
  262. IOMUX_PADS(PAD_KEY_ROW0__UART4_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
  263. };
  264. static void cm_fx6_setup_uart(void)
  265. {
  266. SETUP_IOMUX_PADS(uart4_pads);
  267. enable_uart_clk(1);
  268. }
  269. #ifdef CONFIG_SPL_SPI_SUPPORT
  270. static void cm_fx6_setup_ecspi(void)
  271. {
  272. cm_fx6_set_ecspi_iomux();
  273. enable_spi_clk(1, 0);
  274. }
  275. #else
  276. static void cm_fx6_setup_ecspi(void) { }
  277. #endif
  278. void board_init_f(ulong dummy)
  279. {
  280. struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
  281. /*
  282. * We don't use DMA in SPL, but we do need it in U-Boot. U-Boot
  283. * initializes DMA very early (before all board code), so the only
  284. * opportunity we have to initialize APBHDMA clocks is in SPL.
  285. */
  286. setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK);
  287. enable_usdhc_clk(1, 2);
  288. arch_cpu_init();
  289. timer_init();
  290. cm_fx6_setup_ecspi();
  291. cm_fx6_setup_uart();
  292. get_clocks();
  293. preloader_console_init();
  294. gpio_direction_output(CM_FX6_GREEN_LED, 1);
  295. if (cm_fx6_spl_dram_init()) {
  296. puts("!!!ERROR!!! DRAM detection failed!!!\n");
  297. hang();
  298. }
  299. }
  300. void board_boot_order(u32 *spl_boot_list)
  301. {
  302. spl_boot_list[0] = spl_boot_device();
  303. switch (spl_boot_list[0]) {
  304. case BOOT_DEVICE_SPI:
  305. spl_boot_list[1] = BOOT_DEVICE_MMC1;
  306. break;
  307. case BOOT_DEVICE_MMC1:
  308. spl_boot_list[1] = BOOT_DEVICE_SPI;
  309. break;
  310. }
  311. }
  312. #ifdef CONFIG_SPL_MMC_SUPPORT
  313. static struct fsl_esdhc_cfg usdhc_cfg = {
  314. .esdhc_base = USDHC3_BASE_ADDR,
  315. .max_bus_width = 4,
  316. };
  317. int board_mmc_init(bd_t *bis)
  318. {
  319. cm_fx6_set_usdhc_iomux();
  320. usdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
  321. return fsl_esdhc_initialize(bis, &usdhc_cfg);
  322. }
  323. #endif