speed.c 19 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2004, 2007-2011 Freescale Semiconductor, Inc.
  4. *
  5. * (C) Copyright 2003 Motorola Inc.
  6. * Xianghua Xiao, (X.Xiao@motorola.com)
  7. *
  8. * (C) Copyright 2000
  9. * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  10. */
  11. #include <common.h>
  12. #include <cpu_func.h>
  13. #include <ppc_asm.tmpl>
  14. #include <linux/compiler.h>
  15. #include <asm/processor.h>
  16. #include <asm/io.h>
  17. DECLARE_GLOBAL_DATA_PTR;
  18. #ifndef CONFIG_SYS_FSL_NUM_CC_PLLS
  19. #define CONFIG_SYS_FSL_NUM_CC_PLLS 6
  20. #endif
  21. /* --------------------------------------------------------------- */
  22. void get_sys_info(sys_info_t *sys_info)
  23. {
  24. volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  25. #ifdef CONFIG_FSL_CORENET
  26. volatile ccsr_clk_t *clk = (void *)(CONFIG_SYS_FSL_CORENET_CLK_ADDR);
  27. unsigned int cpu;
  28. #ifdef CONFIG_HETROGENOUS_CLUSTERS
  29. unsigned int dsp_cpu;
  30. uint rcw_tmp1, rcw_tmp2;
  31. #endif
  32. #ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
  33. int cc_group[12] = CONFIG_SYS_FSL_CLUSTER_CLOCKS;
  34. #endif
  35. __maybe_unused u32 svr;
  36. const u8 core_cplx_PLL[16] = {
  37. [ 0] = 0, /* CC1 PPL / 1 */
  38. [ 1] = 0, /* CC1 PPL / 2 */
  39. [ 2] = 0, /* CC1 PPL / 4 */
  40. [ 4] = 1, /* CC2 PPL / 1 */
  41. [ 5] = 1, /* CC2 PPL / 2 */
  42. [ 6] = 1, /* CC2 PPL / 4 */
  43. [ 8] = 2, /* CC3 PPL / 1 */
  44. [ 9] = 2, /* CC3 PPL / 2 */
  45. [10] = 2, /* CC3 PPL / 4 */
  46. [12] = 3, /* CC4 PPL / 1 */
  47. [13] = 3, /* CC4 PPL / 2 */
  48. [14] = 3, /* CC4 PPL / 4 */
  49. };
  50. const u8 core_cplx_pll_div[16] = {
  51. [ 0] = 1, /* CC1 PPL / 1 */
  52. [ 1] = 2, /* CC1 PPL / 2 */
  53. [ 2] = 4, /* CC1 PPL / 4 */
  54. [ 4] = 1, /* CC2 PPL / 1 */
  55. [ 5] = 2, /* CC2 PPL / 2 */
  56. [ 6] = 4, /* CC2 PPL / 4 */
  57. [ 8] = 1, /* CC3 PPL / 1 */
  58. [ 9] = 2, /* CC3 PPL / 2 */
  59. [10] = 4, /* CC3 PPL / 4 */
  60. [12] = 1, /* CC4 PPL / 1 */
  61. [13] = 2, /* CC4 PPL / 2 */
  62. [14] = 4, /* CC4 PPL / 4 */
  63. };
  64. uint i, freq_c_pll[CONFIG_SYS_FSL_NUM_CC_PLLS];
  65. #if !defined(CONFIG_FM_PLAT_CLK_DIV) || !defined(CONFIG_PME_PLAT_CLK_DIV)
  66. uint rcw_tmp;
  67. #endif
  68. uint ratio[CONFIG_SYS_FSL_NUM_CC_PLLS];
  69. unsigned long sysclk = CONFIG_SYS_CLK_FREQ;
  70. uint mem_pll_rat;
  71. sys_info->freq_systembus = sysclk;
  72. #ifdef CONFIG_SYS_FSL_SINGLE_SOURCE_CLK
  73. uint ddr_refclk_sel;
  74. unsigned int porsr1_sys_clk;
  75. porsr1_sys_clk = in_be32(&gur->porsr1) >> FSL_DCFG_PORSR1_SYSCLK_SHIFT
  76. & FSL_DCFG_PORSR1_SYSCLK_MASK;
  77. if (porsr1_sys_clk == FSL_DCFG_PORSR1_SYSCLK_DIFF)
  78. sys_info->diff_sysclk = 1;
  79. else
  80. sys_info->diff_sysclk = 0;
  81. /*
  82. * DDR_REFCLK_SEL rcw bit is used to determine if DDR PLLS
  83. * are driven by separate DDR Refclock or single source
  84. * differential clock.
  85. */
  86. ddr_refclk_sel = (in_be32(&gur->rcwsr[5]) >>
  87. FSL_CORENET2_RCWSR5_DDR_REFCLK_SEL_SHIFT) &
  88. FSL_CORENET2_RCWSR5_DDR_REFCLK_SEL_MASK;
  89. /*
  90. * For single source clocking, both ddrclock and sysclock
  91. * are driven by differential sysclock.
  92. */
  93. if (ddr_refclk_sel == FSL_CORENET2_RCWSR5_DDR_REFCLK_SINGLE_CLK)
  94. sys_info->freq_ddrbus = CONFIG_SYS_CLK_FREQ;
  95. else
  96. #endif
  97. #ifdef CONFIG_DDR_CLK_FREQ
  98. sys_info->freq_ddrbus = CONFIG_DDR_CLK_FREQ;
  99. #else
  100. sys_info->freq_ddrbus = sysclk;
  101. #endif
  102. sys_info->freq_systembus *= (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f;
  103. mem_pll_rat = (in_be32(&gur->rcwsr[0]) >>
  104. FSL_CORENET_RCWSR0_MEM_PLL_RAT_SHIFT)
  105. & FSL_CORENET_RCWSR0_MEM_PLL_RAT_MASK;
  106. #ifdef CONFIG_SYS_FSL_ERRATUM_A007212
  107. if (mem_pll_rat == 0) {
  108. mem_pll_rat = (in_be32(&gur->rcwsr[0]) >>
  109. FSL_CORENET_RCWSR0_MEM_PLL_RAT_RESV_SHIFT) &
  110. FSL_CORENET_RCWSR0_MEM_PLL_RAT_MASK;
  111. }
  112. #endif
  113. /* T4240/T4160 Rev2.0 MEM_PLL_RAT uses a value which is half of
  114. * T4240/T4160 Rev1.0. eg. It's 12 in Rev1.0, however, for Rev2.0
  115. * it uses 6.
  116. * T2080 rev 1.1 and later also use half mem_pll comparing with rev 1.0
  117. */
  118. #if defined(CONFIG_ARCH_T4240) || defined(CONFIG_ARCH_T4160) || \
  119. defined(CONFIG_ARCH_T2080) || defined(CONFIG_ARCH_T2081)
  120. svr = get_svr();
  121. switch (SVR_SOC_VER(svr)) {
  122. case SVR_T4240:
  123. case SVR_T4160:
  124. case SVR_T4120:
  125. case SVR_T4080:
  126. if (SVR_MAJ(svr) >= 2)
  127. mem_pll_rat *= 2;
  128. break;
  129. case SVR_T2080:
  130. case SVR_T2081:
  131. if ((SVR_MAJ(svr) > 1) || (SVR_MIN(svr) >= 1))
  132. mem_pll_rat *= 2;
  133. break;
  134. default:
  135. break;
  136. }
  137. #endif
  138. if (mem_pll_rat > 2)
  139. sys_info->freq_ddrbus *= mem_pll_rat;
  140. else
  141. sys_info->freq_ddrbus = sys_info->freq_systembus * mem_pll_rat;
  142. for (i = 0; i < CONFIG_SYS_FSL_NUM_CC_PLLS; i++) {
  143. ratio[i] = (in_be32(&clk->pllcgsr[i].pllcngsr) >> 1) & 0x3f;
  144. if (ratio[i] > 4)
  145. freq_c_pll[i] = sysclk * ratio[i];
  146. else
  147. freq_c_pll[i] = sys_info->freq_systembus * ratio[i];
  148. }
  149. #ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
  150. /*
  151. * As per CHASSIS2 architeture total 12 clusters are posible and
  152. * Each cluster has up to 4 cores, sharing the same PLL selection.
  153. * The cluster clock assignment is SoC defined.
  154. *
  155. * Total 4 clock groups are possible with 3 PLLs each.
  156. * as per array indices, clock group A has 0, 1, 2 numbered PLLs &
  157. * clock group B has 3, 4, 6 and so on.
  158. *
  159. * Clock group A having PLL1, PLL2, PLL3, feeding cores of any cluster
  160. * depends upon the SoC architeture. Same applies to other
  161. * clock groups and clusters.
  162. *
  163. */
  164. for_each_cpu(i, cpu, cpu_numcores(), cpu_mask()) {
  165. int cluster = fsl_qoriq_core_to_cluster(cpu);
  166. u32 c_pll_sel = (in_be32(&clk->clkcsr[cluster].clkcncsr) >> 27)
  167. & 0xf;
  168. u32 cplx_pll = core_cplx_PLL[c_pll_sel];
  169. cplx_pll += cc_group[cluster] - 1;
  170. sys_info->freq_processor[cpu] =
  171. freq_c_pll[cplx_pll] / core_cplx_pll_div[c_pll_sel];
  172. }
  173. #ifdef CONFIG_HETROGENOUS_CLUSTERS
  174. for_each_cpu(i, dsp_cpu, cpu_num_dspcores(), cpu_dsp_mask()) {
  175. int dsp_cluster = fsl_qoriq_dsp_core_to_cluster(dsp_cpu);
  176. u32 c_pll_sel = (in_be32
  177. (&clk->clkcsr[dsp_cluster].clkcncsr) >> 27)
  178. & 0xf;
  179. u32 cplx_pll = core_cplx_PLL[c_pll_sel];
  180. cplx_pll += cc_group[dsp_cluster] - 1;
  181. sys_info->freq_processor_dsp[dsp_cpu] =
  182. freq_c_pll[cplx_pll] / core_cplx_pll_div[c_pll_sel];
  183. }
  184. #endif
  185. #if defined(CONFIG_ARCH_B4860) || defined(CONFIG_ARCH_B4420) || \
  186. defined(CONFIG_ARCH_T2080) || defined(CONFIG_ARCH_T2081)
  187. #define FM1_CLK_SEL 0xe0000000
  188. #define FM1_CLK_SHIFT 29
  189. #elif defined(CONFIG_ARCH_T1024) || defined(CONFIG_ARCH_T1023)
  190. #define FM1_CLK_SEL 0x00000007
  191. #define FM1_CLK_SHIFT 0
  192. #else
  193. #define PME_CLK_SEL 0xe0000000
  194. #define PME_CLK_SHIFT 29
  195. #define FM1_CLK_SEL 0x1c000000
  196. #define FM1_CLK_SHIFT 26
  197. #endif
  198. #if !defined(CONFIG_FM_PLAT_CLK_DIV) || !defined(CONFIG_PME_PLAT_CLK_DIV)
  199. #if defined(CONFIG_ARCH_T1024) || defined(CONFIG_ARCH_T1023)
  200. rcw_tmp = in_be32(&gur->rcwsr[15]) - 4;
  201. #else
  202. rcw_tmp = in_be32(&gur->rcwsr[7]);
  203. #endif
  204. #endif
  205. #ifdef CONFIG_SYS_DPAA_PME
  206. #ifndef CONFIG_PME_PLAT_CLK_DIV
  207. switch ((rcw_tmp & PME_CLK_SEL) >> PME_CLK_SHIFT) {
  208. case 1:
  209. sys_info->freq_pme = freq_c_pll[CONFIG_SYS_PME_CLK];
  210. break;
  211. case 2:
  212. sys_info->freq_pme = freq_c_pll[CONFIG_SYS_PME_CLK] / 2;
  213. break;
  214. case 3:
  215. sys_info->freq_pme = freq_c_pll[CONFIG_SYS_PME_CLK] / 3;
  216. break;
  217. case 4:
  218. sys_info->freq_pme = freq_c_pll[CONFIG_SYS_PME_CLK] / 4;
  219. break;
  220. case 6:
  221. sys_info->freq_pme = freq_c_pll[CONFIG_SYS_PME_CLK + 1] / 2;
  222. break;
  223. case 7:
  224. sys_info->freq_pme = freq_c_pll[CONFIG_SYS_PME_CLK + 1] / 3;
  225. break;
  226. default:
  227. printf("Error: Unknown PME clock select!\n");
  228. case 0:
  229. sys_info->freq_pme = sys_info->freq_systembus / 2;
  230. break;
  231. }
  232. #else
  233. sys_info->freq_pme = sys_info->freq_systembus / CONFIG_SYS_PME_CLK;
  234. #endif
  235. #endif
  236. #ifdef CONFIG_SYS_DPAA_QBMAN
  237. #ifndef CONFIG_QBMAN_CLK_DIV
  238. #define CONFIG_QBMAN_CLK_DIV 2
  239. #endif
  240. sys_info->freq_qman = sys_info->freq_systembus / CONFIG_QBMAN_CLK_DIV;
  241. #endif
  242. #if defined(CONFIG_SYS_MAPLE)
  243. #define CPRI_CLK_SEL 0x1C000000
  244. #define CPRI_CLK_SHIFT 26
  245. #define CPRI_ALT_CLK_SEL 0x00007000
  246. #define CPRI_ALT_CLK_SHIFT 12
  247. rcw_tmp1 = in_be32(&gur->rcwsr[7]); /* Reading RCW bits: 224-255*/
  248. rcw_tmp2 = in_be32(&gur->rcwsr[15]); /* Reading RCW bits: 480-511*/
  249. /* For MAPLE and CPRI frequency */
  250. switch ((rcw_tmp1 & CPRI_CLK_SEL) >> CPRI_CLK_SHIFT) {
  251. case 1:
  252. sys_info->freq_maple = freq_c_pll[CONFIG_SYS_CPRI_CLK];
  253. sys_info->freq_cpri = freq_c_pll[CONFIG_SYS_CPRI_CLK];
  254. break;
  255. case 2:
  256. sys_info->freq_maple = freq_c_pll[CONFIG_SYS_CPRI_CLK] / 2;
  257. sys_info->freq_cpri = freq_c_pll[CONFIG_SYS_CPRI_CLK] / 2;
  258. break;
  259. case 3:
  260. sys_info->freq_maple = freq_c_pll[CONFIG_SYS_CPRI_CLK] / 3;
  261. sys_info->freq_cpri = freq_c_pll[CONFIG_SYS_CPRI_CLK] / 3;
  262. break;
  263. case 4:
  264. sys_info->freq_maple = freq_c_pll[CONFIG_SYS_CPRI_CLK] / 4;
  265. sys_info->freq_cpri = freq_c_pll[CONFIG_SYS_CPRI_CLK] / 4;
  266. break;
  267. case 5:
  268. if (((rcw_tmp2 & CPRI_ALT_CLK_SEL)
  269. >> CPRI_ALT_CLK_SHIFT) == 6) {
  270. sys_info->freq_maple =
  271. freq_c_pll[CONFIG_SYS_CPRI_CLK - 2] / 2;
  272. sys_info->freq_cpri =
  273. freq_c_pll[CONFIG_SYS_CPRI_CLK - 2] / 2;
  274. }
  275. if (((rcw_tmp2 & CPRI_ALT_CLK_SEL)
  276. >> CPRI_ALT_CLK_SHIFT) == 7) {
  277. sys_info->freq_maple =
  278. freq_c_pll[CONFIG_SYS_CPRI_CLK - 2] / 3;
  279. sys_info->freq_cpri =
  280. freq_c_pll[CONFIG_SYS_CPRI_CLK - 2] / 3;
  281. }
  282. break;
  283. case 6:
  284. sys_info->freq_maple = freq_c_pll[CONFIG_SYS_CPRI_CLK + 1] / 2;
  285. sys_info->freq_cpri = freq_c_pll[CONFIG_SYS_CPRI_CLK + 1] / 2;
  286. break;
  287. case 7:
  288. sys_info->freq_maple = freq_c_pll[CONFIG_SYS_CPRI_CLK + 1] / 3;
  289. sys_info->freq_cpri = freq_c_pll[CONFIG_SYS_CPRI_CLK + 1] / 3;
  290. break;
  291. default:
  292. printf("Error: Unknown MAPLE/CPRI clock select!\n");
  293. }
  294. /* For MAPLE ULB and eTVPE frequencies */
  295. #define ULB_CLK_SEL 0x00000038
  296. #define ULB_CLK_SHIFT 3
  297. #define ETVPE_CLK_SEL 0x00000007
  298. #define ETVPE_CLK_SHIFT 0
  299. switch ((rcw_tmp2 & ULB_CLK_SEL) >> ULB_CLK_SHIFT) {
  300. case 1:
  301. sys_info->freq_maple_ulb = freq_c_pll[CONFIG_SYS_ULB_CLK];
  302. break;
  303. case 2:
  304. sys_info->freq_maple_ulb = freq_c_pll[CONFIG_SYS_ULB_CLK] / 2;
  305. break;
  306. case 3:
  307. sys_info->freq_maple_ulb = freq_c_pll[CONFIG_SYS_ULB_CLK] / 3;
  308. break;
  309. case 4:
  310. sys_info->freq_maple_ulb = freq_c_pll[CONFIG_SYS_ULB_CLK] / 4;
  311. break;
  312. case 5:
  313. sys_info->freq_maple_ulb = sys_info->freq_systembus;
  314. break;
  315. case 6:
  316. sys_info->freq_maple_ulb =
  317. freq_c_pll[CONFIG_SYS_ULB_CLK - 1] / 2;
  318. break;
  319. case 7:
  320. sys_info->freq_maple_ulb =
  321. freq_c_pll[CONFIG_SYS_ULB_CLK - 1] / 3;
  322. break;
  323. default:
  324. printf("Error: Unknown MAPLE ULB clock select!\n");
  325. }
  326. switch ((rcw_tmp2 & ETVPE_CLK_SEL) >> ETVPE_CLK_SHIFT) {
  327. case 1:
  328. sys_info->freq_maple_etvpe = freq_c_pll[CONFIG_SYS_ETVPE_CLK];
  329. break;
  330. case 2:
  331. sys_info->freq_maple_etvpe =
  332. freq_c_pll[CONFIG_SYS_ETVPE_CLK] / 2;
  333. break;
  334. case 3:
  335. sys_info->freq_maple_etvpe =
  336. freq_c_pll[CONFIG_SYS_ETVPE_CLK] / 3;
  337. break;
  338. case 4:
  339. sys_info->freq_maple_etvpe =
  340. freq_c_pll[CONFIG_SYS_ETVPE_CLK] / 4;
  341. break;
  342. case 5:
  343. sys_info->freq_maple_etvpe = sys_info->freq_systembus;
  344. break;
  345. case 6:
  346. sys_info->freq_maple_etvpe =
  347. freq_c_pll[CONFIG_SYS_ETVPE_CLK - 1] / 2;
  348. break;
  349. case 7:
  350. sys_info->freq_maple_etvpe =
  351. freq_c_pll[CONFIG_SYS_ETVPE_CLK - 1] / 3;
  352. break;
  353. default:
  354. printf("Error: Unknown MAPLE eTVPE clock select!\n");
  355. }
  356. #endif
  357. #ifdef CONFIG_SYS_DPAA_FMAN
  358. #ifndef CONFIG_FM_PLAT_CLK_DIV
  359. switch ((rcw_tmp & FM1_CLK_SEL) >> FM1_CLK_SHIFT) {
  360. case 1:
  361. sys_info->freq_fman[0] = freq_c_pll[CONFIG_SYS_FM1_CLK];
  362. break;
  363. case 2:
  364. sys_info->freq_fman[0] = freq_c_pll[CONFIG_SYS_FM1_CLK] / 2;
  365. break;
  366. case 3:
  367. sys_info->freq_fman[0] = freq_c_pll[CONFIG_SYS_FM1_CLK] / 3;
  368. break;
  369. case 4:
  370. sys_info->freq_fman[0] = freq_c_pll[CONFIG_SYS_FM1_CLK] / 4;
  371. break;
  372. case 5:
  373. sys_info->freq_fman[0] = sys_info->freq_systembus;
  374. break;
  375. case 6:
  376. sys_info->freq_fman[0] = freq_c_pll[CONFIG_SYS_FM1_CLK + 1] / 2;
  377. break;
  378. case 7:
  379. sys_info->freq_fman[0] = freq_c_pll[CONFIG_SYS_FM1_CLK + 1] / 3;
  380. break;
  381. default:
  382. printf("Error: Unknown FMan1 clock select!\n");
  383. case 0:
  384. sys_info->freq_fman[0] = sys_info->freq_systembus / 2;
  385. break;
  386. }
  387. #if (CONFIG_SYS_NUM_FMAN) == 2
  388. #ifdef CONFIG_SYS_FM2_CLK
  389. #define FM2_CLK_SEL 0x00000038
  390. #define FM2_CLK_SHIFT 3
  391. rcw_tmp = in_be32(&gur->rcwsr[15]);
  392. switch ((rcw_tmp & FM2_CLK_SEL) >> FM2_CLK_SHIFT) {
  393. case 1:
  394. sys_info->freq_fman[1] = freq_c_pll[CONFIG_SYS_FM2_CLK + 1];
  395. break;
  396. case 2:
  397. sys_info->freq_fman[1] = freq_c_pll[CONFIG_SYS_FM2_CLK + 1] / 2;
  398. break;
  399. case 3:
  400. sys_info->freq_fman[1] = freq_c_pll[CONFIG_SYS_FM2_CLK + 1] / 3;
  401. break;
  402. case 4:
  403. sys_info->freq_fman[1] = freq_c_pll[CONFIG_SYS_FM2_CLK + 1] / 4;
  404. break;
  405. case 5:
  406. sys_info->freq_fman[1] = sys_info->freq_systembus;
  407. break;
  408. case 6:
  409. sys_info->freq_fman[1] = freq_c_pll[CONFIG_SYS_FM2_CLK] / 2;
  410. break;
  411. case 7:
  412. sys_info->freq_fman[1] = freq_c_pll[CONFIG_SYS_FM2_CLK] / 3;
  413. break;
  414. default:
  415. printf("Error: Unknown FMan2 clock select!\n");
  416. case 0:
  417. sys_info->freq_fman[1] = sys_info->freq_systembus / 2;
  418. break;
  419. }
  420. #endif
  421. #endif /* CONFIG_SYS_NUM_FMAN == 2 */
  422. #else
  423. sys_info->freq_fman[0] = sys_info->freq_systembus / CONFIG_SYS_FM1_CLK;
  424. #endif
  425. #endif
  426. #else /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */
  427. for_each_cpu(i, cpu, cpu_numcores(), cpu_mask()) {
  428. u32 c_pll_sel = (in_be32(&clk->clkcsr[cpu].clkcncsr) >> 27)
  429. & 0xf;
  430. u32 cplx_pll = core_cplx_PLL[c_pll_sel];
  431. sys_info->freq_processor[cpu] =
  432. freq_c_pll[cplx_pll] / core_cplx_pll_div[c_pll_sel];
  433. }
  434. #define PME_CLK_SEL 0x80000000
  435. #define FM1_CLK_SEL 0x40000000
  436. #define FM2_CLK_SEL 0x20000000
  437. #define HWA_ASYNC_DIV 0x04000000
  438. #if (CONFIG_SYS_FSL_NUM_CC_PLLS == 2)
  439. #define HWA_CC_PLL 1
  440. #elif (CONFIG_SYS_FSL_NUM_CC_PLLS == 3)
  441. #define HWA_CC_PLL 2
  442. #elif (CONFIG_SYS_FSL_NUM_CC_PLLS == 4)
  443. #define HWA_CC_PLL 2
  444. #else
  445. #error CONFIG_SYS_FSL_NUM_CC_PLLS not set or unknown case
  446. #endif
  447. rcw_tmp = in_be32(&gur->rcwsr[7]);
  448. #ifdef CONFIG_SYS_DPAA_PME
  449. if (rcw_tmp & PME_CLK_SEL) {
  450. if (rcw_tmp & HWA_ASYNC_DIV)
  451. sys_info->freq_pme = freq_c_pll[HWA_CC_PLL] / 4;
  452. else
  453. sys_info->freq_pme = freq_c_pll[HWA_CC_PLL] / 2;
  454. } else {
  455. sys_info->freq_pme = sys_info->freq_systembus / 2;
  456. }
  457. #endif
  458. #ifdef CONFIG_SYS_DPAA_FMAN
  459. if (rcw_tmp & FM1_CLK_SEL) {
  460. if (rcw_tmp & HWA_ASYNC_DIV)
  461. sys_info->freq_fman[0] = freq_c_pll[HWA_CC_PLL] / 4;
  462. else
  463. sys_info->freq_fman[0] = freq_c_pll[HWA_CC_PLL] / 2;
  464. } else {
  465. sys_info->freq_fman[0] = sys_info->freq_systembus / 2;
  466. }
  467. #if (CONFIG_SYS_NUM_FMAN) == 2
  468. if (rcw_tmp & FM2_CLK_SEL) {
  469. if (rcw_tmp & HWA_ASYNC_DIV)
  470. sys_info->freq_fman[1] = freq_c_pll[HWA_CC_PLL] / 4;
  471. else
  472. sys_info->freq_fman[1] = freq_c_pll[HWA_CC_PLL] / 2;
  473. } else {
  474. sys_info->freq_fman[1] = sys_info->freq_systembus / 2;
  475. }
  476. #endif
  477. #endif
  478. #ifdef CONFIG_SYS_DPAA_QBMAN
  479. sys_info->freq_qman = sys_info->freq_systembus / 2;
  480. #endif
  481. #endif /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */
  482. #ifdef CONFIG_U_QE
  483. sys_info->freq_qe = sys_info->freq_systembus / 2;
  484. #endif
  485. #else /* CONFIG_FSL_CORENET */
  486. uint plat_ratio, e500_ratio, half_freq_systembus;
  487. int i;
  488. #ifdef CONFIG_QE
  489. __maybe_unused u32 qe_ratio;
  490. #endif
  491. plat_ratio = (gur->porpllsr) & 0x0000003e;
  492. plat_ratio >>= 1;
  493. sys_info->freq_systembus = plat_ratio * CONFIG_SYS_CLK_FREQ;
  494. /* Divide before multiply to avoid integer
  495. * overflow for processor speeds above 2GHz */
  496. half_freq_systembus = sys_info->freq_systembus/2;
  497. for (i = 0; i < cpu_numcores(); i++) {
  498. e500_ratio = ((gur->porpllsr) >> (i * 8 + 16)) & 0x3f;
  499. sys_info->freq_processor[i] = e500_ratio * half_freq_systembus;
  500. }
  501. /* Note: freq_ddrbus is the MCLK frequency, not the data rate. */
  502. sys_info->freq_ddrbus = sys_info->freq_systembus;
  503. #ifdef CONFIG_DDR_CLK_FREQ
  504. {
  505. u32 ddr_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_DDR_RATIO)
  506. >> MPC85xx_PORPLLSR_DDR_RATIO_SHIFT;
  507. if (ddr_ratio != 0x7)
  508. sys_info->freq_ddrbus = ddr_ratio * CONFIG_DDR_CLK_FREQ;
  509. }
  510. #endif
  511. #ifdef CONFIG_QE
  512. #if defined(CONFIG_ARCH_P1021) || defined(CONFIG_ARCH_P1025)
  513. sys_info->freq_qe = sys_info->freq_systembus;
  514. #else
  515. qe_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_QE_RATIO)
  516. >> MPC85xx_PORPLLSR_QE_RATIO_SHIFT;
  517. sys_info->freq_qe = qe_ratio * CONFIG_SYS_CLK_FREQ;
  518. #endif
  519. #endif
  520. #ifdef CONFIG_SYS_DPAA_FMAN
  521. sys_info->freq_fman[0] = sys_info->freq_systembus;
  522. #endif
  523. #endif /* CONFIG_FSL_CORENET */
  524. #if defined(CONFIG_FSL_LBC)
  525. sys_info->freq_localbus = sys_info->freq_systembus /
  526. CONFIG_SYS_FSL_LBC_CLK_DIV;
  527. #endif
  528. #if defined(CONFIG_FSL_IFC)
  529. sys_info->freq_localbus = sys_info->freq_systembus /
  530. CONFIG_SYS_FSL_IFC_CLK_DIV;
  531. #endif
  532. }
  533. int get_clocks(void)
  534. {
  535. sys_info_t sys_info;
  536. #ifdef CONFIG_ARCH_MPC8544
  537. volatile ccsr_gur_t *gur = (void *) CONFIG_SYS_MPC85xx_GUTS_ADDR;
  538. #endif
  539. #if defined(CONFIG_CPM2)
  540. volatile ccsr_cpm_t *cpm = (ccsr_cpm_t *)CONFIG_SYS_MPC85xx_CPM_ADDR;
  541. uint sccr, dfbrg;
  542. /* set VCO = 4 * BRG */
  543. cpm->im_cpm_intctl.sccr &= 0xfffffffc;
  544. sccr = cpm->im_cpm_intctl.sccr;
  545. dfbrg = (sccr & SCCR_DFBRG_MSK) >> SCCR_DFBRG_SHIFT;
  546. #endif
  547. get_sys_info (&sys_info);
  548. gd->cpu_clk = sys_info.freq_processor[0];
  549. gd->bus_clk = sys_info.freq_systembus;
  550. gd->mem_clk = sys_info.freq_ddrbus;
  551. gd->arch.lbc_clk = sys_info.freq_localbus;
  552. #ifdef CONFIG_QE
  553. gd->arch.qe_clk = sys_info.freq_qe;
  554. gd->arch.brg_clk = gd->arch.qe_clk / 2;
  555. #endif
  556. /*
  557. * The base clock for I2C depends on the actual SOC. Unfortunately,
  558. * there is no pattern that can be used to determine the frequency, so
  559. * the only choice is to look up the actual SOC number and use the value
  560. * for that SOC. This information is taken from application note
  561. * AN2919.
  562. */
  563. #if defined(CONFIG_ARCH_MPC8540) || defined(CONFIG_ARCH_MPC8541) || \
  564. defined(CONFIG_ARCH_MPC8560) || defined(CONFIG_ARCH_MPC8555) || \
  565. defined(CONFIG_ARCH_P1022)
  566. gd->arch.i2c1_clk = sys_info.freq_systembus;
  567. #elif defined(CONFIG_ARCH_MPC8544)
  568. /*
  569. * On the 8544, the I2C clock is the same as the SEC clock. This can be
  570. * either CCB/2 or CCB/3, depending on the value of cfg_sec_freq. See
  571. * 4.4.3.3 of the 8544 RM. Note that this might actually work for all
  572. * 85xx, but only the 8544 has cfg_sec_freq, so it's unknown if the
  573. * PORDEVSR2_SEC_CFG bit is 0 on all 85xx boards that are not an 8544.
  574. */
  575. if (gur->pordevsr2 & MPC85xx_PORDEVSR2_SEC_CFG)
  576. gd->arch.i2c1_clk = sys_info.freq_systembus / 3;
  577. else
  578. gd->arch.i2c1_clk = sys_info.freq_systembus / 2;
  579. #else
  580. /* Most 85xx SOCs use CCB/2, so this is the default behavior. */
  581. gd->arch.i2c1_clk = sys_info.freq_systembus / 2;
  582. #endif
  583. gd->arch.i2c2_clk = gd->arch.i2c1_clk;
  584. #if defined(CONFIG_FSL_ESDHC)
  585. #if defined(CONFIG_ARCH_MPC8569) || defined(CONFIG_ARCH_P1010)
  586. gd->arch.sdhc_clk = gd->bus_clk;
  587. #else
  588. gd->arch.sdhc_clk = gd->bus_clk / 2;
  589. #endif
  590. #endif /* defined(CONFIG_FSL_ESDHC) */
  591. #if defined(CONFIG_CPM2)
  592. gd->arch.vco_out = 2*sys_info.freq_systembus;
  593. gd->arch.cpm_clk = gd->arch.vco_out / 2;
  594. gd->arch.scc_clk = gd->arch.vco_out / 4;
  595. gd->arch.brg_clk = gd->arch.vco_out / (1 << (2 * (dfbrg + 1)));
  596. #endif
  597. if(gd->cpu_clk != 0) return (0);
  598. else return (1);
  599. }
  600. /********************************************
  601. * get_bus_freq
  602. * return system bus freq in Hz
  603. *********************************************/
  604. ulong get_bus_freq(ulong dummy)
  605. {
  606. return gd->bus_clk;
  607. }
  608. /********************************************
  609. * get_ddr_freq
  610. * return ddr bus freq in Hz
  611. *********************************************/
  612. ulong get_ddr_freq (ulong dummy)
  613. {
  614. return gd->mem_clk;
  615. }