fdt.c 22 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2007-2011 Freescale Semiconductor, Inc.
  4. *
  5. * (C) Copyright 2000
  6. * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  7. */
  8. #include <common.h>
  9. #include <clock_legacy.h>
  10. #include <env.h>
  11. #include <linux/libfdt.h>
  12. #include <fdt_support.h>
  13. #include <asm/processor.h>
  14. #include <linux/ctype.h>
  15. #include <asm/io.h>
  16. #include <asm/fsl_fdt.h>
  17. #include <asm/fsl_portals.h>
  18. #include <fsl_qbman.h>
  19. #include <hwconfig.h>
  20. #ifdef CONFIG_FSL_ESDHC
  21. #include <fsl_esdhc.h>
  22. #endif
  23. #ifdef CONFIG_SYS_DPAA_FMAN
  24. #include <fsl_fman.h>
  25. #endif
  26. DECLARE_GLOBAL_DATA_PTR;
  27. extern void ft_qe_setup(void *blob);
  28. extern void ft_fixup_num_cores(void *blob);
  29. extern void ft_srio_setup(void *blob);
  30. #ifdef CONFIG_MP
  31. #include "mp.h"
  32. void ft_fixup_cpu(void *blob, u64 memory_limit)
  33. {
  34. int off;
  35. phys_addr_t spin_tbl_addr = get_spin_phys_addr();
  36. u32 bootpg = determine_mp_bootpg(NULL);
  37. u32 id = get_my_id();
  38. const char *enable_method;
  39. #if defined(T1040_TDM_QUIRK_CCSR_BASE)
  40. int ret;
  41. int tdm_hwconfig_enabled = 0;
  42. char buffer[HWCONFIG_BUFFER_SIZE] = {0};
  43. #endif
  44. off = fdt_node_offset_by_prop_value(blob, -1, "device_type", "cpu", 4);
  45. while (off != -FDT_ERR_NOTFOUND) {
  46. u32 *reg = (u32 *)fdt_getprop(blob, off, "reg", 0);
  47. if (reg) {
  48. u32 phys_cpu_id = thread_to_core(*reg);
  49. u64 val = phys_cpu_id * SIZE_BOOT_ENTRY + spin_tbl_addr;
  50. val = cpu_to_fdt64(val);
  51. if (*reg == id) {
  52. fdt_setprop_string(blob, off, "status",
  53. "okay");
  54. } else {
  55. fdt_setprop_string(blob, off, "status",
  56. "disabled");
  57. }
  58. if (hold_cores_in_reset(0)) {
  59. #ifdef CONFIG_FSL_CORENET
  60. /* Cores held in reset, use BRR to release */
  61. enable_method = "fsl,brr-holdoff";
  62. #else
  63. /* Cores held in reset, use EEBPCR to release */
  64. enable_method = "fsl,eebpcr-holdoff";
  65. #endif
  66. } else {
  67. /* Cores out of reset and in a spin-loop */
  68. enable_method = "spin-table";
  69. fdt_setprop(blob, off, "cpu-release-addr",
  70. &val, sizeof(val));
  71. }
  72. fdt_setprop_string(blob, off, "enable-method",
  73. enable_method);
  74. } else {
  75. printf ("cpu NULL\n");
  76. }
  77. off = fdt_node_offset_by_prop_value(blob, off,
  78. "device_type", "cpu", 4);
  79. }
  80. #if defined(T1040_TDM_QUIRK_CCSR_BASE)
  81. #define CONFIG_MEM_HOLE_16M 0x1000000
  82. /*
  83. * Extract hwconfig from environment.
  84. * Search for tdm entry in hwconfig.
  85. */
  86. ret = env_get_f("hwconfig", buffer, sizeof(buffer));
  87. if (ret > 0)
  88. tdm_hwconfig_enabled = hwconfig_f("tdm", buffer);
  89. /* Reserve the memory hole created by TDM LAW, so OSes dont use it */
  90. if (tdm_hwconfig_enabled) {
  91. off = fdt_add_mem_rsv(blob, T1040_TDM_QUIRK_CCSR_BASE,
  92. CONFIG_MEM_HOLE_16M);
  93. if (off < 0)
  94. printf("Failed to reserve memory for tdm: %s\n",
  95. fdt_strerror(off));
  96. }
  97. #endif
  98. /* Reserve the boot page so OSes dont use it */
  99. if ((u64)bootpg < memory_limit) {
  100. off = fdt_add_mem_rsv(blob, bootpg, (u64)4096);
  101. if (off < 0)
  102. printf("Failed to reserve memory for bootpg: %s\n",
  103. fdt_strerror(off));
  104. }
  105. #ifndef CONFIG_MPC8xxx_DISABLE_BPTR
  106. /*
  107. * Reserve the default boot page so OSes dont use it.
  108. * The default boot page is always mapped to bootpg above using
  109. * boot page translation.
  110. */
  111. if (0xfffff000ull < memory_limit) {
  112. off = fdt_add_mem_rsv(blob, 0xfffff000ull, (u64)4096);
  113. if (off < 0) {
  114. printf("Failed to reserve memory for 0xfffff000: %s\n",
  115. fdt_strerror(off));
  116. }
  117. }
  118. #endif
  119. /* Reserve spin table page */
  120. if (spin_tbl_addr < memory_limit) {
  121. off = fdt_add_mem_rsv(blob,
  122. (spin_tbl_addr & ~0xffful), 4096);
  123. if (off < 0)
  124. printf("Failed to reserve memory for spin table: %s\n",
  125. fdt_strerror(off));
  126. }
  127. #ifdef CONFIG_DEEP_SLEEP
  128. #ifdef CONFIG_SPL_MMC_BOOT
  129. off = fdt_add_mem_rsv(blob, CONFIG_SYS_MMC_U_BOOT_START,
  130. CONFIG_SYS_MMC_U_BOOT_SIZE);
  131. if (off < 0)
  132. printf("Failed to reserve memory for SD deep sleep: %s\n",
  133. fdt_strerror(off));
  134. #elif defined(CONFIG_SPL_SPI_BOOT)
  135. off = fdt_add_mem_rsv(blob, CONFIG_SYS_SPI_FLASH_U_BOOT_START,
  136. CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE);
  137. if (off < 0)
  138. printf("Failed to reserve memory for SPI deep sleep: %s\n",
  139. fdt_strerror(off));
  140. #endif
  141. #endif
  142. }
  143. #endif
  144. #ifdef CONFIG_SYS_FSL_CPC
  145. static inline void ft_fixup_l3cache(void *blob, int off)
  146. {
  147. u32 line_size, num_ways, size, num_sets;
  148. cpc_corenet_t *cpc = (void *)CONFIG_SYS_FSL_CPC_ADDR;
  149. u32 cfg0 = in_be32(&cpc->cpccfg0);
  150. size = CPC_CFG0_SZ_K(cfg0) * 1024 * CONFIG_SYS_NUM_CPC;
  151. num_ways = CPC_CFG0_NUM_WAYS(cfg0);
  152. line_size = CPC_CFG0_LINE_SZ(cfg0);
  153. num_sets = size / (line_size * num_ways);
  154. fdt_setprop(blob, off, "cache-unified", NULL, 0);
  155. fdt_setprop_cell(blob, off, "cache-block-size", line_size);
  156. fdt_setprop_cell(blob, off, "cache-size", size);
  157. fdt_setprop_cell(blob, off, "cache-sets", num_sets);
  158. fdt_setprop_cell(blob, off, "cache-level", 3);
  159. #ifdef CONFIG_SYS_CACHE_STASHING
  160. fdt_setprop_cell(blob, off, "cache-stash-id", 1);
  161. #endif
  162. }
  163. #else
  164. #define ft_fixup_l3cache(x, y)
  165. #endif
  166. #if defined(CONFIG_L2_CACHE) || \
  167. defined(CONFIG_BACKSIDE_L2_CACHE) || \
  168. defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2)
  169. static inline void ft_fixup_l2cache_compatible(void *blob, int off)
  170. {
  171. int len;
  172. struct cpu_type *cpu = identify_cpu(SVR_SOC_VER(get_svr()));
  173. if (cpu) {
  174. char buf[40];
  175. if (isdigit(cpu->name[0])) {
  176. /* MPCxxxx, where xxxx == 4-digit number */
  177. len = sprintf(buf, "fsl,mpc%s-l2-cache-controller",
  178. cpu->name) + 1;
  179. } else {
  180. /* Pxxxx or Txxxx, where xxxx == 4-digit number */
  181. len = sprintf(buf, "fsl,%c%s-l2-cache-controller",
  182. tolower(cpu->name[0]), cpu->name + 1) + 1;
  183. }
  184. /*
  185. * append "cache" after the NULL character that the previous
  186. * sprintf wrote. This is how a device tree stores multiple
  187. * strings in a property.
  188. */
  189. len += sprintf(buf + len, "cache") + 1;
  190. fdt_setprop(blob, off, "compatible", buf, len);
  191. }
  192. }
  193. #endif
  194. #if defined(CONFIG_L2_CACHE)
  195. /* return size in kilobytes */
  196. static inline u32 l2cache_size(void)
  197. {
  198. volatile ccsr_l2cache_t *l2cache = (void *)CONFIG_SYS_MPC85xx_L2_ADDR;
  199. volatile u32 l2siz_field = (l2cache->l2ctl >> 28) & 0x3;
  200. u32 ver = SVR_SOC_VER(get_svr());
  201. switch (l2siz_field) {
  202. case 0x0:
  203. break;
  204. case 0x1:
  205. if (ver == SVR_8540 || ver == SVR_8560 ||
  206. ver == SVR_8541 || ver == SVR_8555)
  207. return 128;
  208. else
  209. return 256;
  210. break;
  211. case 0x2:
  212. if (ver == SVR_8540 || ver == SVR_8560 ||
  213. ver == SVR_8541 || ver == SVR_8555)
  214. return 256;
  215. else
  216. return 512;
  217. break;
  218. case 0x3:
  219. return 1024;
  220. break;
  221. }
  222. return 0;
  223. }
  224. static inline void ft_fixup_l2cache(void *blob)
  225. {
  226. int off;
  227. u32 *ph;
  228. const u32 line_size = 32;
  229. const u32 num_ways = 8;
  230. const u32 size = l2cache_size() * 1024;
  231. const u32 num_sets = size / (line_size * num_ways);
  232. off = fdt_node_offset_by_prop_value(blob, -1, "device_type", "cpu", 4);
  233. if (off < 0) {
  234. debug("no cpu node fount\n");
  235. return;
  236. }
  237. ph = (u32 *)fdt_getprop(blob, off, "next-level-cache", 0);
  238. if (ph == NULL) {
  239. debug("no next-level-cache property\n");
  240. return ;
  241. }
  242. off = fdt_node_offset_by_phandle(blob, *ph);
  243. if (off < 0) {
  244. printf("%s: %s\n", __func__, fdt_strerror(off));
  245. return ;
  246. }
  247. ft_fixup_l2cache_compatible(blob, off);
  248. fdt_setprop(blob, off, "cache-unified", NULL, 0);
  249. fdt_setprop_cell(blob, off, "cache-block-size", line_size);
  250. fdt_setprop_cell(blob, off, "cache-size", size);
  251. fdt_setprop_cell(blob, off, "cache-sets", num_sets);
  252. fdt_setprop_cell(blob, off, "cache-level", 2);
  253. /* we dont bother w/L3 since no platform of this type has one */
  254. }
  255. #elif defined(CONFIG_BACKSIDE_L2_CACHE) || \
  256. defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2)
  257. static inline void ft_fixup_l2cache(void *blob)
  258. {
  259. int off, l2_off, l3_off = -1;
  260. u32 *ph;
  261. #ifdef CONFIG_BACKSIDE_L2_CACHE
  262. u32 l2cfg0 = mfspr(SPRN_L2CFG0);
  263. #else
  264. struct ccsr_cluster_l2 *l2cache =
  265. (struct ccsr_cluster_l2 __iomem *)(CONFIG_SYS_FSL_CLUSTER_1_L2);
  266. u32 l2cfg0 = in_be32(&l2cache->l2cfg0);
  267. #endif
  268. u32 size, line_size, num_ways, num_sets;
  269. int has_l2 = 1;
  270. /* P2040/P2040E has no L2, so dont set any L2 props */
  271. if (SVR_SOC_VER(get_svr()) == SVR_P2040)
  272. has_l2 = 0;
  273. size = (l2cfg0 & 0x3fff) * 64 * 1024;
  274. num_ways = ((l2cfg0 >> 14) & 0x1f) + 1;
  275. line_size = (((l2cfg0 >> 23) & 0x3) + 1) * 32;
  276. num_sets = size / (line_size * num_ways);
  277. off = fdt_node_offset_by_prop_value(blob, -1, "device_type", "cpu", 4);
  278. while (off != -FDT_ERR_NOTFOUND) {
  279. ph = (u32 *)fdt_getprop(blob, off, "next-level-cache", 0);
  280. if (ph == NULL) {
  281. debug("no next-level-cache property\n");
  282. goto next;
  283. }
  284. l2_off = fdt_node_offset_by_phandle(blob, *ph);
  285. if (l2_off < 0) {
  286. printf("%s: %s\n", __func__, fdt_strerror(off));
  287. goto next;
  288. }
  289. if (has_l2) {
  290. #ifdef CONFIG_SYS_CACHE_STASHING
  291. u32 *reg = (u32 *)fdt_getprop(blob, off, "reg", 0);
  292. #if defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && defined(CONFIG_E6500)
  293. /* Only initialize every eighth thread */
  294. if (reg && !((*reg) % 8)) {
  295. fdt_setprop_cell(blob, l2_off, "cache-stash-id",
  296. (*reg / 4) + 32 + 1);
  297. }
  298. #else
  299. if (reg) {
  300. fdt_setprop_cell(blob, l2_off, "cache-stash-id",
  301. (*reg * 2) + 32 + 1);
  302. }
  303. #endif
  304. #endif
  305. fdt_setprop(blob, l2_off, "cache-unified", NULL, 0);
  306. fdt_setprop_cell(blob, l2_off, "cache-block-size",
  307. line_size);
  308. fdt_setprop_cell(blob, l2_off, "cache-size", size);
  309. fdt_setprop_cell(blob, l2_off, "cache-sets", num_sets);
  310. fdt_setprop_cell(blob, l2_off, "cache-level", 2);
  311. ft_fixup_l2cache_compatible(blob, l2_off);
  312. }
  313. if (l3_off < 0) {
  314. ph = (u32 *)fdt_getprop(blob, l2_off, "next-level-cache", 0);
  315. if (ph == NULL) {
  316. debug("no next-level-cache property\n");
  317. goto next;
  318. }
  319. l3_off = *ph;
  320. }
  321. next:
  322. off = fdt_node_offset_by_prop_value(blob, off,
  323. "device_type", "cpu", 4);
  324. }
  325. if (l3_off > 0) {
  326. l3_off = fdt_node_offset_by_phandle(blob, l3_off);
  327. if (l3_off < 0) {
  328. printf("%s: %s\n", __func__, fdt_strerror(off));
  329. return ;
  330. }
  331. ft_fixup_l3cache(blob, l3_off);
  332. }
  333. }
  334. #else
  335. #define ft_fixup_l2cache(x)
  336. #endif
  337. static inline void ft_fixup_cache(void *blob)
  338. {
  339. int off;
  340. off = fdt_node_offset_by_prop_value(blob, -1, "device_type", "cpu", 4);
  341. while (off != -FDT_ERR_NOTFOUND) {
  342. u32 l1cfg0 = mfspr(SPRN_L1CFG0);
  343. u32 l1cfg1 = mfspr(SPRN_L1CFG1);
  344. u32 isize, iline_size, inum_sets, inum_ways;
  345. u32 dsize, dline_size, dnum_sets, dnum_ways;
  346. /* d-side config */
  347. dsize = (l1cfg0 & 0x7ff) * 1024;
  348. dnum_ways = ((l1cfg0 >> 11) & 0xff) + 1;
  349. dline_size = (((l1cfg0 >> 23) & 0x3) + 1) * 32;
  350. dnum_sets = dsize / (dline_size * dnum_ways);
  351. fdt_setprop_cell(blob, off, "d-cache-block-size", dline_size);
  352. fdt_setprop_cell(blob, off, "d-cache-size", dsize);
  353. fdt_setprop_cell(blob, off, "d-cache-sets", dnum_sets);
  354. #ifdef CONFIG_SYS_CACHE_STASHING
  355. {
  356. u32 *reg = (u32 *)fdt_getprop(blob, off, "reg", 0);
  357. if (reg)
  358. fdt_setprop_cell(blob, off, "cache-stash-id",
  359. (*reg * 2) + 32 + 0);
  360. }
  361. #endif
  362. /* i-side config */
  363. isize = (l1cfg1 & 0x7ff) * 1024;
  364. inum_ways = ((l1cfg1 >> 11) & 0xff) + 1;
  365. iline_size = (((l1cfg1 >> 23) & 0x3) + 1) * 32;
  366. inum_sets = isize / (iline_size * inum_ways);
  367. fdt_setprop_cell(blob, off, "i-cache-block-size", iline_size);
  368. fdt_setprop_cell(blob, off, "i-cache-size", isize);
  369. fdt_setprop_cell(blob, off, "i-cache-sets", inum_sets);
  370. off = fdt_node_offset_by_prop_value(blob, off,
  371. "device_type", "cpu", 4);
  372. }
  373. ft_fixup_l2cache(blob);
  374. }
  375. void fdt_add_enet_stashing(void *fdt)
  376. {
  377. do_fixup_by_compat(fdt, "gianfar", "bd-stash", NULL, 0, 1);
  378. do_fixup_by_compat_u32(fdt, "gianfar", "rx-stash-len", 96, 1);
  379. do_fixup_by_compat_u32(fdt, "gianfar", "rx-stash-idx", 0, 1);
  380. do_fixup_by_compat(fdt, "fsl,etsec2", "bd-stash", NULL, 0, 1);
  381. do_fixup_by_compat_u32(fdt, "fsl,etsec2", "rx-stash-len", 96, 1);
  382. do_fixup_by_compat_u32(fdt, "fsl,etsec2", "rx-stash-idx", 0, 1);
  383. }
  384. #if defined(CONFIG_SYS_DPAA_FMAN) || defined(CONFIG_SYS_DPAA_PME)
  385. #ifdef CONFIG_SYS_DPAA_FMAN
  386. static void ft_fixup_clks(void *blob, const char *compat, u32 offset,
  387. unsigned long freq)
  388. {
  389. phys_addr_t phys = offset + CONFIG_SYS_CCSRBAR_PHYS;
  390. int off = fdt_node_offset_by_compat_reg(blob, compat, phys);
  391. if (off >= 0) {
  392. off = fdt_setprop_cell(blob, off, "clock-frequency", freq);
  393. if (off > 0)
  394. printf("WARNING enable to set clock-frequency "
  395. "for %s: %s\n", compat, fdt_strerror(off));
  396. }
  397. }
  398. #endif
  399. static void ft_fixup_dpaa_clks(void *blob)
  400. {
  401. sys_info_t sysinfo;
  402. get_sys_info(&sysinfo);
  403. #ifdef CONFIG_SYS_DPAA_FMAN
  404. ft_fixup_clks(blob, "fsl,fman", CONFIG_SYS_FSL_FM1_OFFSET,
  405. sysinfo.freq_fman[0]);
  406. #if (CONFIG_SYS_NUM_FMAN == 2)
  407. ft_fixup_clks(blob, "fsl,fman", CONFIG_SYS_FSL_FM2_OFFSET,
  408. sysinfo.freq_fman[1]);
  409. #endif
  410. #endif
  411. #ifdef CONFIG_SYS_DPAA_QBMAN
  412. do_fixup_by_compat_u32(blob, "fsl,qman",
  413. "clock-frequency", sysinfo.freq_qman, 1);
  414. #endif
  415. #ifdef CONFIG_SYS_DPAA_PME
  416. do_fixup_by_compat_u32(blob, "fsl,pme",
  417. "clock-frequency", sysinfo.freq_pme, 1);
  418. #endif
  419. }
  420. #else
  421. #define ft_fixup_dpaa_clks(x)
  422. #endif
  423. #ifdef CONFIG_QE
  424. static void ft_fixup_qe_snum(void *blob)
  425. {
  426. unsigned int svr;
  427. svr = mfspr(SPRN_SVR);
  428. if (SVR_SOC_VER(svr) == SVR_8569) {
  429. if(IS_SVR_REV(svr, 1, 0))
  430. do_fixup_by_compat_u32(blob, "fsl,qe",
  431. "fsl,qe-num-snums", 46, 1);
  432. else
  433. do_fixup_by_compat_u32(blob, "fsl,qe",
  434. "fsl,qe-num-snums", 76, 1);
  435. }
  436. }
  437. #endif
  438. #if defined(CONFIG_ARCH_P4080)
  439. static void fdt_fixup_usb(void *fdt)
  440. {
  441. ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  442. u32 rcwsr11 = in_be32(&gur->rcwsr[11]);
  443. int off;
  444. off = fdt_node_offset_by_compatible(fdt, -1, "fsl,mpc85xx-usb2-mph");
  445. if ((rcwsr11 & FSL_CORENET_RCWSR11_EC1) !=
  446. FSL_CORENET_RCWSR11_EC1_FM1_USB1)
  447. fdt_status_disabled(fdt, off);
  448. off = fdt_node_offset_by_compatible(fdt, -1, "fsl,mpc85xx-usb2-dr");
  449. if ((rcwsr11 & FSL_CORENET_RCWSR11_EC2) !=
  450. FSL_CORENET_RCWSR11_EC2_USB2)
  451. fdt_status_disabled(fdt, off);
  452. }
  453. #else
  454. #define fdt_fixup_usb(x)
  455. #endif
  456. #if defined(CONFIG_ARCH_T2080) || defined(CONFIG_ARCH_T4240) || \
  457. defined(CONFIG_ARCH_T4160)
  458. void fdt_fixup_dma3(void *blob)
  459. {
  460. /* the 3rd DMA is not functional if SRIO2 is chosen */
  461. int nodeoff;
  462. ccsr_gur_t __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  463. #define CONFIG_SYS_ELO3_DMA3 (0xffe000000 + 0x102300)
  464. #if defined(CONFIG_ARCH_T2080)
  465. u32 srds_prtcl_s2 = in_be32(&gur->rcwsr[4]) &
  466. FSL_CORENET2_RCWSR4_SRDS2_PRTCL;
  467. srds_prtcl_s2 >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT;
  468. switch (srds_prtcl_s2) {
  469. case 0x29:
  470. case 0x2d:
  471. case 0x2e:
  472. #elif defined(CONFIG_ARCH_T4240) || defined(CONFIG_ARCH_T4160)
  473. u32 srds_prtcl_s4 = in_be32(&gur->rcwsr[4]) &
  474. FSL_CORENET2_RCWSR4_SRDS4_PRTCL;
  475. srds_prtcl_s4 >>= FSL_CORENET2_RCWSR4_SRDS4_PRTCL_SHIFT;
  476. switch (srds_prtcl_s4) {
  477. case 6:
  478. case 8:
  479. case 14:
  480. case 16:
  481. #endif
  482. nodeoff = fdt_node_offset_by_compat_reg(blob, "fsl,elo3-dma",
  483. CONFIG_SYS_ELO3_DMA3);
  484. if (nodeoff > 0)
  485. fdt_status_disabled(blob, nodeoff);
  486. else
  487. printf("WARNING: unable to disable dma3\n");
  488. break;
  489. default:
  490. break;
  491. }
  492. }
  493. #else
  494. #define fdt_fixup_dma3(x)
  495. #endif
  496. #if defined(CONFIG_ARCH_T1040)
  497. static void fdt_fixup_l2_switch(void *blob)
  498. {
  499. uchar l2swaddr[6];
  500. int node;
  501. /* The l2switch node from device-tree has
  502. * compatible string "vitesse-9953" */
  503. node = fdt_node_offset_by_compatible(blob, -1, "vitesse-9953");
  504. if (node == -FDT_ERR_NOTFOUND)
  505. /* no l2switch node has been found */
  506. return;
  507. /* Get MAC address for the l2switch from "l2switchaddr"*/
  508. if (!eth_env_get_enetaddr("l2switchaddr", l2swaddr)) {
  509. printf("Warning: MAC address for l2switch not found\n");
  510. memset(l2swaddr, 0, sizeof(l2swaddr));
  511. }
  512. /* Add MAC address to l2switch node */
  513. fdt_setprop(blob, node, "local-mac-address", l2swaddr,
  514. sizeof(l2swaddr));
  515. }
  516. #else
  517. #define fdt_fixup_l2_switch(x)
  518. #endif
  519. void ft_cpu_setup(void *blob, bd_t *bd)
  520. {
  521. int off;
  522. int val;
  523. int len;
  524. sys_info_t sysinfo;
  525. /* delete crypto node if not on an E-processor */
  526. if (!IS_E_PROCESSOR(get_svr()))
  527. fdt_fixup_crypto_node(blob, 0);
  528. #if CONFIG_SYS_FSL_SEC_COMPAT >= 4
  529. else {
  530. ccsr_sec_t __iomem *sec;
  531. sec = (void __iomem *)CONFIG_SYS_FSL_SEC_ADDR;
  532. fdt_fixup_crypto_node(blob, sec_in32(&sec->secvid_ms));
  533. }
  534. #endif
  535. fdt_add_enet_stashing(blob);
  536. #ifndef CONFIG_FSL_TBCLK_EXTRA_DIV
  537. #define CONFIG_FSL_TBCLK_EXTRA_DIV 1
  538. #endif
  539. do_fixup_by_prop_u32(blob, "device_type", "cpu", 4,
  540. "timebase-frequency", get_tbclk() / CONFIG_FSL_TBCLK_EXTRA_DIV,
  541. 1);
  542. do_fixup_by_prop_u32(blob, "device_type", "cpu", 4,
  543. "bus-frequency", bd->bi_busfreq, 1);
  544. get_sys_info(&sysinfo);
  545. off = fdt_node_offset_by_prop_value(blob, -1, "device_type", "cpu", 4);
  546. while (off != -FDT_ERR_NOTFOUND) {
  547. u32 *reg = (u32 *)fdt_getprop(blob, off, "reg", &len);
  548. val = cpu_to_fdt32(sysinfo.freq_processor[(*reg) / (len / 4)]);
  549. fdt_setprop(blob, off, "clock-frequency", &val, 4);
  550. off = fdt_node_offset_by_prop_value(blob, off, "device_type",
  551. "cpu", 4);
  552. }
  553. do_fixup_by_prop_u32(blob, "device_type", "soc", 4,
  554. "bus-frequency", bd->bi_busfreq, 1);
  555. #ifdef CONFIG_QE
  556. ft_qe_setup(blob);
  557. ft_fixup_qe_snum(blob);
  558. #endif
  559. #ifdef CONFIG_SYS_DPAA_FMAN
  560. fdt_fixup_fman_firmware(blob);
  561. #endif
  562. #ifdef CONFIG_SYS_NS16550
  563. do_fixup_by_compat_u32(blob, "ns16550",
  564. "clock-frequency", CONFIG_SYS_NS16550_CLK, 1);
  565. #endif
  566. #ifdef CONFIG_CPM2
  567. do_fixup_by_compat_u32(blob, "fsl,cpm2-scc-uart",
  568. "current-speed", gd->baudrate, 1);
  569. do_fixup_by_compat_u32(blob, "fsl,cpm2-brg",
  570. "clock-frequency", bd->bi_brgfreq, 1);
  571. #endif
  572. #ifdef CONFIG_FSL_CORENET
  573. do_fixup_by_compat_u32(blob, "fsl,qoriq-clockgen-1.0",
  574. "clock-frequency", CONFIG_SYS_CLK_FREQ, 1);
  575. do_fixup_by_compat_u32(blob, "fsl,qoriq-clockgen-2.0",
  576. "clock-frequency", CONFIG_SYS_CLK_FREQ, 1);
  577. do_fixup_by_compat_u32(blob, "fsl,mpic",
  578. "clock-frequency", get_bus_freq(0)/2, 1);
  579. #else
  580. do_fixup_by_compat_u32(blob, "fsl,mpic",
  581. "clock-frequency", get_bus_freq(0), 1);
  582. #endif
  583. fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize);
  584. #ifdef CONFIG_MP
  585. ft_fixup_cpu(blob, (u64)bd->bi_memstart + (u64)bd->bi_memsize);
  586. ft_fixup_num_cores(blob);
  587. #endif
  588. ft_fixup_cache(blob);
  589. #if defined(CONFIG_FSL_ESDHC)
  590. fdt_fixup_esdhc(blob, bd);
  591. #endif
  592. ft_fixup_dpaa_clks(blob);
  593. #if defined(CONFIG_SYS_BMAN_MEM_PHYS)
  594. fdt_portal(blob, "fsl,bman-portal", "bman-portals",
  595. (u64)CONFIG_SYS_BMAN_MEM_PHYS,
  596. CONFIG_SYS_BMAN_MEM_SIZE);
  597. fdt_fixup_bportals(blob);
  598. #endif
  599. #if defined(CONFIG_SYS_QMAN_MEM_PHYS)
  600. fdt_portal(blob, "fsl,qman-portal", "qman-portals",
  601. (u64)CONFIG_SYS_QMAN_MEM_PHYS,
  602. CONFIG_SYS_QMAN_MEM_SIZE);
  603. fdt_fixup_qportals(blob);
  604. #endif
  605. #ifdef CONFIG_SYS_SRIO
  606. ft_srio_setup(blob);
  607. #endif
  608. /*
  609. * system-clock = CCB clock/2
  610. * Here gd->bus_clk = CCB clock
  611. * We are using the system clock as 1588 Timer reference
  612. * clock source select
  613. */
  614. do_fixup_by_compat_u32(blob, "fsl,gianfar-ptp-timer",
  615. "timer-frequency", gd->bus_clk/2, 1);
  616. /*
  617. * clock-freq should change to clock-frequency and
  618. * flexcan-v1.0 should change to p1010-flexcan respectively
  619. * in the future.
  620. */
  621. do_fixup_by_compat_u32(blob, "fsl,flexcan-v1.0",
  622. "clock_freq", gd->bus_clk/2, 1);
  623. do_fixup_by_compat_u32(blob, "fsl,flexcan-v1.0",
  624. "clock-frequency", gd->bus_clk/2, 1);
  625. do_fixup_by_compat_u32(blob, "fsl,p1010-flexcan",
  626. "clock-frequency", gd->bus_clk/2, 1);
  627. fdt_fixup_usb(blob);
  628. fdt_fixup_l2_switch(blob);
  629. fdt_fixup_dma3(blob);
  630. }
  631. /*
  632. * For some CCSR devices, we only have the virtual address, not the physical
  633. * address. This is because we map CCSR as a whole, so we typically don't need
  634. * a macro for the physical address of any device within CCSR. In this case,
  635. * we calculate the physical address of that device using it's the difference
  636. * between the virtual address of the device and the virtual address of the
  637. * beginning of CCSR.
  638. */
  639. #define CCSR_VIRT_TO_PHYS(x) \
  640. (CONFIG_SYS_CCSRBAR_PHYS + ((x) - CONFIG_SYS_CCSRBAR))
  641. static void msg(const char *name, uint64_t uaddr, uint64_t daddr)
  642. {
  643. printf("Warning: U-Boot configured %s at address %llx,\n"
  644. "but the device tree has it at %llx\n", name, uaddr, daddr);
  645. }
  646. /*
  647. * Verify the device tree
  648. *
  649. * This function compares several CONFIG_xxx macros that contain physical
  650. * addresses with the corresponding nodes in the device tree, to see if
  651. * the physical addresses are all correct. For example, if
  652. * CONFIG_SYS_NS16550_COM1 is defined, then it contains the virtual address
  653. * of the first UART. We convert this to a physical address and compare
  654. * that with the physical address of the first ns16550-compatible node
  655. * in the device tree. If they don't match, then we display a warning.
  656. *
  657. * Returns 1 on success, 0 on failure
  658. */
  659. int ft_verify_fdt(void *fdt)
  660. {
  661. uint64_t addr = 0;
  662. int aliases;
  663. int off;
  664. /* First check the CCSR base address */
  665. off = fdt_node_offset_by_prop_value(fdt, -1, "device_type", "soc", 4);
  666. if (off > 0) {
  667. int size;
  668. u32 naddr;
  669. const fdt32_t *prop;
  670. naddr = fdt_address_cells(fdt, off);
  671. prop = fdt_getprop(fdt, off, "ranges", &size);
  672. addr = fdt_translate_address(fdt, off, prop + naddr);
  673. }
  674. if (!addr) {
  675. printf("Warning: could not determine base CCSR address in "
  676. "device tree\n");
  677. /* No point in checking anything else */
  678. return 0;
  679. }
  680. if (addr != CONFIG_SYS_CCSRBAR_PHYS) {
  681. msg("CCSR", CONFIG_SYS_CCSRBAR_PHYS, addr);
  682. /* No point in checking anything else */
  683. return 0;
  684. }
  685. /*
  686. * Check some nodes via aliases. We assume that U-Boot and the device
  687. * tree enumerate the devices equally. E.g. the first serial port in
  688. * U-Boot is the same as "serial0" in the device tree.
  689. */
  690. aliases = fdt_path_offset(fdt, "/aliases");
  691. if (aliases > 0) {
  692. #ifdef CONFIG_SYS_NS16550_COM1
  693. if (!fdt_verify_alias_address(fdt, aliases, "serial0",
  694. CCSR_VIRT_TO_PHYS(CONFIG_SYS_NS16550_COM1)))
  695. return 0;
  696. #endif
  697. #ifdef CONFIG_SYS_NS16550_COM2
  698. if (!fdt_verify_alias_address(fdt, aliases, "serial1",
  699. CCSR_VIRT_TO_PHYS(CONFIG_SYS_NS16550_COM2)))
  700. return 0;
  701. #endif
  702. }
  703. /*
  704. * The localbus node is typically a root node, even though the lbc
  705. * controller is part of CCSR. If we were to put the lbc node under
  706. * the SOC node, then the 'ranges' property in the lbc node would
  707. * translate through the 'ranges' property of the parent SOC node, and
  708. * we don't want that. Since it's a separate node, it's possible for
  709. * the 'reg' property to be wrong, so check it here. For now, we
  710. * only check for "fsl,elbc" nodes.
  711. */
  712. #ifdef CONFIG_SYS_LBC_ADDR
  713. off = fdt_node_offset_by_compatible(fdt, -1, "fsl,elbc");
  714. if (off > 0) {
  715. const fdt32_t *reg = fdt_getprop(fdt, off, "reg", NULL);
  716. if (reg) {
  717. uint64_t uaddr = CCSR_VIRT_TO_PHYS(CONFIG_SYS_LBC_ADDR);
  718. addr = fdt_translate_address(fdt, off, reg);
  719. if (uaddr != addr) {
  720. msg("the localbus", uaddr, addr);
  721. return 0;
  722. }
  723. }
  724. }
  725. #endif
  726. return 1;
  727. }
  728. void fdt_del_diu(void *blob)
  729. {
  730. int nodeoff = 0;
  731. while ((nodeoff = fdt_node_offset_by_compatible(blob, 0,
  732. "fsl,diu")) >= 0) {
  733. fdt_del_node(blob, nodeoff);
  734. }
  735. }