clk.c 17 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2019 Rosy Song <rosysong@rosinson.com>
  4. */
  5. #include <common.h>
  6. #include <clock_legacy.h>
  7. #include <asm/io.h>
  8. #include <asm/addrspace.h>
  9. #include <asm/types.h>
  10. #include <mach/ar71xx_regs.h>
  11. #include <mach/ath79.h>
  12. #include <wait_bit.h>
  13. #define PLL_SRIF_DPLL2_KI_LSB 29
  14. #define PLL_SRIF_DPLL2_KI_MASK 0x60000000
  15. #define PLL_SRIF_DPLL2_KI_SET(x) \
  16. (((x) << PLL_SRIF_DPLL2_KI_LSB) & PLL_SRIF_DPLL2_KI_MASK)
  17. #define PLL_SRIF_DPLL2_KD_LSB 25
  18. #define PLL_SRIF_DPLL2_KD_MASK 0x1e000000
  19. #define PLL_SRIF_DPLL2_KD_SET(x) \
  20. (((x) << PLL_SRIF_DPLL2_KD_LSB) & PLL_SRIF_DPLL2_KD_MASK)
  21. #define PLL_SRIF_DPLL2_PLL_PWD_LSB 22
  22. #define PLL_SRIF_DPLL2_PLL_PWD_MASK 0x00400000
  23. #define PLL_SRIF_DPLL2_PLL_PWD_SET(x) \
  24. (((x) << PLL_SRIF_DPLL2_PLL_PWD_LSB) & PLL_SRIF_DPLL2_PLL_PWD_MASK)
  25. #define PLL_SRIF_DPLL2_OUTDIV_LSB 19
  26. #define PLL_SRIF_DPLL2_OUTDIV_MASK 0x00380000
  27. #define PLL_SRIF_DPLL2_OUTDIV_SET(x) \
  28. (((x) << PLL_SRIF_DPLL2_OUTDIV_LSB) & PLL_SRIF_DPLL2_OUTDIV_MASK)
  29. #define PLL_SRIF_DPLL2_PHASE_SHIFT_LSB 12
  30. #define PLL_SRIF_DPLL2_PHASE_SHIFT_MASK 0x0007f000
  31. #define PLL_SRIF_DPLL2_PHASE_SHIFT_SET(x) \
  32. (((x) << PLL_SRIF_DPLL2_PHASE_SHIFT_LSB) & PLL_SRIF_DPLL2_PHASE_SHIFT_MASK)
  33. #define CPU_PLL_CONFIG_PLLPWD_LSB 30
  34. #define CPU_PLL_CONFIG_PLLPWD_MASK 0x40000000
  35. #define CPU_PLL_CONFIG_PLLPWD_SET(x) \
  36. (((x) << CPU_PLL_CONFIG_PLLPWD_LSB) & CPU_PLL_CONFIG_PLLPWD_MASK)
  37. #define CPU_PLL_CONFIG_OUTDIV_LSB 19
  38. #define CPU_PLL_CONFIG_OUTDIV_MASK 0x00380000
  39. #define CPU_PLL_CONFIG_OUTDIV_SET(x) \
  40. (((x) << CPU_PLL_CONFIG_OUTDIV_LSB) & CPU_PLL_CONFIG_OUTDIV_MASK)
  41. #define CPU_PLL_CONFIG_RANGE_LSB 17
  42. #define CPU_PLL_CONFIG_RANGE_MASK 0x00060000
  43. #define CPU_PLL_CONFIG_RANGE_SET(x) \
  44. (((x) << CPU_PLL_CONFIG_RANGE_LSB) & CPU_PLL_CONFIG_RANGE_MASK)
  45. #define CPU_PLL_CONFIG_REFDIV_LSB 12
  46. #define CPU_PLL_CONFIG_REFDIV_MASK 0x0001f000
  47. #define CPU_PLL_CONFIG_REFDIV_SET(x) \
  48. (((x) << CPU_PLL_CONFIG_REFDIV_LSB) & CPU_PLL_CONFIG_REFDIV_MASK)
  49. #define CPU_PLL_CONFIG1_NINT_LSB 18
  50. #define CPU_PLL_CONFIG1_NINT_MASK 0x07fc0000
  51. #define CPU_PLL_CONFIG1_NINT_SET(x) \
  52. (((x) << CPU_PLL_CONFIG1_NINT_LSB) & CPU_PLL_CONFIG1_NINT_MASK)
  53. #define CPU_PLL_DITHER1_DITHER_EN_LSB 31
  54. #define CPU_PLL_DITHER1_DITHER_EN_MASK 0x80000000
  55. #define CPU_PLL_DITHER1_DITHER_EN_SET(x) \
  56. (((x) << CPU_PLL_DITHER1_DITHER_EN_LSB) & CPU_PLL_DITHER1_DITHER_EN_MASK)
  57. #define CPU_PLL_DITHER1_UPDATE_COUNT_LSB 24
  58. #define CPU_PLL_DITHER1_UPDATE_COUNT_MASK 0x3f000000
  59. #define CPU_PLL_DITHER1_UPDATE_COUNT_SET(x) \
  60. (((x) << CPU_PLL_DITHER1_UPDATE_COUNT_LSB) & CPU_PLL_DITHER1_UPDATE_COUNT_MASK)
  61. #define CPU_PLL_DITHER1_NFRAC_STEP_LSB 18
  62. #define CPU_PLL_DITHER1_NFRAC_STEP_MASK 0x00fc0000
  63. #define CPU_PLL_DITHER1_NFRAC_STEP_SET(x) \
  64. (((x) << CPU_PLL_DITHER1_NFRAC_STEP_LSB) & CPU_PLL_DITHER1_NFRAC_STEP_MASK)
  65. #define CPU_PLL_DITHER1_NFRAC_MIN_LSB 0
  66. #define CPU_PLL_DITHER1_NFRAC_MIN_MASK 0x0003ffff
  67. #define CPU_PLL_DITHER1_NFRAC_MIN_SET(x) \
  68. (((x) << CPU_PLL_DITHER1_NFRAC_MIN_LSB) & CPU_PLL_DITHER1_NFRAC_MIN_MASK)
  69. #define CPU_PLL_DITHER2_NFRAC_MAX_LSB 0
  70. #define CPU_PLL_DITHER2_NFRAC_MAX_MASK 0x0003ffff
  71. #define CPU_PLL_DITHER2_NFRAC_MAX_SET(x) \
  72. (((x) << CPU_PLL_DITHER2_NFRAC_MAX_LSB) & CPU_PLL_DITHER2_NFRAC_MAX_MASK)
  73. #define DDR_PLL_CONFIG_PLLPWD_LSB 30
  74. #define DDR_PLL_CONFIG_PLLPWD_MASK 0x40000000
  75. #define DDR_PLL_CONFIG_PLLPWD_SET(x) \
  76. (((x) << DDR_PLL_CONFIG_PLLPWD_LSB) & DDR_PLL_CONFIG_PLLPWD_MASK)
  77. #define DDR_PLL_CONFIG_OUTDIV_LSB 23
  78. #define DDR_PLL_CONFIG_OUTDIV_MASK 0x03800000
  79. #define DDR_PLL_CONFIG_OUTDIV_SET(x) \
  80. (((x) << DDR_PLL_CONFIG_OUTDIV_LSB) & DDR_PLL_CONFIG_OUTDIV_MASK)
  81. #define DDR_PLL_CONFIG_RANGE_LSB 21
  82. #define DDR_PLL_CONFIG_RANGE_MASK 0x00600000
  83. #define DDR_PLL_CONFIG_RANGE_SET(x) \
  84. (((x) << DDR_PLL_CONFIG_RANGE_LSB) & DDR_PLL_CONFIG_RANGE_MASK)
  85. #define DDR_PLL_CONFIG_REFDIV_LSB 16
  86. #define DDR_PLL_CONFIG_REFDIV_MASK 0x001f0000
  87. #define DDR_PLL_CONFIG_REFDIV_SET(x) \
  88. (((x) << DDR_PLL_CONFIG_REFDIV_LSB) & DDR_PLL_CONFIG_REFDIV_MASK)
  89. #define DDR_PLL_CONFIG1_NINT_LSB 18
  90. #define DDR_PLL_CONFIG1_NINT_MASK 0x07fc0000
  91. #define DDR_PLL_CONFIG1_NINT_SET(x) \
  92. (((x) << DDR_PLL_CONFIG1_NINT_LSB) & DDR_PLL_CONFIG1_NINT_MASK)
  93. #define DDR_PLL_DITHER1_DITHER_EN_LSB 31
  94. #define DDR_PLL_DITHER1_DITHER_EN_MASK 0x80000000
  95. #define DDR_PLL_DITHER1_DITHER_EN_SET(x) \
  96. (((x) << DDR_PLL_DITHER1_DITHER_EN_LSB) & DDR_PLL_DITHER1_DITHER_EN_MASK)
  97. #define DDR_PLL_DITHER1_UPDATE_COUNT_LSB 27
  98. #define DDR_PLL_DITHER1_UPDATE_COUNT_MASK 0x78000000
  99. #define DDR_PLL_DITHER1_UPDATE_COUNT_SET(x) \
  100. (((x) << DDR_PLL_DITHER1_UPDATE_COUNT_LSB) & DDR_PLL_DITHER1_UPDATE_COUNT_MASK)
  101. #define DDR_PLL_DITHER1_NFRAC_STEP_LSB 20
  102. #define DDR_PLL_DITHER1_NFRAC_STEP_MASK 0x07f00000
  103. #define DDR_PLL_DITHER1_NFRAC_STEP_SET(x) \
  104. (((x) << DDR_PLL_DITHER1_NFRAC_STEP_LSB) & DDR_PLL_DITHER1_NFRAC_STEP_MASK)
  105. #define DDR_PLL_DITHER1_NFRAC_MIN_LSB 0
  106. #define DDR_PLL_DITHER1_NFRAC_MIN_MASK 0x0003ffff
  107. #define DDR_PLL_DITHER1_NFRAC_MIN_SET(x) \
  108. (((x) << DDR_PLL_DITHER1_NFRAC_MIN_LSB) & DDR_PLL_DITHER1_NFRAC_MIN_MASK)
  109. #define DDR_PLL_DITHER2_NFRAC_MAX_LSB 0
  110. #define DDR_PLL_DITHER2_NFRAC_MAX_MASK 0x0003ffff
  111. #define DDR_PLL_DITHER2_NFRAC_MAX_SET(x) \
  112. (((x) << DDR_PLL_DITHER2_NFRAC_MAX_LSB) & DDR_PLL_DITHER2_NFRAC_MAX_MASK)
  113. #define CPU_DDR_CLOCK_CONTROL_AHBCLK_FROM_DDRPLL_LSB 24
  114. #define CPU_DDR_CLOCK_CONTROL_AHBCLK_FROM_DDRPLL_MASK 0x01000000
  115. #define CPU_DDR_CLOCK_CONTROL_AHBCLK_FROM_DDRPLL_SET(x) \
  116. (((x) << CPU_DDR_CLOCK_CONTROL_AHBCLK_FROM_DDRPLL_LSB) & CPU_DDR_CLOCK_CONTROL_AHBCLK_FROM_DDRPLL_MASK)
  117. #define CPU_DDR_CLOCK_CONTROL_CPU_DDR_CLK_FROM_CPUPLL_LSB 21
  118. #define CPU_DDR_CLOCK_CONTROL_CPU_DDR_CLK_FROM_CPUPLL_MASK 0x00200000
  119. #define CPU_DDR_CLOCK_CONTROL_CPU_DDR_CLK_FROM_CPUPLL_SET(x) \
  120. (((x) << CPU_DDR_CLOCK_CONTROL_CPU_DDR_CLK_FROM_CPUPLL_LSB) & CPU_DDR_CLOCK_CONTROL_CPU_DDR_CLK_FROM_CPUPLL_MASK)
  121. #define CPU_DDR_CLOCK_CONTROL_CPU_DDR_CLK_FROM_DDRPLL_LSB 20
  122. #define CPU_DDR_CLOCK_CONTROL_CPU_DDR_CLK_FROM_DDRPLL_MASK 0x00100000
  123. #define CPU_DDR_CLOCK_CONTROL_CPU_DDR_CLK_FROM_DDRPLL_SET(x) \
  124. (((x) << CPU_DDR_CLOCK_CONTROL_CPU_DDR_CLK_FROM_DDRPLL_LSB) & CPU_DDR_CLOCK_CONTROL_CPU_DDR_CLK_FROM_DDRPLL_MASK)
  125. #define CPU_DDR_CLOCK_CONTROL_AHB_POST_DIV_LSB 15
  126. #define CPU_DDR_CLOCK_CONTROL_AHB_POST_DIV_MASK 0x000f8000
  127. #define CPU_DDR_CLOCK_CONTROL_AHB_POST_DIV_SET(x) \
  128. (((x) << CPU_DDR_CLOCK_CONTROL_AHB_POST_DIV_LSB) & CPU_DDR_CLOCK_CONTROL_AHB_POST_DIV_MASK)
  129. #define CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV_LSB 10
  130. #define CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV_MASK 0x00007c00
  131. #define CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV_SET(x) \
  132. (((x) << CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV_LSB) & CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV_MASK)
  133. #define CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV_LSB 5
  134. #define CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV_MASK 0x000003e0
  135. #define CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV_SET(x) \
  136. (((x) << CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV_LSB) & CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV_MASK)
  137. #define CPU_DDR_CLOCK_CONTROL_AHB_PLL_BYPASS_LSB 4
  138. #define CPU_DDR_CLOCK_CONTROL_AHB_PLL_BYPASS_MASK 0x00000010
  139. #define CPU_DDR_CLOCK_CONTROL_AHB_PLL_BYPASS_SET(x) \
  140. (((x) << CPU_DDR_CLOCK_CONTROL_AHB_PLL_BYPASS_LSB) & CPU_DDR_CLOCK_CONTROL_AHB_PLL_BYPASS_MASK)
  141. #define CPU_DDR_CLOCK_CONTROL_DDR_PLL_BYPASS_LSB 3
  142. #define CPU_DDR_CLOCK_CONTROL_DDR_PLL_BYPASS_MASK 0x00000008
  143. #define CPU_DDR_CLOCK_CONTROL_DDR_PLL_BYPASS_SET(x) \
  144. (((x) << CPU_DDR_CLOCK_CONTROL_DDR_PLL_BYPASS_LSB) & CPU_DDR_CLOCK_CONTROL_DDR_PLL_BYPASS_MASK)
  145. #define CPU_DDR_CLOCK_CONTROL_CPU_PLL_BYPASS_LSB 2
  146. #define CPU_DDR_CLOCK_CONTROL_CPU_PLL_BYPASS_MASK 0x00000004
  147. #define CPU_DDR_CLOCK_CONTROL_CPU_PLL_BYPASS_SET(x) \
  148. (((x) << CPU_DDR_CLOCK_CONTROL_CPU_PLL_BYPASS_LSB) & CPU_DDR_CLOCK_CONTROL_CPU_PLL_BYPASS_MASK)
  149. #define CPU_PLL_CONFIG1_NINT_VAL CPU_PLL_CONFIG1_NINT_SET(0x1f)
  150. #define CPU_PLL_CONFIG_REF_DIV_VAL CPU_PLL_CONFIG_REFDIV_SET(0x1)
  151. #define CPU_PLL_CONFIG_RANGE_VAL CPU_PLL_CONFIG_RANGE_SET(0)
  152. #define CPU_PLL_CONFIG_OUT_DIV_VAL1 CPU_PLL_CONFIG_OUTDIV_SET(0)
  153. #define CPU_PLL_CONFIG_OUT_DIV_VAL2 CPU_PLL_CONFIG_OUTDIV_SET(0)
  154. #define CPU_PLL_DITHER1_VAL CPU_PLL_DITHER1_DITHER_EN_SET(0) | \
  155. CPU_PLL_DITHER1_NFRAC_MIN_SET(0) | \
  156. CPU_PLL_DITHER1_NFRAC_STEP_SET(0) | \
  157. CPU_PLL_DITHER1_UPDATE_COUNT_SET(0x0)
  158. #define CPU_PLL_DITHER2_VAL CPU_PLL_DITHER2_NFRAC_MAX_SET(0x0)
  159. #define DDR_PLL_CONFIG1_NINT_VAL DDR_PLL_CONFIG1_NINT_SET(0x1a)
  160. #define DDR_PLL_CONFIG_REF_DIV_VAL DDR_PLL_CONFIG_REFDIV_SET(0x1)
  161. #define DDR_PLL_CONFIG_RANGE_VAL DDR_PLL_CONFIG_RANGE_SET(0)
  162. #define DDR_PLL_CONFIG_OUT_DIV_VAL1 DDR_PLL_CONFIG_OUTDIV_SET(0)
  163. #define DDR_PLL_CONFIG_OUT_DIV_VAL2 DDR_PLL_CONFIG_OUTDIV_SET(0)
  164. #define DDR_PLL_DITHER1_VAL DDR_PLL_DITHER1_DITHER_EN_SET(0) | \
  165. DDR_PLL_DITHER1_NFRAC_MIN_SET(0) | \
  166. DDR_PLL_DITHER1_NFRAC_STEP_SET(0) | \
  167. DDR_PLL_DITHER1_UPDATE_COUNT_SET(0x0)
  168. #define DDR_PLL_DITHER2_VAL DDR_PLL_DITHER2_NFRAC_MAX_SET(0x0)
  169. #define AHB_CLK_FROM_DDR CPU_DDR_CLOCK_CONTROL_AHBCLK_FROM_DDRPLL_SET(0)
  170. #define CPU_AND_DDR_CLK_FROM_DDR \
  171. CPU_DDR_CLOCK_CONTROL_CPU_DDR_CLK_FROM_DDRPLL_SET(0)
  172. #define CPU_AND_DDR_CLK_FROM_CPU \
  173. CPU_DDR_CLOCK_CONTROL_CPU_DDR_CLK_FROM_CPUPLL_SET(0)
  174. #define CPU_DDR_CLOCK_CONTROL_AHB_DIV_VAL \
  175. CPU_DDR_CLOCK_CONTROL_AHB_POST_DIV_SET(0x2)
  176. #define CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV \
  177. CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV_SET(0)
  178. #define CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV \
  179. CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV_SET(0)
  180. static inline void set_val(u32 _reg, u32 _mask, u32 _val)
  181. {
  182. void __iomem *pll_regs = map_physmem(AR71XX_PLL_BASE,
  183. AR71XX_PLL_SIZE, MAP_NOCACHE);
  184. writel((readl(pll_regs + _reg) & (~(_mask))) | _val, pll_regs + _reg);
  185. }
  186. #define cpu_pll_set(_mask, _val) \
  187. set_val(QCA956X_PLL_CPU_CONFIG_REG, _mask, _val)
  188. #define ddr_pll_set(_mask, _val) \
  189. set_val(QCA956X_PLL_DDR_CONFIG_REG, _mask, _val)
  190. #define cpu_ddr_control_set(_mask, _val) \
  191. set_val(QCA956X_PLL_CLK_CTRL_REG, _mask, _val)
  192. DECLARE_GLOBAL_DATA_PTR;
  193. static u32 qca956x_get_xtal(void)
  194. {
  195. u32 val;
  196. val = ath79_get_bootstrap();
  197. if (val & QCA956X_BOOTSTRAP_REF_CLK_40)
  198. return 40000000;
  199. else
  200. return 25000000;
  201. }
  202. int get_serial_clock(void)
  203. {
  204. return qca956x_get_xtal();
  205. }
  206. void qca956x_pll_init(void)
  207. {
  208. void __iomem *srif_regs = map_physmem(QCA956X_SRIF_BASE,
  209. QCA956X_SRIF_SIZE, MAP_NOCACHE);
  210. void __iomem *pll_regs = map_physmem(AR71XX_PLL_BASE,
  211. AR71XX_PLL_SIZE, MAP_NOCACHE);
  212. /* 8.16.2 Baseband DPLL2 */
  213. writel(PLL_SRIF_DPLL2_KI_SET(2) | PLL_SRIF_DPLL2_KD_SET(0xa) |
  214. PLL_SRIF_DPLL2_PLL_PWD_SET(1) | PLL_SRIF_DPLL2_OUTDIV_SET(1) |
  215. PLL_SRIF_DPLL2_PHASE_SHIFT_SET(6), srif_regs + QCA956X_SRIF_BB_DPLL2_REG);
  216. /* 8.16.2 PCIE DPLL2 */
  217. writel(PLL_SRIF_DPLL2_KI_SET(2) | PLL_SRIF_DPLL2_KD_SET(0xa) |
  218. PLL_SRIF_DPLL2_PLL_PWD_SET(1) | PLL_SRIF_DPLL2_OUTDIV_SET(3) |
  219. PLL_SRIF_DPLL2_PHASE_SHIFT_SET(6), srif_regs + QCA956X_SRIF_PCIE_DPLL2_REG);
  220. /* 8.16.2 DDR DPLL2 */
  221. writel(PLL_SRIF_DPLL2_KI_SET(2) | PLL_SRIF_DPLL2_KD_SET(0xa) |
  222. PLL_SRIF_DPLL2_PLL_PWD_SET(1) | PLL_SRIF_DPLL2_PHASE_SHIFT_SET(6),
  223. srif_regs + QCA956X_SRIF_DDR_DPLL2_REG);
  224. /* 8.16.2 CPU DPLL2 */
  225. writel(PLL_SRIF_DPLL2_KI_SET(1) | PLL_SRIF_DPLL2_KD_SET(7) |
  226. PLL_SRIF_DPLL2_PLL_PWD_SET(1) | PLL_SRIF_DPLL2_PHASE_SHIFT_SET(6),
  227. srif_regs + QCA956X_SRIF_CPU_DPLL2_REG);
  228. /* pll_bypass_set */
  229. cpu_ddr_control_set(CPU_DDR_CLOCK_CONTROL_CPU_PLL_BYPASS_MASK,
  230. CPU_DDR_CLOCK_CONTROL_CPU_PLL_BYPASS_SET(1));
  231. cpu_ddr_control_set(CPU_DDR_CLOCK_CONTROL_DDR_PLL_BYPASS_MASK,
  232. CPU_DDR_CLOCK_CONTROL_DDR_PLL_BYPASS_SET(1));
  233. cpu_ddr_control_set(CPU_DDR_CLOCK_CONTROL_AHB_PLL_BYPASS_MASK,
  234. CPU_DDR_CLOCK_CONTROL_AHB_PLL_BYPASS_SET(1));
  235. /* init_cpu_pll */
  236. cpu_pll_set(CPU_PLL_CONFIG_PLLPWD_MASK, CPU_PLL_CONFIG_PLLPWD_SET(1));
  237. cpu_pll_set(CPU_PLL_CONFIG_REFDIV_MASK, CPU_PLL_CONFIG_REF_DIV_VAL);
  238. cpu_pll_set(CPU_PLL_CONFIG_RANGE_MASK, CPU_PLL_CONFIG_RANGE_VAL);
  239. cpu_pll_set(CPU_PLL_CONFIG_OUTDIV_MASK, CPU_PLL_CONFIG_OUT_DIV_VAL1);
  240. set_val(QCA956X_PLL_CPU_CONFIG1_REG, CPU_PLL_CONFIG1_NINT_MASK, \
  241. CPU_PLL_CONFIG1_NINT_VAL);
  242. /* init_ddr_pll */
  243. ddr_pll_set(DDR_PLL_CONFIG_PLLPWD_MASK, DDR_PLL_CONFIG_PLLPWD_SET(1));
  244. ddr_pll_set(DDR_PLL_CONFIG_REFDIV_MASK, DDR_PLL_CONFIG_REF_DIV_VAL);
  245. ddr_pll_set(DDR_PLL_CONFIG_RANGE_MASK, DDR_PLL_CONFIG_RANGE_VAL);
  246. ddr_pll_set(DDR_PLL_CONFIG_OUTDIV_MASK, DDR_PLL_CONFIG_OUT_DIV_VAL1);
  247. set_val(QCA956X_PLL_DDR_CONFIG1_REG, DDR_PLL_CONFIG1_NINT_MASK,
  248. DDR_PLL_CONFIG1_NINT_VAL);
  249. /* init_ahb_pll */
  250. writel(CPU_DDR_CLOCK_CONTROL_AHB_DIV_VAL | AHB_CLK_FROM_DDR |
  251. CPU_AND_DDR_CLK_FROM_DDR | CPU_AND_DDR_CLK_FROM_CPU |
  252. CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV | CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV |
  253. CPU_DDR_CLOCK_CONTROL_CPU_PLL_BYPASS_SET(1) |
  254. CPU_DDR_CLOCK_CONTROL_DDR_PLL_BYPASS_SET(1) |
  255. CPU_DDR_CLOCK_CONTROL_AHB_PLL_BYPASS_SET(1), pll_regs + QCA956X_PLL_CLK_CTRL_REG);
  256. /* ddr_pll_dither_unset */
  257. writel(DDR_PLL_DITHER1_VAL, pll_regs + QCA956X_PLL_DDR_DIT_FRAC_REG);
  258. writel(DDR_PLL_DITHER2_VAL, pll_regs + QCA956X_PLL_DDR_DIT2_FRAC_REG);
  259. /* cpu_pll_dither_unset */
  260. writel(CPU_PLL_DITHER1_VAL, pll_regs + QCA956X_PLL_CPU_DIT_FRAC_REG);
  261. writel(CPU_PLL_DITHER2_VAL, pll_regs + QCA956X_PLL_CPU_DIT2_FRAC_REG);
  262. /* pll_pwd_unset */
  263. cpu_pll_set(CPU_PLL_CONFIG_PLLPWD_MASK, CPU_PLL_CONFIG_PLLPWD_SET(0));
  264. ddr_pll_set(DDR_PLL_CONFIG_PLLPWD_MASK, DDR_PLL_CONFIG_PLLPWD_SET(0));
  265. /* outdiv_unset */
  266. cpu_pll_set(CPU_PLL_CONFIG_OUTDIV_MASK, CPU_PLL_CONFIG_OUT_DIV_VAL2);
  267. ddr_pll_set(DDR_PLL_CONFIG_OUTDIV_MASK, DDR_PLL_CONFIG_OUT_DIV_VAL2);
  268. /* pll_bypass_unset */
  269. cpu_ddr_control_set(CPU_DDR_CLOCK_CONTROL_CPU_PLL_BYPASS_MASK,
  270. CPU_DDR_CLOCK_CONTROL_CPU_PLL_BYPASS_SET(0));
  271. cpu_ddr_control_set(CPU_DDR_CLOCK_CONTROL_DDR_PLL_BYPASS_MASK,
  272. CPU_DDR_CLOCK_CONTROL_DDR_PLL_BYPASS_SET(0));
  273. cpu_ddr_control_set(CPU_DDR_CLOCK_CONTROL_AHB_PLL_BYPASS_MASK,
  274. CPU_DDR_CLOCK_CONTROL_AHB_PLL_BYPASS_SET(0));
  275. while (readl(pll_regs + QCA956X_PLL_CPU_CONFIG_REG) & 0x8000000)
  276. /* NOP */;
  277. while (readl(pll_regs + QCA956X_PLL_DDR_CONFIG_REG) & 0x8000000)
  278. /* NOP */;
  279. }
  280. int get_clocks(void)
  281. {
  282. void __iomem *regs;
  283. u32 ref_rate, cpu_rate, ddr_rate, ahb_rate;
  284. u32 out_div, ref_div, postdiv, nint, hfrac, lfrac, clk_ctrl;
  285. u32 pll, cpu_pll, ddr_pll, misc;
  286. /*
  287. * QCA956x timer init workaround has to be applied right before setting
  288. * up the clock. Else, there will be no jiffies
  289. */
  290. regs = map_physmem(AR71XX_RESET_BASE, AR71XX_RESET_SIZE,
  291. MAP_NOCACHE);
  292. misc = readl(regs + AR71XX_RESET_REG_MISC_INT_ENABLE);
  293. misc |= MISC_INT_MIPS_SI_TIMERINT_MASK;
  294. writel(misc, regs + AR71XX_RESET_REG_MISC_INT_ENABLE);
  295. regs = map_physmem(AR71XX_PLL_BASE, AR71XX_PLL_SIZE,
  296. MAP_NOCACHE);
  297. pll = readl(regs + QCA956X_PLL_CPU_CONFIG_REG);
  298. out_div = (pll >> QCA956X_PLL_CPU_CONFIG_OUTDIV_SHIFT) &
  299. QCA956X_PLL_CPU_CONFIG_OUTDIV_MASK;
  300. ref_div = (pll >> QCA956X_PLL_CPU_CONFIG_REFDIV_SHIFT) &
  301. QCA956X_PLL_CPU_CONFIG_REFDIV_MASK;
  302. pll = readl(regs + QCA956X_PLL_CPU_CONFIG1_REG);
  303. nint = (pll >> QCA956X_PLL_CPU_CONFIG1_NINT_SHIFT) &
  304. QCA956X_PLL_CPU_CONFIG1_NINT_MASK;
  305. hfrac = (pll >> QCA956X_PLL_CPU_CONFIG1_NFRAC_H_SHIFT) &
  306. QCA956X_PLL_CPU_CONFIG1_NFRAC_H_MASK;
  307. lfrac = (pll >> QCA956X_PLL_CPU_CONFIG1_NFRAC_L_SHIFT) &
  308. QCA956X_PLL_CPU_CONFIG1_NFRAC_L_MASK;
  309. ref_rate = qca956x_get_xtal();
  310. cpu_pll = nint * ref_rate / ref_div;
  311. cpu_pll += (lfrac * ref_rate) / ((ref_div * 25) << 13);
  312. cpu_pll += (hfrac >> 13) * ref_rate / ref_div;
  313. cpu_pll /= (1 << out_div);
  314. pll = readl(regs + QCA956X_PLL_DDR_CONFIG_REG);
  315. out_div = (pll >> QCA956X_PLL_DDR_CONFIG_OUTDIV_SHIFT) &
  316. QCA956X_PLL_DDR_CONFIG_OUTDIV_MASK;
  317. ref_div = (pll >> QCA956X_PLL_DDR_CONFIG_REFDIV_SHIFT) &
  318. QCA956X_PLL_DDR_CONFIG_REFDIV_MASK;
  319. pll = readl(regs + QCA956X_PLL_DDR_CONFIG1_REG);
  320. nint = (pll >> QCA956X_PLL_DDR_CONFIG1_NINT_SHIFT) &
  321. QCA956X_PLL_DDR_CONFIG1_NINT_MASK;
  322. hfrac = (pll >> QCA956X_PLL_DDR_CONFIG1_NFRAC_H_SHIFT) &
  323. QCA956X_PLL_DDR_CONFIG1_NFRAC_H_MASK;
  324. lfrac = (pll >> QCA956X_PLL_DDR_CONFIG1_NFRAC_L_SHIFT) &
  325. QCA956X_PLL_DDR_CONFIG1_NFRAC_L_MASK;
  326. ddr_pll = nint * ref_rate / ref_div;
  327. ddr_pll += (lfrac * ref_rate) / ((ref_div * 25) << 13);
  328. ddr_pll += (hfrac >> 13) * ref_rate / ref_div;
  329. ddr_pll /= (1 << out_div);
  330. clk_ctrl = readl(regs + QCA956X_PLL_CLK_CTRL_REG);
  331. postdiv = (clk_ctrl >> QCA956X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT) &
  332. QCA956X_PLL_CLK_CTRL_CPU_POST_DIV_MASK;
  333. if (clk_ctrl & QCA956X_PLL_CLK_CTRL_CPU_PLL_BYPASS)
  334. cpu_rate = ref_rate;
  335. else if (clk_ctrl & QCA956X_PLL_CLK_CTRL_CPU_DDRCLK_FROM_CPUPLL)
  336. cpu_rate = ddr_pll / (postdiv + 1);
  337. else
  338. cpu_rate = cpu_pll / (postdiv + 1);
  339. postdiv = (clk_ctrl >> QCA956X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT) &
  340. QCA956X_PLL_CLK_CTRL_DDR_POST_DIV_MASK;
  341. if (clk_ctrl & QCA956X_PLL_CLK_CTRL_DDR_PLL_BYPASS)
  342. ddr_rate = ref_rate;
  343. else if (clk_ctrl & QCA956X_PLL_CLK_CTRL_CPU_DDRCLK_FROM_DDRPLL)
  344. ddr_rate = cpu_pll / (postdiv + 1);
  345. else
  346. ddr_rate = ddr_pll / (postdiv + 1);
  347. postdiv = (clk_ctrl >> QCA956X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT) &
  348. QCA956X_PLL_CLK_CTRL_AHB_POST_DIV_MASK;
  349. if (clk_ctrl & QCA956X_PLL_CLK_CTRL_AHB_PLL_BYPASS)
  350. ahb_rate = ref_rate;
  351. else if (clk_ctrl & QCA956X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL)
  352. ahb_rate = ddr_pll / (postdiv + 1);
  353. else
  354. ahb_rate = cpu_pll / (postdiv + 1);
  355. gd->cpu_clk = cpu_rate;
  356. gd->mem_clk = ddr_rate;
  357. gd->bus_clk = ahb_rate;
  358. debug("cpu_clk=%u, ddr_clk=%u, bus_clk=%u\n",
  359. cpu_rate, ddr_rate, ahb_rate);
  360. return 0;
  361. }
  362. ulong get_bus_freq(ulong dummy)
  363. {
  364. if (!gd->bus_clk)
  365. get_clocks();
  366. return gd->bus_clk;
  367. }
  368. ulong get_ddr_freq(ulong dummy)
  369. {
  370. if (!gd->mem_clk)
  371. get_clocks();
  372. return gd->mem_clk;
  373. }