clk.c 2.5 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111
  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2015-2016 Wills Wang <wills.wang@live.com>
  4. */
  5. #include <common.h>
  6. #include <clock_legacy.h>
  7. #include <asm/io.h>
  8. #include <asm/addrspace.h>
  9. #include <asm/types.h>
  10. #include <mach/ar71xx_regs.h>
  11. #include <mach/ath79.h>
  12. DECLARE_GLOBAL_DATA_PTR;
  13. static u32 qca953x_get_xtal(void)
  14. {
  15. u32 val;
  16. val = ath79_get_bootstrap();
  17. if (val & QCA953X_BOOTSTRAP_REF_CLK_40)
  18. return 40000000;
  19. else
  20. return 25000000;
  21. }
  22. int get_serial_clock(void)
  23. {
  24. return qca953x_get_xtal();
  25. }
  26. int get_clocks(void)
  27. {
  28. void __iomem *regs;
  29. u32 val, ctrl, xtal, pll, div;
  30. regs = map_physmem(AR71XX_PLL_BASE, AR71XX_PLL_SIZE,
  31. MAP_NOCACHE);
  32. xtal = qca953x_get_xtal();
  33. ctrl = readl(regs + QCA953X_PLL_CLK_CTRL_REG);
  34. val = readl(regs + QCA953X_PLL_CPU_CONFIG_REG);
  35. /* VCOOUT = XTAL * DIV_INT */
  36. div = (val >> QCA953X_PLL_CPU_CONFIG_REFDIV_SHIFT)
  37. & QCA953X_PLL_CPU_CONFIG_REFDIV_MASK;
  38. pll = xtal / div;
  39. /* PLLOUT = VCOOUT * (1/2^OUTDIV) */
  40. div = (val >> QCA953X_PLL_CPU_CONFIG_NINT_SHIFT)
  41. & QCA953X_PLL_CPU_CONFIG_NINT_MASK;
  42. pll *= div;
  43. div = (val >> QCA953X_PLL_CPU_CONFIG_OUTDIV_SHIFT)
  44. & QCA953X_PLL_CPU_CONFIG_OUTDIV_MASK;
  45. if (!div)
  46. div = 1;
  47. pll >>= div;
  48. /* CPU_CLK = PLLOUT / CPU_POST_DIV */
  49. div = ((ctrl >> QCA953X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT)
  50. & QCA953X_PLL_CLK_CTRL_CPU_POST_DIV_MASK) + 1;
  51. gd->cpu_clk = pll / div;
  52. val = readl(regs + QCA953X_PLL_DDR_CONFIG_REG);
  53. /* VCOOUT = XTAL * DIV_INT */
  54. div = (val >> QCA953X_PLL_DDR_CONFIG_REFDIV_SHIFT)
  55. & QCA953X_PLL_DDR_CONFIG_REFDIV_MASK;
  56. pll = xtal / div;
  57. /* PLLOUT = VCOOUT * (1/2^OUTDIV) */
  58. div = (val >> QCA953X_PLL_DDR_CONFIG_NINT_SHIFT)
  59. & QCA953X_PLL_DDR_CONFIG_NINT_MASK;
  60. pll *= div;
  61. div = (val >> QCA953X_PLL_DDR_CONFIG_OUTDIV_SHIFT)
  62. & QCA953X_PLL_DDR_CONFIG_OUTDIV_MASK;
  63. if (!div)
  64. div = 1;
  65. pll >>= div;
  66. /* DDR_CLK = PLLOUT / DDR_POST_DIV */
  67. div = ((ctrl >> QCA953X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT)
  68. & QCA953X_PLL_CLK_CTRL_DDR_POST_DIV_MASK) + 1;
  69. gd->mem_clk = pll / div;
  70. div = ((ctrl >> QCA953X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT)
  71. & QCA953X_PLL_CLK_CTRL_AHB_POST_DIV_MASK) + 1;
  72. if (ctrl & QCA953X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL) {
  73. /* AHB_CLK = DDR_CLK / AHB_POST_DIV */
  74. gd->bus_clk = gd->mem_clk / (div + 1);
  75. } else {
  76. /* AHB_CLK = CPU_CLK / AHB_POST_DIV */
  77. gd->bus_clk = gd->cpu_clk / (div + 1);
  78. }
  79. return 0;
  80. }
  81. ulong get_bus_freq(ulong dummy)
  82. {
  83. if (!gd->bus_clk)
  84. get_clocks();
  85. return gd->bus_clk;
  86. }
  87. ulong get_ddr_freq(ulong dummy)
  88. {
  89. if (!gd->mem_clk)
  90. get_clocks();
  91. return gd->mem_clk;
  92. }