clk.c 1.9 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2015-2016 Wills Wang <wills.wang@live.com>
  4. */
  5. #include <common.h>
  6. #include <clock_legacy.h>
  7. #include <asm/io.h>
  8. #include <asm/addrspace.h>
  9. #include <asm/types.h>
  10. #include <mach/ar71xx_regs.h>
  11. #include <mach/ath79.h>
  12. DECLARE_GLOBAL_DATA_PTR;
  13. static u32 ar933x_get_xtal(void)
  14. {
  15. u32 val;
  16. val = ath79_get_bootstrap();
  17. if (val & AR933X_BOOTSTRAP_REF_CLK_40)
  18. return 40000000;
  19. else
  20. return 25000000;
  21. }
  22. int get_serial_clock(void)
  23. {
  24. return ar933x_get_xtal();
  25. }
  26. int get_clocks(void)
  27. {
  28. void __iomem *regs;
  29. u32 val, xtal, pll, div;
  30. regs = map_physmem(AR71XX_PLL_BASE, AR71XX_PLL_SIZE,
  31. MAP_NOCACHE);
  32. xtal = ar933x_get_xtal();
  33. val = readl(regs + AR933X_PLL_CPU_CONFIG_REG);
  34. /* VCOOUT = XTAL * DIV_INT */
  35. div = (val >> AR933X_PLL_CPU_CONFIG_REFDIV_SHIFT)
  36. & AR933X_PLL_CPU_CONFIG_REFDIV_MASK;
  37. pll = xtal / div;
  38. /* PLLOUT = VCOOUT * (1/2^OUTDIV) */
  39. div = (val >> AR933X_PLL_CPU_CONFIG_NINT_SHIFT)
  40. & AR933X_PLL_CPU_CONFIG_NINT_MASK;
  41. pll *= div;
  42. div = (val >> AR933X_PLL_CPU_CONFIG_OUTDIV_SHIFT)
  43. & AR933X_PLL_CPU_CONFIG_OUTDIV_MASK;
  44. if (!div)
  45. div = 1;
  46. pll >>= div;
  47. val = readl(regs + AR933X_PLL_CLK_CTRL_REG);
  48. /* CPU_CLK = PLLOUT / CPU_POST_DIV */
  49. div = ((val >> AR933X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT)
  50. & AR933X_PLL_CLK_CTRL_CPU_POST_DIV_MASK) + 1;
  51. gd->cpu_clk = pll / div;
  52. /* DDR_CLK = PLLOUT / DDR_POST_DIV */
  53. div = ((val >> AR933X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT)
  54. & AR933X_PLL_CLK_CTRL_DDR_POST_DIV_MASK) + 1;
  55. gd->mem_clk = pll / div;
  56. /* AHB_CLK = PLLOUT / AHB_POST_DIV */
  57. div = ((val >> AR933X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT)
  58. & AR933X_PLL_CLK_CTRL_AHB_POST_DIV_MASK) + 1;
  59. gd->bus_clk = pll / div;
  60. return 0;
  61. }
  62. ulong get_bus_freq(ulong dummy)
  63. {
  64. if (!gd->bus_clk)
  65. get_clocks();
  66. return gd->bus_clk;
  67. }
  68. ulong get_ddr_freq(ulong dummy)
  69. {
  70. if (!gd->mem_clk)
  71. get_clocks();
  72. return gd->mem_clk;
  73. }