speed.c 6.8 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. *
  4. * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
  5. * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
  6. */
  7. #include <common.h>
  8. #include <clock_legacy.h>
  9. #include <asm/processor.h>
  10. #include <asm/immap.h>
  11. #include <asm/io.h>
  12. DECLARE_GLOBAL_DATA_PTR;
  13. /*
  14. * Low Power Divider specifications
  15. */
  16. #define CLOCK_LPD_MIN (1 << 0) /* Divider (decoded) */
  17. #define CLOCK_LPD_MAX (1 << 15) /* Divider (decoded) */
  18. #define CLOCK_PLL_FVCO_MAX 540000000
  19. #define CLOCK_PLL_FVCO_MIN 300000000
  20. #define CLOCK_PLL_FSYS_MAX 266666666
  21. #define CLOCK_PLL_FSYS_MIN 100000000
  22. #define MHZ 1000000
  23. void clock_enter_limp(int lpdiv)
  24. {
  25. ccm_t *ccm = (ccm_t *)MMAP_CCM;
  26. int i, j;
  27. /* Check bounds of divider */
  28. if (lpdiv < CLOCK_LPD_MIN)
  29. lpdiv = CLOCK_LPD_MIN;
  30. if (lpdiv > CLOCK_LPD_MAX)
  31. lpdiv = CLOCK_LPD_MAX;
  32. /* Round divider down to nearest power of two */
  33. for (i = 0, j = lpdiv; j != 1; j >>= 1, i++) ;
  34. #ifdef CONFIG_MCF5445x
  35. /* Apply the divider to the system clock */
  36. clrsetbits_be16(&ccm->cdr, 0x0f00, CCM_CDR_LPDIV(i));
  37. #endif
  38. /* Enable Limp Mode */
  39. setbits_be16(&ccm->misccr, CCM_MISCCR_LIMP);
  40. }
  41. /*
  42. * brief Exit Limp mode
  43. * warning The PLL should be set and locked prior to exiting Limp mode
  44. */
  45. void clock_exit_limp(void)
  46. {
  47. ccm_t *ccm = (ccm_t *)MMAP_CCM;
  48. pll_t *pll = (pll_t *)MMAP_PLL;
  49. /* Exit Limp mode */
  50. clrbits_be16(&ccm->misccr, CCM_MISCCR_LIMP);
  51. /* Wait for the PLL to lock */
  52. while (!(in_be32(&pll->psr) & PLL_PSR_LOCK))
  53. ;
  54. }
  55. #ifdef CONFIG_MCF5441x
  56. void setup_5441x_clocks(void)
  57. {
  58. ccm_t *ccm = (ccm_t *)MMAP_CCM;
  59. pll_t *pll = (pll_t *)MMAP_PLL;
  60. int temp, vco = 0, bootmod_ccr, pdr;
  61. bootmod_ccr = (in_be16(&ccm->ccr) & CCM_CCR_BOOTMOD) >> 14;
  62. switch (bootmod_ccr) {
  63. case 0:
  64. out_be32(&pll->pcr, 0x00000013);
  65. out_be32(&pll->pdr, 0x00e70c61);
  66. clock_exit_limp();
  67. break;
  68. case 2:
  69. break;
  70. case 3:
  71. break;
  72. }
  73. /*Change frequency for Modelo SER1 USB host*/
  74. #ifdef CONFIG_LOW_MCFCLK
  75. temp = in_be32(&pll->pcr);
  76. temp &= ~0x3f;
  77. temp |= 5;
  78. out_be32(&pll->pcr, temp);
  79. temp = in_be32(&pll->pdr);
  80. temp &= ~0x001f0000;
  81. temp |= 0x00040000;
  82. out_be32(&pll->pdr, temp);
  83. __asm__("tpf");
  84. #endif
  85. setbits_be16(&ccm->misccr2, 0x02);
  86. vco = ((in_be32(&pll->pcr) & PLL_CR_FBKDIV_BITS) + 1) *
  87. CONFIG_SYS_INPUT_CLKSRC;
  88. gd->arch.vco_clk = vco;
  89. gd->arch.inp_clk = CONFIG_SYS_INPUT_CLKSRC; /* Input clock */
  90. pdr = in_be32(&pll->pdr);
  91. temp = (pdr & PLL_DR_OUTDIV1_BITS) + 1;
  92. gd->cpu_clk = vco / temp; /* cpu clock */
  93. gd->arch.flb_clk = vco / temp; /* FlexBus clock */
  94. gd->arch.flb_clk >>= 1;
  95. if (in_be16(&ccm->misccr2) & 2) /* fsys/4 */
  96. gd->arch.flb_clk >>= 1;
  97. temp = ((pdr & PLL_DR_OUTDIV2_BITS) >> 5) + 1;
  98. gd->bus_clk = vco / temp; /* bus clock */
  99. temp = ((pdr & PLL_DR_OUTDIV3_BITS) >> 10) + 1;
  100. gd->arch.sdhc_clk = vco / temp;
  101. }
  102. #endif
  103. #ifdef CONFIG_MCF5445x
  104. void setup_5445x_clocks(void)
  105. {
  106. ccm_t *ccm = (ccm_t *)MMAP_CCM;
  107. pll_t *pll = (pll_t *)MMAP_PLL;
  108. int pllmult_nopci[] = { 20, 10, 24, 18, 12, 6, 16, 8 };
  109. int pllmult_pci[] = { 12, 6, 16, 8 };
  110. int vco = 0, temp, fbtemp, pcrvalue;
  111. int *pPllmult = NULL;
  112. u16 fbpll_mask;
  113. #ifdef CONFIG_PCI
  114. int bPci;
  115. #endif
  116. #ifdef CONFIG_M54455EVB
  117. u8 *cpld = (u8 *)(CONFIG_SYS_CS2_BASE + 3);
  118. #endif
  119. u8 bootmode;
  120. /* To determine PCI is present or not */
  121. if (((in_be16(&ccm->ccr) & CCM_CCR_360_FBCONFIG_MASK) == 0x00e0) ||
  122. ((in_be16(&ccm->ccr) & CCM_CCR_360_FBCONFIG_MASK) == 0x0060)) {
  123. pPllmult = &pllmult_pci[0];
  124. fbpll_mask = 3; /* 11b */
  125. #ifdef CONFIG_PCI
  126. bPci = 1;
  127. #endif
  128. } else {
  129. pPllmult = &pllmult_nopci[0];
  130. fbpll_mask = 7; /* 111b */
  131. #ifdef CONFIG_PCI
  132. gd->pci_clk = 0;
  133. bPci = 0;
  134. #endif
  135. }
  136. #ifdef CONFIG_M54455EVB
  137. bootmode = (in_8(cpld) & 0x03);
  138. if (bootmode != 3) {
  139. /* Temporary read from CCR- fixed fb issue, must be the same clock
  140. as pci or input clock, causing cpld/fpga read inconsistancy */
  141. fbtemp = pPllmult[ccm->ccr & fbpll_mask];
  142. /* Break down into small pieces, code still in flex bus */
  143. pcrvalue = in_be32(&pll->pcr) & 0xFFFFF0FF;
  144. temp = fbtemp - 1;
  145. pcrvalue |= PLL_PCR_OUTDIV3(temp);
  146. out_be32(&pll->pcr, pcrvalue);
  147. }
  148. #endif
  149. #ifdef CONFIG_M54451EVB
  150. /* No external logic to read the bootmode, hard coded from built */
  151. #ifdef CONFIG_CF_SBF
  152. bootmode = 3;
  153. #else
  154. bootmode = 2;
  155. /* default value is 16 mul, set to 20 mul */
  156. pcrvalue = (in_be32(&pll->pcr) & 0x00FFFFFF) | 0x14000000;
  157. out_be32(&pll->pcr, pcrvalue);
  158. while ((in_be32(&pll->psr) & PLL_PSR_LOCK) != PLL_PSR_LOCK)
  159. ;
  160. #endif
  161. #endif
  162. if (bootmode == 0) {
  163. /* RCON mode */
  164. vco = pPllmult[ccm->rcon & fbpll_mask] * CONFIG_SYS_INPUT_CLKSRC;
  165. if ((vco < CLOCK_PLL_FVCO_MIN) || (vco > CLOCK_PLL_FVCO_MAX)) {
  166. /* invaild range, re-set in PCR */
  167. int temp = ((in_be32(&pll->pcr) & PLL_PCR_OUTDIV2_MASK) >> 4) + 1;
  168. int i, j, bus;
  169. j = (in_be32(&pll->pcr) & 0xFF000000) >> 24;
  170. for (i = j; i < 0xFF; i++) {
  171. vco = i * CONFIG_SYS_INPUT_CLKSRC;
  172. if (vco >= CLOCK_PLL_FVCO_MIN) {
  173. bus = vco / temp;
  174. if (bus <= CLOCK_PLL_FSYS_MIN - MHZ)
  175. continue;
  176. else
  177. break;
  178. }
  179. }
  180. pcrvalue = in_be32(&pll->pcr) & 0x00FF00FF;
  181. fbtemp = ((i - 1) << 8) | ((i - 1) << 12);
  182. pcrvalue |= ((i << 24) | fbtemp);
  183. out_be32(&pll->pcr, pcrvalue);
  184. }
  185. gd->arch.vco_clk = vco; /* Vco clock */
  186. } else if (bootmode == 2) {
  187. /* Normal mode */
  188. vco = ((in_be32(&pll->pcr) & 0xFF000000) >> 24) * CONFIG_SYS_INPUT_CLKSRC;
  189. if ((vco < CLOCK_PLL_FVCO_MIN) || (vco > CLOCK_PLL_FVCO_MAX)) {
  190. /* Default value */
  191. pcrvalue = (in_be32(&pll->pcr) & 0x00FFFFFF);
  192. pcrvalue |= pPllmult[in_be16(&ccm->ccr) & fbpll_mask] << 24;
  193. out_be32(&pll->pcr, pcrvalue);
  194. vco = ((in_be32(&pll->pcr) & 0xFF000000) >> 24) * CONFIG_SYS_INPUT_CLKSRC;
  195. }
  196. gd->arch.vco_clk = vco; /* Vco clock */
  197. } else if (bootmode == 3) {
  198. /* serial mode */
  199. vco = ((in_be32(&pll->pcr) & 0xFF000000) >> 24) * CONFIG_SYS_INPUT_CLKSRC;
  200. gd->arch.vco_clk = vco; /* Vco clock */
  201. }
  202. if ((in_be16(&ccm->ccr) & CCM_MISCCR_LIMP) == CCM_MISCCR_LIMP) {
  203. /* Limp mode */
  204. } else {
  205. gd->arch.inp_clk = CONFIG_SYS_INPUT_CLKSRC; /* Input clock */
  206. temp = (in_be32(&pll->pcr) & PLL_PCR_OUTDIV1_MASK) + 1;
  207. gd->cpu_clk = vco / temp; /* cpu clock */
  208. temp = ((in_be32(&pll->pcr) & PLL_PCR_OUTDIV2_MASK) >> 4) + 1;
  209. gd->bus_clk = vco / temp; /* bus clock */
  210. temp = ((in_be32(&pll->pcr) & PLL_PCR_OUTDIV3_MASK) >> 8) + 1;
  211. gd->arch.flb_clk = vco / temp; /* FlexBus clock */
  212. #ifdef CONFIG_PCI
  213. if (bPci) {
  214. temp = ((in_be32(&pll->pcr) & PLL_PCR_OUTDIV4_MASK) >> 12) + 1;
  215. gd->pci_clk = vco / temp; /* PCI clock */
  216. }
  217. #endif
  218. }
  219. #ifdef CONFIG_SYS_I2C_FSL
  220. gd->arch.i2c1_clk = gd->bus_clk;
  221. #endif
  222. }
  223. #endif
  224. /* get_clocks() fills in gd->cpu_clock and gd->bus_clk */
  225. int get_clocks(void)
  226. {
  227. #ifdef CONFIG_MCF5441x
  228. setup_5441x_clocks();
  229. #endif
  230. #ifdef CONFIG_MCF5445x
  231. setup_5445x_clocks();
  232. #endif
  233. #ifdef CONFIG_SYS_FSL_I2C
  234. gd->arch.i2c1_clk = gd->bus_clk;
  235. #endif
  236. return (0);
  237. }