speed.c 2.2 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2003
  4. * Josef Baumgartner <josef.baumgartner@telex.de>
  5. *
  6. * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
  7. * Hayden Fraser (Hayden.Fraser@freescale.com)
  8. */
  9. #include <common.h>
  10. #include <clock_legacy.h>
  11. #include <asm/processor.h>
  12. #include <asm/immap.h>
  13. #include <asm/io.h>
  14. DECLARE_GLOBAL_DATA_PTR;
  15. /* get_clocks() fills in gd->cpu_clock and gd->bus_clk */
  16. int get_clocks(void)
  17. {
  18. #if defined(CONFIG_M5208)
  19. pll_t *pll = (pll_t *) MMAP_PLL;
  20. out_8(&pll->odr, CONFIG_SYS_PLL_ODR);
  21. out_8(&pll->fdr, CONFIG_SYS_PLL_FDR);
  22. #endif
  23. #if defined(CONFIG_M5249) || defined(CONFIG_M5253)
  24. volatile unsigned long cpll = mbar2_readLong(MCFSIM_PLLCR);
  25. unsigned long pllcr;
  26. #ifndef CONFIG_SYS_PLL_BYPASS
  27. #ifdef CONFIG_M5249
  28. /* Setup the PLL to run at the specified speed */
  29. #ifdef CONFIG_SYS_FAST_CLK
  30. pllcr = 0x925a3100; /* ~140MHz clock (PLL bypass = 0) */
  31. #else
  32. pllcr = 0x135a4140; /* ~72MHz clock (PLL bypass = 0) */
  33. #endif
  34. #endif /* CONFIG_M5249 */
  35. #ifdef CONFIG_M5253
  36. pllcr = CONFIG_SYS_PLLCR;
  37. #endif /* CONFIG_M5253 */
  38. cpll = cpll & 0xfffffffe; /* Set PLL bypass mode = 0 (PSTCLK = crystal) */
  39. mbar2_writeLong(MCFSIM_PLLCR, cpll); /* Set the PLL to bypass mode (PSTCLK = crystal) */
  40. mbar2_writeLong(MCFSIM_PLLCR, pllcr); /* set the clock speed */
  41. pllcr ^= 0x00000001; /* Set pll bypass to 1 */
  42. mbar2_writeLong(MCFSIM_PLLCR, pllcr); /* Start locking (pll bypass = 1) */
  43. udelay(0x20); /* Wait for a lock ... */
  44. #endif /* #ifndef CONFIG_SYS_PLL_BYPASS */
  45. #endif /* CONFIG_M5249 || CONFIG_M5253 */
  46. #if defined(CONFIG_M5275)
  47. pll_t *pll = (pll_t *)(MMAP_PLL);
  48. /* Setup PLL */
  49. out_be32(&pll->syncr, 0x01080000);
  50. while (!(in_be32(&pll->synsr) & FMPLL_SYNSR_LOCK))
  51. ;
  52. out_be32(&pll->syncr, 0x01000000);
  53. while (!(in_be32(&pll->synsr) & FMPLL_SYNSR_LOCK))
  54. ;
  55. #endif
  56. gd->cpu_clk = CONFIG_SYS_CLK;
  57. #if defined(CONFIG_M5208) || defined(CONFIG_M5249) || defined(CONFIG_M5253) || \
  58. defined(CONFIG_M5271) || defined(CONFIG_M5275)
  59. gd->bus_clk = gd->cpu_clk / 2;
  60. #else
  61. gd->bus_clk = gd->cpu_clk;
  62. #endif
  63. #ifdef CONFIG_SYS_I2C_FSL
  64. gd->arch.i2c1_clk = gd->bus_clk;
  65. #ifdef CONFIG_SYS_I2C2_FSL_OFFSET
  66. gd->arch.i2c2_clk = gd->bus_clk;
  67. #endif
  68. #endif
  69. return (0);
  70. }