speed.c 2.9 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. *
  4. * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
  5. * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
  6. */
  7. #include <common.h>
  8. #include <clock_legacy.h>
  9. #include <asm/processor.h>
  10. #include <asm/immap.h>
  11. #include <asm/io.h>
  12. DECLARE_GLOBAL_DATA_PTR;
  13. /*
  14. * Low Power Divider specifications
  15. */
  16. #define CLOCK_LPD_MIN (1 << 0) /* Divider (decoded) */
  17. #define CLOCK_LPD_MAX (1 << 15) /* Divider (decoded) */
  18. #define CLOCK_PLL_FVCO_MAX 540000000
  19. #define CLOCK_PLL_FVCO_MIN 300000000
  20. #define CLOCK_PLL_FSYS_MAX 266666666
  21. #define CLOCK_PLL_FSYS_MIN 100000000
  22. #define MHZ 1000000
  23. void clock_enter_limp(int lpdiv)
  24. {
  25. ccm_t *ccm = (ccm_t *)MMAP_CCM;
  26. int i, j;
  27. /* Check bounds of divider */
  28. if (lpdiv < CLOCK_LPD_MIN)
  29. lpdiv = CLOCK_LPD_MIN;
  30. if (lpdiv > CLOCK_LPD_MAX)
  31. lpdiv = CLOCK_LPD_MAX;
  32. /* Round divider down to nearest power of two */
  33. for (i = 0, j = lpdiv; j != 1; j >>= 1, i++) ;
  34. /* Apply the divider to the system clock */
  35. clrsetbits_be16(&ccm->cdr, 0x0f00, CCM_CDR_LPDIV(i));
  36. /* Enable Limp Mode */
  37. setbits_be16(&ccm->misccr, CCM_MISCCR_LIMP);
  38. }
  39. /*
  40. * brief Exit Limp mode
  41. * warning The PLL should be set and locked prior to exiting Limp mode
  42. */
  43. void clock_exit_limp(void)
  44. {
  45. ccm_t *ccm = (ccm_t *)MMAP_CCM;
  46. pll_t *pll = (pll_t *)MMAP_PLL;
  47. /* Exit Limp mode */
  48. clrbits_be16(&ccm->misccr, CCM_MISCCR_LIMP);
  49. /* Wait for the PLL to lock */
  50. while (!(in_be32(&pll->psr) & PLL_PSR_LOCK))
  51. ;
  52. }
  53. /*
  54. * get_clocks() fills in gd->cpu_clock and gd->bus_clk
  55. */
  56. int get_clocks(void)
  57. {
  58. ccm_t *ccm = (ccm_t *)MMAP_CCM;
  59. pll_t *pll = (pll_t *)MMAP_PLL;
  60. int vco, temp, pcrvalue, pfdr;
  61. u8 bootmode;
  62. pcrvalue = in_be32(&pll->pcr) & 0xFF0F0FFF;
  63. pfdr = pcrvalue >> 24;
  64. if (pfdr == 0x1E)
  65. bootmode = 0; /* Normal Mode */
  66. #ifdef CONFIG_CF_SBF
  67. bootmode = 3; /* Serial Mode */
  68. #endif
  69. if (bootmode == 0) {
  70. /* Normal mode */
  71. vco = ((in_be32(&pll->pcr) & 0xFF000000) >> 24) * CONFIG_SYS_INPUT_CLKSRC;
  72. if ((vco < CLOCK_PLL_FVCO_MIN) || (vco > CLOCK_PLL_FVCO_MAX)) {
  73. /* Default value */
  74. pcrvalue = (in_be32(&pll->pcr) & 0x00FFFFFF);
  75. pcrvalue |= 0x1E << 24;
  76. out_be32(&pll->pcr, pcrvalue);
  77. vco =
  78. ((in_be32(&pll->pcr) & 0xFF000000) >> 24) *
  79. CONFIG_SYS_INPUT_CLKSRC;
  80. }
  81. gd->arch.vco_clk = vco; /* Vco clock */
  82. } else if (bootmode == 3) {
  83. /* serial mode */
  84. vco = ((in_be32(&pll->pcr) & 0xFF000000) >> 24) * CONFIG_SYS_INPUT_CLKSRC;
  85. gd->arch.vco_clk = vco; /* Vco clock */
  86. }
  87. if ((in_be16(&ccm->ccr) & CCM_MISCCR_LIMP) == CCM_MISCCR_LIMP) {
  88. /* Limp mode */
  89. } else {
  90. gd->arch.inp_clk = CONFIG_SYS_INPUT_CLKSRC; /* Input clock */
  91. temp = (in_be32(&pll->pcr) & PLL_PCR_OUTDIV1_MASK) + 1;
  92. gd->cpu_clk = vco / temp; /* cpu clock */
  93. temp = ((in_be32(&pll->pcr) & PLL_PCR_OUTDIV2_MASK) >> 4) + 1;
  94. gd->arch.flb_clk = vco / temp; /* flexbus clock */
  95. gd->bus_clk = gd->arch.flb_clk;
  96. }
  97. #ifdef CONFIG_SYS_I2C_FSL
  98. gd->arch.i2c1_clk = gd->bus_clk;
  99. #endif
  100. return (0);
  101. }