fdt.c 5.0 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2014 Freescale Semiconductor, Inc.
  4. */
  5. #include <common.h>
  6. #include <clock_legacy.h>
  7. #include <linux/libfdt.h>
  8. #include <fdt_support.h>
  9. #include <asm/io.h>
  10. #include <asm/processor.h>
  11. #include <asm/arch/clock.h>
  12. #include <linux/ctype.h>
  13. #ifdef CONFIG_FSL_ESDHC
  14. #include <fsl_esdhc.h>
  15. #endif
  16. #include <tsec.h>
  17. #include <asm/arch/immap_ls102xa.h>
  18. #include <fsl_sec.h>
  19. #include <dm.h>
  20. DECLARE_GLOBAL_DATA_PTR;
  21. void ft_fixup_enet_phy_connect_type(void *fdt)
  22. {
  23. #ifdef CONFIG_DM_ETH
  24. struct udevice *dev;
  25. #else
  26. struct eth_device *dev;
  27. #endif
  28. struct tsec_private *priv;
  29. const char *enet_path, *phy_path;
  30. char enet[16];
  31. char phy[16];
  32. int phy_node;
  33. int i = 0;
  34. uint32_t ph;
  35. #ifdef CONFIG_DM_ETH
  36. char *name[3] = { "ethernet@2d10000", "ethernet@2d50000",
  37. "ethernet@2d90000" };
  38. #else
  39. char *name[3] = { "eTSEC1", "eTSEC2", "eTSEC3" };
  40. #endif
  41. for (; i < ARRAY_SIZE(name); i++) {
  42. dev = eth_get_dev_by_name(name[i]);
  43. if (dev) {
  44. sprintf(enet, "ethernet%d", i);
  45. sprintf(phy, "enet%d_rgmii_phy", i);
  46. } else {
  47. continue;
  48. }
  49. priv = dev->priv;
  50. if (priv->flags & TSEC_SGMII)
  51. continue;
  52. enet_path = fdt_get_alias(fdt, enet);
  53. if (!enet_path)
  54. continue;
  55. phy_path = fdt_get_alias(fdt, phy);
  56. if (!phy_path)
  57. continue;
  58. phy_node = fdt_path_offset(fdt, phy_path);
  59. if (phy_node < 0)
  60. continue;
  61. ph = fdt_create_phandle(fdt, phy_node);
  62. if (ph)
  63. do_fixup_by_path_u32(fdt, enet_path,
  64. "phy-handle", ph, 1);
  65. do_fixup_by_path(fdt, enet_path, "phy-connection-type",
  66. phy_string_for_interface(
  67. PHY_INTERFACE_MODE_RGMII_ID),
  68. strlen(phy_string_for_interface(
  69. PHY_INTERFACE_MODE_RGMII_ID)) + 1,
  70. 1);
  71. }
  72. }
  73. void ft_cpu_setup(void *blob, bd_t *bd)
  74. {
  75. int off;
  76. int val;
  77. const char *sysclk_path;
  78. struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
  79. unsigned int svr;
  80. svr = in_be32(&gur->svr);
  81. unsigned long busclk = get_bus_freq(0);
  82. /* delete crypto node if not on an E-processor */
  83. if (!IS_E_PROCESSOR(svr))
  84. fdt_fixup_crypto_node(blob, 0);
  85. #if CONFIG_SYS_FSL_SEC_COMPAT >= 4
  86. else {
  87. ccsr_sec_t __iomem *sec;
  88. sec = (void __iomem *)CONFIG_SYS_FSL_SEC_ADDR;
  89. fdt_fixup_crypto_node(blob, sec_in32(&sec->secvid_ms));
  90. }
  91. #endif
  92. off = fdt_node_offset_by_prop_value(blob, -1, "device_type", "cpu", 4);
  93. while (off != -FDT_ERR_NOTFOUND) {
  94. val = gd->cpu_clk;
  95. fdt_setprop(blob, off, "clock-frequency", &val, 4);
  96. off = fdt_node_offset_by_prop_value(blob, off,
  97. "device_type", "cpu", 4);
  98. }
  99. do_fixup_by_prop_u32(blob, "device_type", "soc",
  100. 4, "bus-frequency", busclk, 1);
  101. ft_fixup_enet_phy_connect_type(blob);
  102. #ifdef CONFIG_SYS_NS16550
  103. do_fixup_by_compat_u32(blob, "fsl,16550-FIFO64",
  104. "clock-frequency", CONFIG_SYS_NS16550_CLK, 1);
  105. #endif
  106. sysclk_path = fdt_get_alias(blob, "sysclk");
  107. if (sysclk_path)
  108. do_fixup_by_path_u32(blob, sysclk_path, "clock-frequency",
  109. CONFIG_SYS_CLK_FREQ, 1);
  110. do_fixup_by_compat_u32(blob, "fsl,qoriq-sysclk-2.0",
  111. "clock-frequency", CONFIG_SYS_CLK_FREQ, 1);
  112. #if defined(CONFIG_DEEP_SLEEP) && defined(CONFIG_SD_BOOT)
  113. #define UBOOT_HEAD_LEN 0x1000
  114. /*
  115. * Reserved memory in SD boot deep sleep case.
  116. * Second stage uboot binary and malloc space should be reserved.
  117. * If the memory they occupied has not been reserved, then this
  118. * space would be used by kernel and overwritten in uboot when
  119. * deep sleep resume, which cause deep sleep failed.
  120. * Since second uboot binary has a head, that space need to be
  121. * reserved either(assuming its size is less than 0x1000).
  122. */
  123. off = fdt_add_mem_rsv(blob, CONFIG_SYS_TEXT_BASE - UBOOT_HEAD_LEN,
  124. CONFIG_SYS_MONITOR_LEN + CONFIG_SYS_SPL_MALLOC_SIZE +
  125. UBOOT_HEAD_LEN);
  126. if (off < 0)
  127. printf("Failed to reserve memory for SD boot deep sleep: %s\n",
  128. fdt_strerror(off));
  129. #endif
  130. #if defined(CONFIG_FSL_ESDHC)
  131. fdt_fixup_esdhc(blob, bd);
  132. #endif
  133. /*
  134. * platform bus clock = system bus clock/2
  135. * Here busclk = system bus clock
  136. * We are using the platform bus clock as 1588 Timer reference
  137. * clock source select
  138. */
  139. do_fixup_by_compat_u32(blob, "fsl, gianfar-ptp-timer",
  140. "timer-frequency", busclk / 2, 1);
  141. /*
  142. * clock-freq should change to clock-frequency and
  143. * flexcan-v1.0 should change to p1010-flexcan respectively
  144. * in the future.
  145. */
  146. do_fixup_by_compat_u32(blob, "fsl, flexcan-v1.0",
  147. "clock_freq", busclk / 2, 1);
  148. do_fixup_by_compat_u32(blob, "fsl, flexcan-v1.0",
  149. "clock-frequency", busclk / 2, 1);
  150. do_fixup_by_compat_u32(blob, "fsl, ls1021a-flexcan",
  151. "clock-frequency", busclk / 2, 1);
  152. #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
  153. off = fdt_node_offset_by_compat_reg(blob, FSL_IFC_COMPAT,
  154. CONFIG_SYS_IFC_ADDR);
  155. fdt_set_node_status(blob, off, FDT_STATUS_DISABLED, 0);
  156. #else
  157. off = fdt_node_offset_by_compat_reg(blob, FSL_QSPI_COMPAT,
  158. QSPI0_BASE_ADDR);
  159. fdt_set_node_status(blob, off, FDT_STATUS_DISABLED, 0);
  160. off = fdt_node_offset_by_compat_reg(blob, FSL_DSPI_COMPAT,
  161. DSPI1_BASE_ADDR);
  162. fdt_set_node_status(blob, off, FDT_STATUS_DISABLED, 0);
  163. #endif
  164. }