generic.c 5.7 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2009 DENX Software Engineering
  4. * Author: John Rigby <jrigby@gmail.com>
  5. *
  6. * Based on mx27/generic.c:
  7. * Copyright (c) 2008 Eric Jarrige <eric.jarrige@armadeus.org>
  8. * Copyright (c) 2009 Ilya Yanok <yanok@emcraft.com>
  9. */
  10. #include <common.h>
  11. #include <clock_legacy.h>
  12. #include <div64.h>
  13. #include <netdev.h>
  14. #include <vsprintf.h>
  15. #include <asm/io.h>
  16. #include <asm/arch-imx/cpu.h>
  17. #include <asm/arch/imx-regs.h>
  18. #include <asm/arch/clock.h>
  19. #ifdef CONFIG_FSL_ESDHC_IMX
  20. #include <fsl_esdhc_imx.h>
  21. DECLARE_GLOBAL_DATA_PTR;
  22. #endif
  23. /*
  24. * get the system pll clock in Hz
  25. *
  26. * mfi + mfn / (mfd +1)
  27. * f = 2 * f_ref * --------------------
  28. * pd + 1
  29. */
  30. static unsigned int imx_decode_pll(unsigned int pll, unsigned int f_ref)
  31. {
  32. unsigned int mfi = (pll >> CCM_PLL_MFI_SHIFT)
  33. & CCM_PLL_MFI_MASK;
  34. int mfn = (pll >> CCM_PLL_MFN_SHIFT)
  35. & CCM_PLL_MFN_MASK;
  36. unsigned int mfd = (pll >> CCM_PLL_MFD_SHIFT)
  37. & CCM_PLL_MFD_MASK;
  38. unsigned int pd = (pll >> CCM_PLL_PD_SHIFT)
  39. & CCM_PLL_PD_MASK;
  40. mfi = mfi <= 5 ? 5 : mfi;
  41. mfn = mfn >= 512 ? mfn - 1024 : mfn;
  42. mfd += 1;
  43. pd += 1;
  44. return lldiv(2 * (u64) f_ref * (mfi * mfd + mfn),
  45. mfd * pd);
  46. }
  47. static ulong imx_get_mpllclk(void)
  48. {
  49. struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE;
  50. ulong fref = MXC_HCLK;
  51. return imx_decode_pll(readl(&ccm->mpctl), fref);
  52. }
  53. static ulong imx_get_upllclk(void)
  54. {
  55. struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE;
  56. ulong fref = MXC_HCLK;
  57. return imx_decode_pll(readl(&ccm->upctl), fref);
  58. }
  59. static ulong imx_get_armclk(void)
  60. {
  61. struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE;
  62. ulong cctl = readl(&ccm->cctl);
  63. ulong fref = imx_get_mpllclk();
  64. ulong div;
  65. if (cctl & CCM_CCTL_ARM_SRC)
  66. fref = lldiv((u64) fref * 3, 4);
  67. div = ((cctl >> CCM_CCTL_ARM_DIV_SHIFT)
  68. & CCM_CCTL_ARM_DIV_MASK) + 1;
  69. return fref / div;
  70. }
  71. static ulong imx_get_ahbclk(void)
  72. {
  73. struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE;
  74. ulong cctl = readl(&ccm->cctl);
  75. ulong fref = imx_get_armclk();
  76. ulong div;
  77. div = ((cctl >> CCM_CCTL_AHB_DIV_SHIFT)
  78. & CCM_CCTL_AHB_DIV_MASK) + 1;
  79. return fref / div;
  80. }
  81. static ulong imx_get_ipgclk(void)
  82. {
  83. return imx_get_ahbclk() / 2;
  84. }
  85. static ulong imx_get_perclk(int clk)
  86. {
  87. struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE;
  88. ulong fref = readl(&ccm->mcr) & (1 << clk) ? imx_get_upllclk() :
  89. imx_get_ahbclk();
  90. ulong div;
  91. div = readl(&ccm->pcdr[CCM_PERCLK_REG(clk)]);
  92. div = ((div >> CCM_PERCLK_SHIFT(clk)) & CCM_PERCLK_MASK) + 1;
  93. return fref / div;
  94. }
  95. int imx_set_perclk(enum mxc_clock clk, bool from_upll, unsigned int freq)
  96. {
  97. struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE;
  98. ulong fref = from_upll ? imx_get_upllclk() : imx_get_ahbclk();
  99. ulong div = (fref + freq - 1) / freq;
  100. if (clk > MXC_UART_CLK || !div || --div > CCM_PERCLK_MASK)
  101. return -EINVAL;
  102. clrsetbits_le32(&ccm->pcdr[CCM_PERCLK_REG(clk)],
  103. CCM_PERCLK_MASK << CCM_PERCLK_SHIFT(clk),
  104. div << CCM_PERCLK_SHIFT(clk));
  105. if (from_upll)
  106. setbits_le32(&ccm->mcr, 1 << clk);
  107. else
  108. clrbits_le32(&ccm->mcr, 1 << clk);
  109. return 0;
  110. }
  111. unsigned int mxc_get_clock(enum mxc_clock clk)
  112. {
  113. if (clk >= MXC_CLK_NUM)
  114. return -1;
  115. switch (clk) {
  116. case MXC_ARM_CLK:
  117. return imx_get_armclk();
  118. case MXC_AHB_CLK:
  119. return imx_get_ahbclk();
  120. case MXC_IPG_CLK:
  121. case MXC_CSPI_CLK:
  122. case MXC_FEC_CLK:
  123. return imx_get_ipgclk();
  124. default:
  125. return imx_get_perclk(clk);
  126. }
  127. }
  128. u32 get_cpu_rev(void)
  129. {
  130. u32 srev;
  131. u32 system_rev = 0x25000;
  132. /* read SREV register from IIM module */
  133. struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE;
  134. srev = readl(&iim->iim_srev);
  135. switch (srev) {
  136. case 0x00:
  137. system_rev |= CHIP_REV_1_0;
  138. break;
  139. case 0x01:
  140. system_rev |= CHIP_REV_1_1;
  141. break;
  142. case 0x02:
  143. system_rev |= CHIP_REV_1_2;
  144. break;
  145. default:
  146. system_rev |= 0x8000;
  147. break;
  148. }
  149. return system_rev;
  150. }
  151. #if defined(CONFIG_DISPLAY_CPUINFO)
  152. static char *get_reset_cause(void)
  153. {
  154. /* read RCSR register from CCM module */
  155. struct ccm_regs *ccm =
  156. (struct ccm_regs *)IMX_CCM_BASE;
  157. u32 cause = readl(&ccm->rcsr) & 0x0f;
  158. if (cause == 0)
  159. return "POR";
  160. else if (cause == 1)
  161. return "RST";
  162. else if ((cause & 2) == 2)
  163. return "WDOG";
  164. else if ((cause & 4) == 4)
  165. return "SW RESET";
  166. else if ((cause & 8) == 8)
  167. return "JTAG";
  168. else
  169. return "unknown reset";
  170. }
  171. int print_cpuinfo(void)
  172. {
  173. char buf[32];
  174. u32 cpurev = get_cpu_rev();
  175. printf("CPU: Freescale i.MX25 rev%d.%d%s at %s MHz\n",
  176. (cpurev & 0xF0) >> 4, (cpurev & 0x0F),
  177. ((cpurev & 0x8000) ? " unknown" : ""),
  178. strmhz(buf, imx_get_armclk()));
  179. printf("Reset cause: %s\n", get_reset_cause());
  180. return 0;
  181. }
  182. #endif
  183. #if defined(CONFIG_FEC_MXC)
  184. /*
  185. * Initializes on-chip ethernet controllers.
  186. * to override, implement board_eth_init()
  187. */
  188. int cpu_eth_init(bd_t *bis)
  189. {
  190. struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE;
  191. ulong val;
  192. val = readl(&ccm->cgr0);
  193. val |= (1 << 23);
  194. writel(val, &ccm->cgr0);
  195. return fecmxc_initialize(bis);
  196. }
  197. #endif
  198. int get_clocks(void)
  199. {
  200. #ifdef CONFIG_FSL_ESDHC_IMX
  201. #if CONFIG_SYS_FSL_ESDHC_ADDR == IMX_MMC_SDHC2_BASE
  202. gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
  203. #else
  204. gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC1_CLK);
  205. #endif
  206. #endif
  207. return 0;
  208. }
  209. #ifdef CONFIG_FSL_ESDHC_IMX
  210. /*
  211. * Initializes on-chip MMC controllers.
  212. * to override, implement board_mmc_init()
  213. */
  214. int cpu_mmc_init(bd_t *bis)
  215. {
  216. return fsl_esdhc_mmc_init(bis);
  217. }
  218. #endif
  219. #ifdef CONFIG_FEC_MXC
  220. void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
  221. {
  222. int i;
  223. struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE;
  224. struct fuse_bank *bank = &iim->bank[0];
  225. struct fuse_bank0_regs *fuse =
  226. (struct fuse_bank0_regs *)bank->fuse_regs;
  227. for (i = 0; i < 6; i++)
  228. mac[i] = readl(&fuse->mac_addr[i]) & 0xff;
  229. }
  230. #endif /* CONFIG_FEC_MXC */