generic.c 12 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2007
  4. * Sascha Hauer, Pengutronix
  5. *
  6. * (C) Copyright 2008-2010 Freescale Semiconductor, Inc.
  7. */
  8. #include <common.h>
  9. #include <clock_legacy.h>
  10. #include <div64.h>
  11. #include <asm/io.h>
  12. #include <linux/errno.h>
  13. #include <asm/arch/imx-regs.h>
  14. #include <asm/arch/crm_regs.h>
  15. #include <asm/arch/clock.h>
  16. #include <asm/arch/sys_proto.h>
  17. #ifdef CONFIG_FSL_ESDHC_IMX
  18. #include <fsl_esdhc_imx.h>
  19. #endif
  20. #include <netdev.h>
  21. #include <spl.h>
  22. #define CLK_CODE(arm, ahb, sel) (((arm) << 16) + ((ahb) << 8) + (sel))
  23. #define CLK_CODE_ARM(c) (((c) >> 16) & 0xFF)
  24. #define CLK_CODE_AHB(c) (((c) >> 8) & 0xFF)
  25. #define CLK_CODE_PATH(c) ((c) & 0xFF)
  26. #define CCM_GET_DIVIDER(x, m, o) (((x) & (m)) >> (o))
  27. #ifdef CONFIG_FSL_ESDHC_IMX
  28. DECLARE_GLOBAL_DATA_PTR;
  29. #endif
  30. static int g_clk_mux_auto[8] = {
  31. CLK_CODE(1, 3, 0), CLK_CODE(1, 2, 1), CLK_CODE(2, 1, 1), -1,
  32. CLK_CODE(1, 6, 0), CLK_CODE(1, 4, 1), CLK_CODE(2, 2, 1), -1,
  33. };
  34. static int g_clk_mux_consumer[16] = {
  35. CLK_CODE(1, 4, 0), CLK_CODE(1, 3, 1), CLK_CODE(1, 3, 1), -1,
  36. -1, -1, CLK_CODE(4, 1, 0), CLK_CODE(1, 5, 0),
  37. CLK_CODE(1, 8, 1), CLK_CODE(1, 6, 1), CLK_CODE(2, 4, 0), -1,
  38. -1, -1, CLK_CODE(4, 2, 0), -1,
  39. };
  40. static int hsp_div_table[3][16] = {
  41. {4, 3, 2, -1, -1, -1, 1, 5, 4, 3, 2, -1, -1, -1, 1, -1},
  42. {-1, -1, -1, -1, -1, -1, -1, -1, 8, 6, 4, -1, -1, -1, 2, -1},
  43. {3, -1, -1, -1, -1, -1, -1, -1, 3, -1, -1, -1, -1, -1, -1, -1},
  44. };
  45. u32 get_cpu_rev(void)
  46. {
  47. int reg;
  48. struct iim_regs *iim =
  49. (struct iim_regs *)IIM_BASE_ADDR;
  50. reg = readl(&iim->iim_srev);
  51. if (!reg) {
  52. reg = readw(ROMPATCH_REV);
  53. reg <<= 4;
  54. } else {
  55. reg += CHIP_REV_1_0;
  56. }
  57. return 0x35000 + (reg & 0xFF);
  58. }
  59. static u32 get_arm_div(u32 pdr0, u32 *fi, u32 *fd)
  60. {
  61. int *pclk_mux;
  62. if (pdr0 & MXC_CCM_PDR0_AUTO_CON) {
  63. pclk_mux = g_clk_mux_consumer +
  64. ((pdr0 & MXC_CCM_PDR0_CON_MUX_DIV_MASK) >>
  65. MXC_CCM_PDR0_CON_MUX_DIV_OFFSET);
  66. } else {
  67. pclk_mux = g_clk_mux_auto +
  68. ((pdr0 & MXC_CCM_PDR0_AUTO_MUX_DIV_MASK) >>
  69. MXC_CCM_PDR0_AUTO_MUX_DIV_OFFSET);
  70. }
  71. if ((*pclk_mux) == -1)
  72. return -1;
  73. if (fi && fd) {
  74. if (!CLK_CODE_PATH(*pclk_mux)) {
  75. *fi = *fd = 1;
  76. return CLK_CODE_ARM(*pclk_mux);
  77. }
  78. if (pdr0 & MXC_CCM_PDR0_AUTO_CON) {
  79. *fi = 3;
  80. *fd = 4;
  81. } else {
  82. *fi = 2;
  83. *fd = 3;
  84. }
  85. }
  86. return CLK_CODE_ARM(*pclk_mux);
  87. }
  88. static int get_ahb_div(u32 pdr0)
  89. {
  90. int *pclk_mux;
  91. pclk_mux = g_clk_mux_consumer +
  92. ((pdr0 & MXC_CCM_PDR0_CON_MUX_DIV_MASK) >>
  93. MXC_CCM_PDR0_CON_MUX_DIV_OFFSET);
  94. if ((*pclk_mux) == -1)
  95. return -1;
  96. return CLK_CODE_AHB(*pclk_mux);
  97. }
  98. static u32 decode_pll(u32 reg, u32 infreq)
  99. {
  100. u32 mfi = (reg >> 10) & 0xf;
  101. s32 mfn = reg & 0x3ff;
  102. u32 mfd = (reg >> 16) & 0x3ff;
  103. u32 pd = (reg >> 26) & 0xf;
  104. mfi = mfi <= 5 ? 5 : mfi;
  105. mfn = mfn >= 512 ? mfn - 1024 : mfn;
  106. mfd += 1;
  107. pd += 1;
  108. return lldiv(2 * (u64)infreq * (mfi * mfd + mfn),
  109. mfd * pd);
  110. }
  111. static u32 get_mcu_main_clk(void)
  112. {
  113. u32 arm_div = 0, fi = 0, fd = 0;
  114. struct ccm_regs *ccm =
  115. (struct ccm_regs *)IMX_CCM_BASE;
  116. arm_div = get_arm_div(readl(&ccm->pdr0), &fi, &fd);
  117. fi *= decode_pll(readl(&ccm->mpctl), MXC_HCLK);
  118. return fi / (arm_div * fd);
  119. }
  120. static u32 get_ipg_clk(void)
  121. {
  122. u32 freq = get_mcu_main_clk();
  123. struct ccm_regs *ccm =
  124. (struct ccm_regs *)IMX_CCM_BASE;
  125. u32 pdr0 = readl(&ccm->pdr0);
  126. return freq / (get_ahb_div(pdr0) * 2);
  127. }
  128. static u32 get_ipg_per_clk(void)
  129. {
  130. u32 freq = get_mcu_main_clk();
  131. struct ccm_regs *ccm =
  132. (struct ccm_regs *)IMX_CCM_BASE;
  133. u32 pdr0 = readl(&ccm->pdr0);
  134. u32 pdr4 = readl(&ccm->pdr4);
  135. u32 div;
  136. if (pdr0 & MXC_CCM_PDR0_PER_SEL) {
  137. div = CCM_GET_DIVIDER(pdr4,
  138. MXC_CCM_PDR4_PER0_PODF_MASK,
  139. MXC_CCM_PDR4_PER0_PODF_OFFSET) + 1;
  140. } else {
  141. div = CCM_GET_DIVIDER(pdr0,
  142. MXC_CCM_PDR0_PER_PODF_MASK,
  143. MXC_CCM_PDR0_PER_PODF_OFFSET) + 1;
  144. div *= get_ahb_div(pdr0);
  145. }
  146. return freq / div;
  147. }
  148. u32 imx_get_uartclk(void)
  149. {
  150. u32 freq;
  151. struct ccm_regs *ccm =
  152. (struct ccm_regs *)IMX_CCM_BASE;
  153. u32 pdr4 = readl(&ccm->pdr4);
  154. if (readl(&ccm->pdr3) & MXC_CCM_PDR3_UART_M_U)
  155. freq = get_mcu_main_clk();
  156. else
  157. freq = decode_pll(readl(&ccm->ppctl), MXC_HCLK);
  158. freq /= CCM_GET_DIVIDER(pdr4,
  159. MXC_CCM_PDR4_UART_PODF_MASK,
  160. MXC_CCM_PDR4_UART_PODF_OFFSET) + 1;
  161. return freq;
  162. }
  163. unsigned int mxc_get_main_clock(enum mxc_main_clock clk)
  164. {
  165. u32 nfc_pdf, hsp_podf;
  166. u32 pll, ret_val = 0, usb_podf;
  167. struct ccm_regs *ccm =
  168. (struct ccm_regs *)IMX_CCM_BASE;
  169. u32 reg = readl(&ccm->pdr0);
  170. u32 reg4 = readl(&ccm->pdr4);
  171. reg |= 0x1;
  172. switch (clk) {
  173. case CPU_CLK:
  174. ret_val = get_mcu_main_clk();
  175. break;
  176. case AHB_CLK:
  177. ret_val = get_mcu_main_clk();
  178. break;
  179. case HSP_CLK:
  180. if (reg & CLKMODE_CONSUMER) {
  181. hsp_podf = (reg >> 20) & 0x3;
  182. pll = get_mcu_main_clk();
  183. hsp_podf = hsp_div_table[hsp_podf][(reg>>16)&0xF];
  184. if (hsp_podf > 0) {
  185. ret_val = pll / hsp_podf;
  186. } else {
  187. puts("mismatch HSP with ARM clock setting\n");
  188. ret_val = 0;
  189. }
  190. } else {
  191. ret_val = get_mcu_main_clk();
  192. }
  193. break;
  194. case IPG_CLK:
  195. ret_val = get_ipg_clk();
  196. break;
  197. case IPG_PER_CLK:
  198. ret_val = get_ipg_per_clk();
  199. break;
  200. case NFC_CLK:
  201. nfc_pdf = (reg4 >> 28) & 0xF;
  202. pll = get_mcu_main_clk();
  203. /* AHB/nfc_pdf */
  204. ret_val = pll / (nfc_pdf + 1);
  205. break;
  206. case USB_CLK:
  207. usb_podf = (reg4 >> 22) & 0x3F;
  208. if (reg4 & 0x200)
  209. pll = get_mcu_main_clk();
  210. else
  211. pll = decode_pll(readl(&ccm->ppctl), MXC_HCLK);
  212. ret_val = pll / (usb_podf + 1);
  213. break;
  214. default:
  215. printf("Unknown clock: %d\n", clk);
  216. break;
  217. }
  218. return ret_val;
  219. }
  220. unsigned int mxc_get_peri_clock(enum mxc_peri_clock clk)
  221. {
  222. u32 ret_val = 0, pdf, pre_pdf, clk_sel;
  223. struct ccm_regs *ccm =
  224. (struct ccm_regs *)IMX_CCM_BASE;
  225. u32 mpdr2 = readl(&ccm->pdr2);
  226. u32 mpdr3 = readl(&ccm->pdr3);
  227. u32 mpdr4 = readl(&ccm->pdr4);
  228. switch (clk) {
  229. case UART1_BAUD:
  230. case UART2_BAUD:
  231. case UART3_BAUD:
  232. clk_sel = mpdr3 & (1 << 14);
  233. pdf = (mpdr4 >> 10) & 0x3F;
  234. ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) :
  235. decode_pll(readl(&ccm->ppctl), MXC_HCLK)) / (pdf + 1);
  236. break;
  237. case SSI1_BAUD:
  238. pre_pdf = (mpdr2 >> 24) & 0x7;
  239. pdf = mpdr2 & 0x3F;
  240. clk_sel = mpdr2 & (1 << 6);
  241. ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) :
  242. decode_pll(readl(&ccm->ppctl), MXC_HCLK)) /
  243. ((pre_pdf + 1) * (pdf + 1));
  244. break;
  245. case SSI2_BAUD:
  246. pre_pdf = (mpdr2 >> 27) & 0x7;
  247. pdf = (mpdr2 >> 8) & 0x3F;
  248. clk_sel = mpdr2 & (1 << 6);
  249. ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) :
  250. decode_pll(readl(&ccm->ppctl), MXC_HCLK)) /
  251. ((pre_pdf + 1) * (pdf + 1));
  252. break;
  253. case CSI_BAUD:
  254. clk_sel = mpdr2 & (1 << 7);
  255. pdf = (mpdr2 >> 16) & 0x3F;
  256. ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) :
  257. decode_pll(readl(&ccm->ppctl), MXC_HCLK)) / (pdf + 1);
  258. break;
  259. case MSHC_CLK:
  260. pre_pdf = readl(&ccm->pdr1);
  261. clk_sel = (pre_pdf & 0x80);
  262. pdf = (pre_pdf >> 22) & 0x3F;
  263. pre_pdf = (pre_pdf >> 28) & 0x7;
  264. ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) :
  265. decode_pll(readl(&ccm->ppctl), MXC_HCLK)) /
  266. ((pre_pdf + 1) * (pdf + 1));
  267. break;
  268. case ESDHC1_CLK:
  269. clk_sel = mpdr3 & 0x40;
  270. pdf = mpdr3 & 0x3F;
  271. ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) :
  272. decode_pll(readl(&ccm->ppctl), MXC_HCLK)) / (pdf + 1);
  273. break;
  274. case ESDHC2_CLK:
  275. clk_sel = mpdr3 & 0x40;
  276. pdf = (mpdr3 >> 8) & 0x3F;
  277. ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) :
  278. decode_pll(readl(&ccm->ppctl), MXC_HCLK)) / (pdf + 1);
  279. break;
  280. case ESDHC3_CLK:
  281. clk_sel = mpdr3 & 0x40;
  282. pdf = (mpdr3 >> 16) & 0x3F;
  283. ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) :
  284. decode_pll(readl(&ccm->ppctl), MXC_HCLK)) / (pdf + 1);
  285. break;
  286. case SPDIF_CLK:
  287. clk_sel = mpdr3 & 0x400000;
  288. pre_pdf = (mpdr3 >> 29) & 0x7;
  289. pdf = (mpdr3 >> 23) & 0x3F;
  290. ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) :
  291. decode_pll(readl(&ccm->ppctl), MXC_HCLK)) /
  292. ((pre_pdf + 1) * (pdf + 1));
  293. break;
  294. default:
  295. printf("%s(): This clock: %d not supported yet\n",
  296. __func__, clk);
  297. break;
  298. }
  299. return ret_val;
  300. }
  301. unsigned int mxc_get_clock(enum mxc_clock clk)
  302. {
  303. switch (clk) {
  304. case MXC_ARM_CLK:
  305. return get_mcu_main_clk();
  306. case MXC_AHB_CLK:
  307. break;
  308. case MXC_IPG_CLK:
  309. return get_ipg_clk();
  310. case MXC_IPG_PERCLK:
  311. case MXC_I2C_CLK:
  312. return get_ipg_per_clk();
  313. case MXC_UART_CLK:
  314. return imx_get_uartclk();
  315. case MXC_ESDHC1_CLK:
  316. return mxc_get_peri_clock(ESDHC1_CLK);
  317. case MXC_ESDHC2_CLK:
  318. return mxc_get_peri_clock(ESDHC2_CLK);
  319. case MXC_ESDHC3_CLK:
  320. return mxc_get_peri_clock(ESDHC3_CLK);
  321. case MXC_USB_CLK:
  322. return mxc_get_main_clock(USB_CLK);
  323. case MXC_FEC_CLK:
  324. return get_ipg_clk();
  325. case MXC_CSPI_CLK:
  326. return get_ipg_clk();
  327. }
  328. return -1;
  329. }
  330. #ifdef CONFIG_FEC_MXC
  331. /*
  332. * The MX35 has no fuse for MAC, return a NULL MAC
  333. */
  334. void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
  335. {
  336. memset(mac, 0, 6);
  337. }
  338. u32 imx_get_fecclk(void)
  339. {
  340. return mxc_get_clock(MXC_IPG_CLK);
  341. }
  342. #endif
  343. int do_mx35_showclocks(cmd_tbl_t *cmdtp,
  344. int flag, int argc, char * const argv[])
  345. {
  346. u32 cpufreq = get_mcu_main_clk();
  347. printf("mx35 cpu clock: %dMHz\n", cpufreq / 1000000);
  348. printf("ipg clock : %dHz\n", get_ipg_clk());
  349. printf("ipg per clock : %dHz\n", get_ipg_per_clk());
  350. printf("uart clock : %dHz\n", mxc_get_clock(MXC_UART_CLK));
  351. return 0;
  352. }
  353. U_BOOT_CMD(
  354. clocks, CONFIG_SYS_MAXARGS, 1, do_mx35_showclocks,
  355. "display clocks",
  356. ""
  357. );
  358. #if defined(CONFIG_DISPLAY_CPUINFO)
  359. static char *get_reset_cause(void)
  360. {
  361. /* read RCSR register from CCM module */
  362. struct ccm_regs *ccm =
  363. (struct ccm_regs *)IMX_CCM_BASE;
  364. u32 cause = readl(&ccm->rcsr) & 0x0F;
  365. switch (cause) {
  366. case 0x0000:
  367. return "POR";
  368. case 0x0002:
  369. return "JTAG";
  370. case 0x0004:
  371. return "RST";
  372. case 0x0008:
  373. return "WDOG";
  374. default:
  375. return "unknown reset";
  376. }
  377. }
  378. int print_cpuinfo(void)
  379. {
  380. u32 srev = get_cpu_rev();
  381. printf("CPU: Freescale i.MX35 rev %d.%d at %d MHz.\n",
  382. (srev & 0xF0) >> 4, (srev & 0x0F),
  383. get_mcu_main_clk() / 1000000);
  384. printf("Reset cause: %s\n", get_reset_cause());
  385. return 0;
  386. }
  387. #endif
  388. /*
  389. * Initializes on-chip ethernet controllers.
  390. * to override, implement board_eth_init()
  391. */
  392. int cpu_eth_init(bd_t *bis)
  393. {
  394. int rc = -ENODEV;
  395. #if defined(CONFIG_FEC_MXC)
  396. rc = fecmxc_initialize(bis);
  397. #endif
  398. return rc;
  399. }
  400. #ifdef CONFIG_FSL_ESDHC_IMX
  401. /*
  402. * Initializes on-chip MMC controllers.
  403. * to override, implement board_mmc_init()
  404. */
  405. int cpu_mmc_init(bd_t *bis)
  406. {
  407. return fsl_esdhc_mmc_init(bis);
  408. }
  409. #endif
  410. int get_clocks(void)
  411. {
  412. #ifdef CONFIG_FSL_ESDHC_IMX
  413. #if CONFIG_SYS_FSL_ESDHC_ADDR == MMC_SDHC2_BASE_ADDR
  414. gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
  415. #elif CONFIG_SYS_FSL_ESDHC_ADDR == MMC_SDHC3_BASE_ADDR
  416. gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
  417. #else
  418. gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC1_CLK);
  419. #endif
  420. #endif
  421. return 0;
  422. }
  423. #define RCSR_MEM_CTL_WEIM 0
  424. #define RCSR_MEM_CTL_NAND 1
  425. #define RCSR_MEM_CTL_ATA 2
  426. #define RCSR_MEM_CTL_EXPANSION 3
  427. #define RCSR_MEM_TYPE_NOR 0
  428. #define RCSR_MEM_TYPE_ONENAND 2
  429. #define RCSR_MEM_TYPE_SD 0
  430. #define RCSR_MEM_TYPE_I2C 2
  431. #define RCSR_MEM_TYPE_SPI 3
  432. u32 spl_boot_device(void)
  433. {
  434. struct ccm_regs *ccm =
  435. (struct ccm_regs *)IMX_CCM_BASE;
  436. u32 rcsr = readl(&ccm->rcsr);
  437. u32 mem_type, mem_ctl;
  438. /* In external mode, no boot device is returned */
  439. if ((rcsr >> 10) & 0x03)
  440. return BOOT_DEVICE_NONE;
  441. mem_ctl = (rcsr >> 25) & 0x03;
  442. mem_type = (rcsr >> 23) & 0x03;
  443. switch (mem_ctl) {
  444. case RCSR_MEM_CTL_WEIM:
  445. switch (mem_type) {
  446. case RCSR_MEM_TYPE_NOR:
  447. return BOOT_DEVICE_NOR;
  448. case RCSR_MEM_TYPE_ONENAND:
  449. return BOOT_DEVICE_ONENAND;
  450. default:
  451. return BOOT_DEVICE_NONE;
  452. }
  453. case RCSR_MEM_CTL_NAND:
  454. return BOOT_DEVICE_NAND;
  455. case RCSR_MEM_CTL_EXPANSION:
  456. switch (mem_type) {
  457. case RCSR_MEM_TYPE_SD:
  458. return BOOT_DEVICE_MMC1;
  459. case RCSR_MEM_TYPE_I2C:
  460. return BOOT_DEVICE_I2C;
  461. case RCSR_MEM_TYPE_SPI:
  462. return BOOT_DEVICE_SPI;
  463. default:
  464. return BOOT_DEVICE_NONE;
  465. }
  466. }
  467. return BOOT_DEVICE_NONE;
  468. }