omap3_cairo.h 7.0 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Configuration settings for the QUIPOS Cairo board.
  4. *
  5. * Copyright (C) DENX GmbH
  6. *
  7. * Author :
  8. * Albert ARIBAUD <albert.aribaud@3adev.fr>
  9. *
  10. * Derived from EVM code by
  11. * Manikandan Pillai <mani.pillai@ti.com>
  12. * Itself derived from Beagle Board and 3430 SDP code by
  13. * Richard Woodruff <r-woodruff2@ti.com>
  14. * Syed Mohammed Khasim <khasim@ti.com>
  15. *
  16. * Also derived from include/configs/omap3_beagle.h
  17. */
  18. #ifndef __OMAP3_CAIRO_CONFIG_H
  19. #define __OMAP3_CAIRO_CONFIG_H
  20. /*
  21. * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM
  22. * 64 bytes before this address should be set aside for u-boot.img's
  23. * header. That is 0x800FFFC0--0x80100000 should not be used for any
  24. * other needs. We use this rather than the inherited defines from
  25. * ti_armv7_common.h for backwards compatibility.
  26. */
  27. #define CONFIG_SPL_BSS_START_ADDR 0x80000000
  28. #define CONFIG_SPL_BSS_MAX_SIZE (512 << 10) /* 512 KB */
  29. #define CONFIG_SYS_SPL_MALLOC_START 0x80208000
  30. #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
  31. #include <configs/ti_omap3_common.h>
  32. #define CONFIG_REVISION_TAG 1
  33. #define CONFIG_ENV_OVERWRITE
  34. /* Enable Multi Bus support for I2C */
  35. #define CONFIG_I2C_MULTI_BUS 1
  36. /* Probe all devices */
  37. #define CONFIG_SYS_I2C_NOPROBES { {0x0, 0x0} }
  38. /*
  39. * TWL4030
  40. */
  41. /*
  42. * Board NAND Info.
  43. */
  44. #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */
  45. /* devices */
  46. #define CONFIG_EXTRA_ENV_SETTINGS \
  47. "machid=ffffffff\0" \
  48. "fdt_high=0x87000000\0" \
  49. "baudrate=115200\0" \
  50. "fec_addr=00:50:C2:7E:90:F0\0" \
  51. "netmask=255.255.255.0\0" \
  52. "ipaddr=192.168.2.9\0" \
  53. "gateway=192.168.2.1\0" \
  54. "serverip=192.168.2.10\0" \
  55. "nfshost=192.168.2.10\0" \
  56. "stdin=serial\0" \
  57. "stdout=serial\0" \
  58. "stderr=serial\0" \
  59. "bootargs_mmc_ramdisk=mem=128M " \
  60. "console=ttyO1,115200n8 " \
  61. "root=/dev/ram0 rw " \
  62. "initrd=0x81600000,16M " \
  63. "mpurate=600 ramdisk_size=16384 omapfb.rotate=1 " \
  64. "omapfb.rotate_type=1 omap_vout.vid1_static_vrfb_alloc=y\0" \
  65. "mmcboot=mmc init; " \
  66. "fatload mmc 0 0x80000000 uImage; " \
  67. "fatload mmc 0 0x81600000 ramdisk.gz; " \
  68. "setenv bootargs ${bootargs_mmc_ramdisk}; " \
  69. "bootm 0x80000000\0" \
  70. "bootargs_nfs=mem=99M console=ttyO0,115200n8 noinitrd rw ip=dhcp " \
  71. "root=/dev/nfs " \
  72. "nfsroot=192.168.2.10:/home/spiid/workdir/Quipos/rootfs,nolock " \
  73. "mpurate=600 omapfb.rotate=1 omapfb.rotate_type=1 " \
  74. "omap_vout.vid1_static_vrfb_alloc=y\0" \
  75. "boot_nfs=run get_kernel; setenv bootargs ${bootargs_nfs}; " \
  76. "bootm 0x80000000\0" \
  77. "bootargs_nand=mem=128M console=ttyO1,115200n8 noinitrd " \
  78. "root=/dev/mtdblock4 rw rootfstype=jffs2 mpurate=600 " \
  79. "omap_vout.vid1_static_vrfb_alloc=y omapfb.rotate=1 " \
  80. "omapfb.rotate_type=1\0" \
  81. "boot_nand=nand read.i 0x80000000 280000 300000; setenv " \
  82. "bootargs ${bootargs_nand}; bootm 0x80000000\0" \
  83. "ledorange=i2c dev 1; i2c mw 60 00 00 1; i2c mw 60 14 FF 1; " \
  84. "i2c mw 60 15 FF 1; i2c mw 60 16 FF 1; i2c mw 60 17 FF 1; " \
  85. "i2c mw 60 09 10 1; i2c mw 60 06 10 1\0" \
  86. "ledgreen=i2c dev 1; i2c mw 60 00 00 1; i2c mw 60 14 FF 1; " \
  87. "i2c mw 60 15 FF 1; i2c mw 60 16 FF 1; i2c mw 60 17 FF 1; i2c " \
  88. "mw 60 09 00 1; i2c mw 60 06 10 1\0" \
  89. "ledoff=i2c dev 1; i2c mw 60 00 00 1; i2c mw 60 14 FF 1; " \
  90. "i2c mw 60 15 FF 1; i2c mw 60 16 FF 1; i2c mw 60 17 FF 1; " \
  91. "i2c mw 60 09 00 1; i2c mw 60 06 0 1\0" \
  92. "ledred=i2c dev 1; i2c mw 60 00 00 1; i2c mw 60 14 FF 1; " \
  93. "i2c mw 60 15 FF 1; i2c mw 60 16 FF 1; i2c mw 60 17 FF 1; " \
  94. "i2c mw 60 09 10 1; i2c mw 60 06 0 1\0" \
  95. "flash_xloader=mw.b 0x81600000 0xff 0x20000; " \
  96. "nand erase 0 20000; " \
  97. "fatload mmc 0 0x81600000 MLO; " \
  98. "nandecc hw; " \
  99. "nand write.i 0x81600000 0 20000;\0" \
  100. "flash_uboot=mw.b 0x81600000 0xff 0x40000; " \
  101. "nand erase 80000 40000; " \
  102. "fatload mmc 0 0x81600000 u-boot.bin; " \
  103. "nandecc sw; " \
  104. "nand write.i 0x81600000 80000 40000;\0" \
  105. "flash_kernel=mw.b 0x81600000 0xff 0x300000; " \
  106. "nand erase 280000 300000; " \
  107. "fatload mmc 0 0x81600000 uImage; " \
  108. "nandecc sw; " \
  109. "nand write.i 0x81600000 280000 300000;\0" \
  110. "flash_rootfs=fatload mmc 0 0x81600000 rootfs.jffs2; " \
  111. "nandecc sw; " \
  112. "nand write.jffs2 0x680000 0xFF ${filesize}; " \
  113. "nand erase 680000 ${filesize}; " \
  114. "nand write.jffs2 81600000 680000 ${filesize};\0" \
  115. "flash_scrub=nand scrub; " \
  116. "run flash_xloader; " \
  117. "run flash_uboot; " \
  118. "run flash_kernel; " \
  119. "run flash_rootfs;\0" \
  120. "flash_all=run ledred; " \
  121. "nand erase.chip; " \
  122. "run ledorange; " \
  123. "run flash_xloader; " \
  124. "run flash_uboot; " \
  125. "run flash_kernel; " \
  126. "run flash_rootfs; " \
  127. "run ledgreen; " \
  128. "run boot_nand; \0" \
  129. #define CONFIG_BOOTCOMMAND \
  130. "if fatload mmc 0 0x81600000 MLO; then run flash_all; " \
  131. "else run boot_nand; fi"
  132. /*
  133. * OMAP3 has 12 GP timers, they can be driven by the system clock
  134. * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
  135. * This rate is divided by a local divisor.
  136. */
  137. #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
  138. /*-----------------------------------------------------------------------
  139. * FLASH and environment organization
  140. */
  141. /* **** PISMO SUPPORT *** */
  142. #if defined(CONFIG_CMD_NAND)
  143. #define CONFIG_SYS_FLASH_BASE NAND_BASE
  144. #endif
  145. /* Monitor at start of flash */
  146. #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
  147. #define CONFIG_SYS_ONENAND_BASE ONENAND_MAP
  148. #define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */
  149. /* Defines for SPL */
  150. /* NAND boot config */
  151. #define CONFIG_SYS_NAND_5_ADDR_CYCLE
  152. #define CONFIG_SYS_NAND_PAGE_COUNT 64
  153. #define CONFIG_SYS_NAND_PAGE_SIZE 2048
  154. #define CONFIG_SYS_NAND_OOBSIZE 64
  155. #define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024)
  156. #define CONFIG_SYS_NAND_BAD_BLOCK_POS 0
  157. #define CONFIG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9,\
  158. 10, 11, 12, 13}
  159. #define CONFIG_SYS_NAND_ECCSIZE 512
  160. #define CONFIG_SYS_NAND_ECCBYTES 3
  161. #define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_HW
  162. #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000
  163. /* NAND: SPL falcon mode configs */
  164. #ifdef CONFIG_SPL_OS_BOOT
  165. #define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x280000
  166. #endif
  167. /* env defaults */
  168. #define CONFIG_BOOTFILE "uImage"
  169. /* Provide the MACH_TYPE value the vendor kernel requires */
  170. #define CONFIG_MACH_TYPE 3063
  171. /*-----------------------------------------------------------------------
  172. * FLASH and environment organization
  173. */
  174. /* **** PISMO SUPPORT *** */
  175. #define CONFIG_SYS_MAX_FLASH_SECT 520 /* max number of sectors */
  176. /* on one chip */
  177. #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of flash banks */
  178. /*-----------------------------------------------------------------------
  179. * CFI FLASH driver setup
  180. */
  181. /* timeout values are in ticks */
  182. #define CONFIG_SYS_FLASH_ERASE_TOUT (100 * CONFIG_SYS_HZ)
  183. #define CONFIG_SYS_FLASH_WRITE_TOUT (100 * CONFIG_SYS_HZ)
  184. /* Flash banks JFFS2 should use */
  185. #define CONFIG_SYS_MAX_MTD_BANKS (CONFIG_SYS_MAX_FLASH_BANKS + \
  186. CONFIG_SYS_MAX_NAND_DEVICE)
  187. #define CONFIG_SYS_JFFS2_MEM_NAND
  188. /* use flash_info[2] */
  189. #define CONFIG_SYS_JFFS2_FIRST_BANK CONFIG_SYS_MAX_FLASH_BANKS
  190. #define CONFIG_SYS_JFFS2_NUM_BANKS 1
  191. #endif /* __OMAP3_CAIRO_CONFIG_H */