vme8349.h 16 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * esd vme8349 U-Boot configuration file
  4. * Copyright (c) 2008, 2009 esd gmbh Hannover Germany
  5. *
  6. * (C) Copyright 2006-2010
  7. * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  8. *
  9. * reinhard.arlt@esd-electronics.de
  10. * Based on the MPC8349EMDS config.
  11. */
  12. /*
  13. * vme8349 board configuration file.
  14. */
  15. #ifndef __CONFIG_H
  16. #define __CONFIG_H
  17. /*
  18. * Top level Makefile configuration choices
  19. */
  20. #ifdef CONFIG_CADDY2
  21. #define VME_CADDY2
  22. #endif
  23. /*
  24. * High Level Configuration Options
  25. */
  26. #define CONFIG_E300 1 /* E300 Family */
  27. #define CONFIG_VME8349 1 /* ESD VME8349 board specific */
  28. /* Don't enable PCI2 on vme834x - it doesn't exist physically. */
  29. #undef CONFIG_MPC83XX_PCI2 /* support for 2nd PCI controller */
  30. #define CONFIG_PCI_66M
  31. #ifdef CONFIG_PCI_66M
  32. #define CONFIG_83XX_CLKIN 66000000 /* in Hz */
  33. #else
  34. #define CONFIG_83XX_CLKIN 33000000 /* in Hz */
  35. #endif
  36. #ifndef CONFIG_SYS_CLK_FREQ
  37. #ifdef CONFIG_PCI_66M
  38. #define CONFIG_SYS_CLK_FREQ 66000000
  39. #define HRCWL_CSB_TO_CLKIN HRCWL_CSB_TO_CLKIN_4X1
  40. #else
  41. #define CONFIG_SYS_CLK_FREQ 33000000
  42. #define HRCWL_CSB_TO_CLKIN HRCWL_CSB_TO_CLKIN_8X1
  43. #endif
  44. #endif
  45. #define CONFIG_SYS_IMMR 0xE0000000
  46. #undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */
  47. #define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest region */
  48. #define CONFIG_SYS_MEMTEST_END 0x00100000
  49. /*
  50. * DDR Setup
  51. */
  52. #define CONFIG_DDR_ECC /* only for ECC DDR module */
  53. #define CONFIG_DDR_ECC_CMD /* use DDR ECC user commands */
  54. #define CONFIG_SPD_EEPROM
  55. #define SPD_EEPROM_ADDRESS 0x54
  56. #define CONFIG_SYS_READ_SPD vme8349_read_spd
  57. #define CONFIG_SYS_83XX_DDR_USES_CS0 /* esd; Fsl board uses CS2/CS3 */
  58. /*
  59. * 32-bit data path mode.
  60. *
  61. * Please note that using this mode for devices with the real density of 64-bit
  62. * effectively reduces the amount of available memory due to the effect of
  63. * wrapping around while translating address to row/columns, for example in the
  64. * 256MB module the upper 128MB get aliased with contents of the lower
  65. * 128MB); normally this define should be used for devices with real 32-bit
  66. * data path.
  67. */
  68. #undef CONFIG_DDR_32BIT
  69. #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is sys memory*/
  70. #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
  71. #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
  72. #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN \
  73. | DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075)
  74. #define CONFIG_DDR_2T_TIMING
  75. #define CONFIG_SYS_DDRCDR (DDRCDR_DHC_EN \
  76. | DDRCDR_ODT \
  77. | DDRCDR_Q_DRN)
  78. /* 0x80080001 */
  79. /*
  80. * FLASH on the Local Bus
  81. */
  82. #ifdef VME_CADDY2
  83. #define CONFIG_SYS_FLASH_BASE 0xffc00000 /* start of FLASH */
  84. #define CONFIG_SYS_FLASH_SIZE 4 /* flash size in MB */
  85. #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | \
  86. BR_PS_16 | /* 16bit */ \
  87. BR_MS_GPCM | /* MSEL = GPCM */ \
  88. BR_V) /* valid */
  89. #define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
  90. | OR_GPCM_XAM \
  91. | OR_GPCM_CSNT \
  92. | OR_GPCM_ACS_DIV2 \
  93. | OR_GPCM_XACS \
  94. | OR_GPCM_SCY_15 \
  95. | OR_GPCM_TRLX_SET \
  96. | OR_GPCM_EHTR_SET \
  97. | OR_GPCM_EAD)
  98. /* 0xffc06ff7 */
  99. #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
  100. #define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_4MB)
  101. #else
  102. #define CONFIG_SYS_FLASH_BASE 0xf8000000 /* start of FLASH */
  103. #define CONFIG_SYS_FLASH_SIZE 128 /* flash size in MB */
  104. #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | \
  105. BR_PS_16 | /* 16bit */ \
  106. BR_MS_GPCM | /* MSEL = GPCM */ \
  107. BR_V) /* valid */
  108. #define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
  109. | OR_GPCM_XAM \
  110. | OR_GPCM_CSNT \
  111. | OR_GPCM_ACS_DIV2 \
  112. | OR_GPCM_XACS \
  113. | OR_GPCM_SCY_15 \
  114. | OR_GPCM_TRLX_SET \
  115. | OR_GPCM_EHTR_SET \
  116. | OR_GPCM_EAD)
  117. /* 0xf8006ff7 */
  118. #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
  119. #define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_128MB)
  120. #endif
  121. #define CONFIG_SYS_WINDOW1_BASE 0xf0000000
  122. #define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_WINDOW1_BASE \
  123. | BR_PS_32 \
  124. | BR_MS_GPCM \
  125. | BR_V)
  126. /* 0xF0001801 */
  127. #define CONFIG_SYS_OR1_PRELIM (OR_AM_256KB \
  128. | OR_GPCM_SETA)
  129. /* 0xfffc0208 */
  130. #define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_WINDOW1_BASE
  131. #define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_256KB)
  132. #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
  133. #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device*/
  134. #undef CONFIG_SYS_FLASH_CHECKSUM
  135. #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase TO (ms) */
  136. #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write TO (ms) */
  137. #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
  138. #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
  139. #define CONFIG_SYS_RAMBOOT
  140. #else
  141. #undef CONFIG_SYS_RAMBOOT
  142. #endif
  143. #define CONFIG_SYS_INIT_RAM_LOCK 1
  144. #define CONFIG_SYS_INIT_RAM_ADDR 0xF7000000 /* Initial RAM addr */
  145. #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* size */
  146. #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
  147. GENERATED_GBL_DATA_SIZE)
  148. #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
  149. #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB */
  150. #define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Malloc size */
  151. /*
  152. * Local Bus LCRR and LBCR regs
  153. * LCRR: no DLL bypass, Clock divider is 4
  154. * External Local Bus rate is
  155. * CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV
  156. */
  157. #define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4
  158. #define CONFIG_SYS_LBC_LBCR 0x00000000
  159. #undef CONFIG_SYS_LB_SDRAM /* if board has SDRAM on local bus */
  160. /*
  161. * Serial Port
  162. */
  163. #define CONFIG_SYS_NS16550_SERIAL
  164. #define CONFIG_SYS_NS16550_REG_SIZE 1
  165. #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
  166. #define CONFIG_SYS_BAUDRATE_TABLE \
  167. {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
  168. #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500)
  169. #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600)
  170. /* I2C */
  171. #define CONFIG_SYS_I2C
  172. #define CONFIG_SYS_I2C_FSL
  173. #define CONFIG_SYS_FSL_I2C_SPEED 400000
  174. #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
  175. #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
  176. #define CONFIG_SYS_FSL_I2C2_SPEED 400000
  177. #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
  178. #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
  179. #define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} }
  180. /* could also use CONFIG_I2C_MULTI_BUS and CONFIG_SYS_SPD_BUS_NUM... */
  181. #define CONFIG_SYS_I2C_8574_ADDR2 0x20 /* I2C1, PCF8574 */
  182. /* TSEC */
  183. #define CONFIG_SYS_TSEC1_OFFSET 0x24000
  184. #define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC1_OFFSET)
  185. #define CONFIG_SYS_TSEC2_OFFSET 0x25000
  186. #define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC2_OFFSET)
  187. /*
  188. * General PCI
  189. * Addresses are mapped 1-1.
  190. */
  191. #define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
  192. #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
  193. #define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */
  194. #define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000
  195. #define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE
  196. #define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */
  197. #define CONFIG_SYS_PCI1_IO_BASE 0x00000000
  198. #define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000
  199. #define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */
  200. #define CONFIG_SYS_PCI2_MEM_BASE 0xA0000000
  201. #define CONFIG_SYS_PCI2_MEM_PHYS CONFIG_SYS_PCI2_MEM_BASE
  202. #define CONFIG_SYS_PCI2_MEM_SIZE 0x10000000 /* 256M */
  203. #define CONFIG_SYS_PCI2_MMIO_BASE 0xB0000000
  204. #define CONFIG_SYS_PCI2_MMIO_PHYS CONFIG_SYS_PCI2_MMIO_BASE
  205. #define CONFIG_SYS_PCI2_MMIO_SIZE 0x10000000 /* 256M */
  206. #define CONFIG_SYS_PCI2_IO_BASE 0x00000000
  207. #define CONFIG_SYS_PCI2_IO_PHYS 0xE2100000
  208. #define CONFIG_SYS_PCI2_IO_SIZE 0x00100000 /* 1M */
  209. #if defined(CONFIG_PCI)
  210. #define PCI_64BIT
  211. #define PCI_ONE_PCI1
  212. #if defined(PCI_64BIT)
  213. #undef PCI_ALL_PCI1
  214. #undef PCI_TWO_PCI1
  215. #undef PCI_ONE_PCI1
  216. #endif
  217. #undef CONFIG_EEPRO100
  218. #undef CONFIG_TULIP
  219. #if !defined(CONFIG_PCI_PNP)
  220. #define PCI_ENET0_IOADDR 0xFIXME
  221. #define PCI_ENET0_MEMADDR 0xFIXME
  222. #define PCI_IDSEL_NUMBER 0xFIXME
  223. #endif
  224. #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
  225. #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */
  226. #endif /* CONFIG_PCI */
  227. /*
  228. * TSEC configuration
  229. */
  230. #if defined(CONFIG_TSEC_ENET)
  231. #define CONFIG_GMII /* MII PHY management */
  232. #define CONFIG_TSEC1
  233. #define CONFIG_TSEC1_NAME "TSEC0"
  234. #define CONFIG_TSEC2
  235. #define CONFIG_TSEC2_NAME "TSEC1"
  236. #define CONFIG_PHY_M88E1111
  237. #define TSEC1_PHY_ADDR 0x08
  238. #define TSEC2_PHY_ADDR 0x10
  239. #define TSEC1_PHYIDX 0
  240. #define TSEC2_PHYIDX 0
  241. #define TSEC1_FLAGS TSEC_GIGABIT
  242. #define TSEC2_FLAGS TSEC_GIGABIT
  243. /* Options are: TSEC[0-1] */
  244. #define CONFIG_ETHPRIME "TSEC0"
  245. #endif /* CONFIG_TSEC_ENET */
  246. /*
  247. * Environment
  248. */
  249. #ifndef CONFIG_SYS_RAMBOOT
  250. #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0xc0000)
  251. #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */
  252. #define CONFIG_ENV_SIZE 0x2000
  253. /* Address and size of Redundant Environment Sector */
  254. #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
  255. #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
  256. #else
  257. #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
  258. #define CONFIG_ENV_SIZE 0x2000
  259. #endif
  260. #define CONFIG_LOADS_ECHO /* echo on for serial download */
  261. #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
  262. /*
  263. * BOOTP options
  264. */
  265. #define CONFIG_BOOTP_BOOTFILESIZE
  266. /*
  267. * Command line configuration.
  268. */
  269. #define CONFIG_SYS_RTC_BUS_NUM 0x01
  270. #define CONFIG_SYS_I2C_RTC_ADDR 0x32
  271. #define CONFIG_RTC_RX8025
  272. /* Pass Ethernet MAC to VxWorks */
  273. #define CONFIG_SYS_VXWORKS_MAC_PTR 0x000043f0
  274. #undef CONFIG_WATCHDOG /* watchdog disabled */
  275. /*
  276. * Miscellaneous configurable options
  277. */
  278. #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
  279. /*
  280. * For booting Linux, the board info and command line data
  281. * have to be in the first 256 MB of memory, since this is
  282. * the maximum mapped by the Linux kernel during initialization.
  283. */
  284. #define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Init Memory map for Linux*/
  285. #define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST */
  286. #define CONFIG_SYS_HRCW_LOW (\
  287. HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
  288. HRCWL_DDR_TO_SCB_CLK_1X1 |\
  289. HRCWL_CSB_TO_CLKIN |\
  290. HRCWL_VCO_1X2 |\
  291. HRCWL_CORE_TO_CSB_2X1)
  292. #if defined(PCI_64BIT)
  293. #define CONFIG_SYS_HRCW_HIGH (\
  294. HRCWH_PCI_HOST |\
  295. HRCWH_64_BIT_PCI |\
  296. HRCWH_PCI1_ARBITER_ENABLE |\
  297. HRCWH_PCI2_ARBITER_DISABLE |\
  298. HRCWH_CORE_ENABLE |\
  299. HRCWH_FROM_0X00000100 |\
  300. HRCWH_BOOTSEQ_DISABLE |\
  301. HRCWH_SW_WATCHDOG_DISABLE |\
  302. HRCWH_ROM_LOC_LOCAL_16BIT |\
  303. HRCWH_TSEC1M_IN_GMII |\
  304. HRCWH_TSEC2M_IN_GMII)
  305. #else
  306. #define CONFIG_SYS_HRCW_HIGH (\
  307. HRCWH_PCI_HOST |\
  308. HRCWH_32_BIT_PCI |\
  309. HRCWH_PCI1_ARBITER_ENABLE |\
  310. HRCWH_PCI2_ARBITER_ENABLE |\
  311. HRCWH_CORE_ENABLE |\
  312. HRCWH_FROM_0X00000100 |\
  313. HRCWH_BOOTSEQ_DISABLE |\
  314. HRCWH_SW_WATCHDOG_DISABLE |\
  315. HRCWH_ROM_LOC_LOCAL_16BIT |\
  316. HRCWH_TSEC1M_IN_GMII |\
  317. HRCWH_TSEC2M_IN_GMII)
  318. #endif
  319. /* System IO Config */
  320. #define CONFIG_SYS_SICRH 0
  321. #define CONFIG_SYS_SICRL SICRL_LDP_A
  322. #define CONFIG_SYS_HID0_INIT 0x000000000
  323. #define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \
  324. HID0_ENABLE_INSTRUCTION_CACHE)
  325. #define CONFIG_SYS_HID2 HID2_HBE
  326. #define CONFIG_SYS_GPIO1_PRELIM
  327. #define CONFIG_SYS_GPIO1_DIR 0x00100000
  328. #define CONFIG_SYS_GPIO1_DAT 0x00100000
  329. #define CONFIG_SYS_GPIO2_PRELIM
  330. #define CONFIG_SYS_GPIO2_DIR 0x78900000
  331. #define CONFIG_SYS_GPIO2_DAT 0x70100000
  332. #define CONFIG_HIGH_BATS /* High BATs supported */
  333. /* DDR @ 0x00000000 */
  334. #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | \
  335. BATL_MEMCOHERENCE)
  336. #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | \
  337. BATU_VS | BATU_VP)
  338. /* PCI @ 0x80000000 */
  339. #ifdef CONFIG_PCI
  340. #define CONFIG_PCI_INDIRECT_BRIDGE
  341. #define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_BASE | BATL_PP_RW | \
  342. BATL_MEMCOHERENCE)
  343. #define CONFIG_SYS_IBAT1U (CONFIG_SYS_PCI1_MEM_BASE | BATU_BL_256M | \
  344. BATU_VS | BATU_VP)
  345. #define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MMIO_BASE | BATL_PP_RW | \
  346. BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
  347. #define CONFIG_SYS_IBAT2U (CONFIG_SYS_PCI1_MMIO_BASE | BATU_BL_256M | \
  348. BATU_VS | BATU_VP)
  349. #else
  350. #define CONFIG_SYS_IBAT1L (0)
  351. #define CONFIG_SYS_IBAT1U (0)
  352. #define CONFIG_SYS_IBAT2L (0)
  353. #define CONFIG_SYS_IBAT2U (0)
  354. #endif
  355. #ifdef CONFIG_MPC83XX_PCI2
  356. #define CONFIG_SYS_IBAT3L (CONFIG_SYS_PCI2_MEM_BASE | BATL_PP_RW | \
  357. BATL_MEMCOHERENCE)
  358. #define CONFIG_SYS_IBAT3U (CONFIG_SYS_PCI2_MEM_BASE | BATU_BL_256M | \
  359. BATU_VS | BATU_VP)
  360. #define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCI2_MMIO_BASE | BATL_PP_RW | \
  361. BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
  362. #define CONFIG_SYS_IBAT4U (CONFIG_SYS_PCI2_MMIO_BASE | BATU_BL_256M | \
  363. BATU_VS | BATU_VP)
  364. #else
  365. #define CONFIG_SYS_IBAT3L (0)
  366. #define CONFIG_SYS_IBAT3U (0)
  367. #define CONFIG_SYS_IBAT4L (0)
  368. #define CONFIG_SYS_IBAT4U (0)
  369. #endif
  370. /* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 */
  371. #define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR | BATL_PP_RW | \
  372. BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
  373. #define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR | BATU_BL_256M | \
  374. BATU_VS | BATU_VP)
  375. #define CONFIG_SYS_IBAT6L (0xF0000000 | BATL_PP_RW | BATL_MEMCOHERENCE)
  376. #define CONFIG_SYS_IBAT6U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
  377. #if (CONFIG_SYS_DDR_SIZE == 512)
  378. #define CONFIG_SYS_IBAT7L (CONFIG_SYS_SDRAM_BASE+0x10000000 | \
  379. BATL_PP_RW | BATL_MEMCOHERENCE)
  380. #define CONFIG_SYS_IBAT7U (CONFIG_SYS_SDRAM_BASE+0x10000000 | \
  381. BATU_BL_256M | BATU_VS | BATU_VP)
  382. #else
  383. #define CONFIG_SYS_IBAT7L (0)
  384. #define CONFIG_SYS_IBAT7U (0)
  385. #endif
  386. #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
  387. #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
  388. #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
  389. #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
  390. #define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L
  391. #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
  392. #define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
  393. #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
  394. #define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L
  395. #define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U
  396. #define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L
  397. #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
  398. #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
  399. #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
  400. #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
  401. #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
  402. #if defined(CONFIG_CMD_KGDB)
  403. #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
  404. #endif
  405. /*
  406. * Environment Configuration
  407. */
  408. #define CONFIG_ENV_OVERWRITE
  409. #if defined(CONFIG_TSEC_ENET)
  410. #define CONFIG_HAS_ETH0
  411. #define CONFIG_HAS_ETH1
  412. #endif
  413. #define CONFIG_HOSTNAME "VME8349"
  414. #define CONFIG_ROOTPATH "/tftpboot/rootfs"
  415. #define CONFIG_BOOTFILE "uImage"
  416. #define CONFIG_LOADADDR 800000 /* def location for tftp and bootm */
  417. #define CONFIG_EXTRA_ENV_SETTINGS \
  418. "netdev=eth0\0" \
  419. "hostname=vme8349\0" \
  420. "nfsargs=setenv bootargs root=/dev/nfs rw " \
  421. "nfsroot=${serverip}:${rootpath}\0" \
  422. "ramargs=setenv bootargs root=/dev/ram rw\0" \
  423. "addip=setenv bootargs ${bootargs} " \
  424. "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
  425. ":${hostname}:${netdev}:off panic=1\0" \
  426. "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
  427. "flash_nfs=run nfsargs addip addtty;" \
  428. "bootm ${kernel_addr}\0" \
  429. "flash_self=run ramargs addip addtty;" \
  430. "bootm ${kernel_addr} ${ramdisk_addr}\0" \
  431. "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \
  432. "bootm\0" \
  433. "load=tftp 100000 /tftpboot/bdi2000/vme8349.bin\0" \
  434. "update=protect off fff00000 fff3ffff; " \
  435. "era fff00000 fff3ffff; cp.b 100000 fff00000 ${filesize}\0" \
  436. "upd=run load update\0" \
  437. "fdtaddr=780000\0" \
  438. "fdtfile=vme8349.dtb\0" \
  439. ""
  440. #define CONFIG_NFSBOOTCOMMAND \
  441. "setenv bootargs root=/dev/nfs rw " \
  442. "nfsroot=$serverip:$rootpath " \
  443. "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:" \
  444. "$netdev:off " \
  445. "console=$consoledev,$baudrate $othbootargs;" \
  446. "tftp $loadaddr $bootfile;" \
  447. "tftp $fdtaddr $fdtfile;" \
  448. "bootm $loadaddr - $fdtaddr"
  449. #define CONFIG_RAMBOOTCOMMAND \
  450. "setenv bootargs root=/dev/ram rw " \
  451. "console=$consoledev,$baudrate $othbootargs;" \
  452. "tftp $ramdiskaddr $ramdiskfile;" \
  453. "tftp $loadaddr $bootfile;" \
  454. "tftp $fdtaddr $fdtfile;" \
  455. "bootm $loadaddr $ramdiskaddr $fdtaddr"
  456. #define CONFIG_BOOTCOMMAND "run flash_self"
  457. #ifndef __ASSEMBLY__
  458. int vme8349_read_spd(unsigned char chip, unsigned int addr, int alen,
  459. unsigned char *buffer, int len);
  460. #endif
  461. #endif /* __CONFIG_H */