sbc8349.h 19 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * WindRiver SBC8349 U-Boot configuration file.
  4. * Copyright (c) 2006, 2007 Wind River Systems, Inc.
  5. *
  6. * Paul Gortmaker <paul.gortmaker@windriver.com>
  7. * Based on the MPC8349EMDS config.
  8. */
  9. /*
  10. * sbc8349 board configuration file.
  11. */
  12. #ifndef __CONFIG_H
  13. #define __CONFIG_H
  14. /*
  15. * High Level Configuration Options
  16. */
  17. #define CONFIG_E300 1 /* E300 Family */
  18. /* Don't enable PCI2 on sbc834x - it doesn't exist physically. */
  19. #undef CONFIG_MPC83XX_PCI2 /* support for 2nd PCI controller */
  20. /*
  21. * The default if PCI isn't enabled, or if no PCI clk setting is given
  22. * is 66MHz; this is what the board defaults to when the PCI slot is
  23. * physically empty. The board will automatically (i.e w/o jumpers)
  24. * clock down to 33MHz if you insert a 33MHz PCI card.
  25. */
  26. #ifdef CONFIG_PCI_33M
  27. #define CONFIG_83XX_CLKIN 33000000 /* in Hz */
  28. #else /* 66M */
  29. #define CONFIG_83XX_CLKIN 66000000 /* in Hz */
  30. #endif
  31. #ifndef CONFIG_SYS_CLK_FREQ
  32. #ifdef CONFIG_PCI_33M
  33. #define CONFIG_SYS_CLK_FREQ 33000000
  34. #define HRCWL_CSB_TO_CLKIN HRCWL_CSB_TO_CLKIN_8X1
  35. #else /* 66M */
  36. #define CONFIG_SYS_CLK_FREQ 66000000
  37. #define HRCWL_CSB_TO_CLKIN HRCWL_CSB_TO_CLKIN_4X1
  38. #endif
  39. #endif
  40. #define CONFIG_SYS_IMMR 0xE0000000
  41. #undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */
  42. #define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest region */
  43. #define CONFIG_SYS_MEMTEST_END 0x00100000
  44. /*
  45. * DDR Setup
  46. */
  47. #undef CONFIG_DDR_ECC /* only for ECC DDR module */
  48. #undef CONFIG_DDR_ECC_CMD /* use DDR ECC user commands */
  49. #define CONFIG_SPD_EEPROM /* use SPD EEPROM for DDR setup*/
  50. #define CONFIG_SYS_83XX_DDR_USES_CS0 /* WRS; Fsl board uses CS2/CS3 */
  51. /*
  52. * 32-bit data path mode.
  53. *
  54. * Please note that using this mode for devices with the real density of 64-bit
  55. * effectively reduces the amount of available memory due to the effect of
  56. * wrapping around while translating address to row/columns, for example in the
  57. * 256MB module the upper 128MB get aliased with contents of the lower
  58. * 128MB); normally this define should be used for devices with real 32-bit
  59. * data path.
  60. */
  61. #undef CONFIG_DDR_32BIT
  62. #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory*/
  63. #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
  64. #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
  65. #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \
  66. DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075)
  67. #define CONFIG_DDR_2T_TIMING
  68. #if defined(CONFIG_SPD_EEPROM)
  69. /*
  70. * Determine DDR configuration from I2C interface.
  71. */
  72. #define SPD_EEPROM_ADDRESS 0x52 /* DDR DIMM */
  73. #else
  74. /*
  75. * Manually set up DDR parameters
  76. * NB: manual DDR setup untested on sbc834x
  77. */
  78. #define CONFIG_SYS_DDR_SIZE 256 /* MB */
  79. #define CONFIG_SYS_DDR_CS2_CONFIG (CSCONFIG_EN \
  80. | CSCONFIG_ROW_BIT_13 \
  81. | CSCONFIG_COL_BIT_10)
  82. #define CONFIG_SYS_DDR_TIMING_1 0x36332321
  83. #define CONFIG_SYS_DDR_TIMING_2 0x00000800 /* P9-45,may need tuning */
  84. #define CONFIG_SYS_DDR_CONTROL 0xc2000000 /* unbuffered,no DYN_PWR */
  85. #define CONFIG_SYS_DDR_INTERVAL 0x04060100 /* autocharge,no open page */
  86. #if defined(CONFIG_DDR_32BIT)
  87. /* set burst length to 8 for 32-bit data path */
  88. /* DLL,normal,seq,4/2.5, 8 burst len */
  89. #define CONFIG_SYS_DDR_MODE 0x00000023
  90. #else
  91. /* the default burst length is 4 - for 64-bit data path */
  92. /* DLL,normal,seq,4/2.5, 4 burst len */
  93. #define CONFIG_SYS_DDR_MODE 0x00000022
  94. #endif
  95. #endif
  96. /*
  97. * SDRAM on the Local Bus
  98. */
  99. #define CONFIG_SYS_LBC_SDRAM_BASE 0xF0000000 /* Localbus SDRAM */
  100. #define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */
  101. /*
  102. * FLASH on the Local Bus
  103. */
  104. #define CONFIG_SYS_FLASH_BASE 0xFF800000 /* start of FLASH */
  105. #define CONFIG_SYS_FLASH_SIZE 8 /* flash size in MB */
  106. #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \
  107. | BR_PS_16 /* 16 bit port */ \
  108. | BR_MS_GPCM /* MSEL = GPCM */ \
  109. | BR_V) /* valid */
  110. #define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
  111. | OR_GPCM_XAM \
  112. | OR_GPCM_CSNT \
  113. | OR_GPCM_ACS_DIV2 \
  114. | OR_GPCM_XACS \
  115. | OR_GPCM_SCY_15 \
  116. | OR_GPCM_TRLX_SET \
  117. | OR_GPCM_EHTR_SET \
  118. | OR_GPCM_EAD)
  119. /* 0xFF806FF7 */
  120. /* window base at flash base */
  121. #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
  122. #define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_8MB)
  123. #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
  124. #define CONFIG_SYS_MAX_FLASH_SECT 64 /* sectors per device */
  125. #undef CONFIG_SYS_FLASH_CHECKSUM
  126. #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
  127. #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
  128. #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
  129. #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
  130. #define CONFIG_SYS_RAMBOOT
  131. #else
  132. #undef CONFIG_SYS_RAMBOOT
  133. #endif
  134. #define CONFIG_SYS_INIT_RAM_LOCK 1
  135. /* Initial RAM address */
  136. #define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000
  137. /* Size of used area in RAM*/
  138. #define CONFIG_SYS_INIT_RAM_SIZE 0x1000
  139. #define CONFIG_SYS_GBL_DATA_OFFSET \
  140. (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
  141. #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
  142. #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
  143. #define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Reserved for malloc */
  144. /*
  145. * Local Bus LCRR and LBCR regs
  146. * LCRR: DLL bypass, Clock divider is 4
  147. * External Local Bus rate is
  148. * CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV
  149. */
  150. #define CONFIG_SYS_LCRR_DBYP LCRR_DBYP
  151. #define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4
  152. #define CONFIG_SYS_LBC_LBCR 0x00000000
  153. #undef CONFIG_SYS_LB_SDRAM /* if board has SDRAM on local bus */
  154. #ifdef CONFIG_SYS_LB_SDRAM
  155. /* Local bus BR2, OR2 definition for SDRAM if soldered on the board*/
  156. /*
  157. * Base Register 2 and Option Register 2 configure SDRAM.
  158. * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000.
  159. *
  160. * For BR2, need:
  161. * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0
  162. * port-size = 32-bits = BR2[19:20] = 11
  163. * no parity checking = BR2[21:22] = 00
  164. * SDRAM for MSEL = BR2[24:26] = 011
  165. * Valid = BR[31] = 1
  166. *
  167. * 0 4 8 12 16 20 24 28
  168. * 1111 0000 0000 0000 0001 1000 0110 0001 = F0001861
  169. */
  170. #define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_LBC_SDRAM_BASE \
  171. | BR_PS_32 \
  172. | BR_MS_SDRAM \
  173. | BR_V)
  174. /* 0xF0001861 */
  175. #define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_LBC_SDRAM_BASE
  176. #define CONFIG_SYS_LBLAWAR2_PRELIM (LBLAWAR_EN | LBLAWAR_64MB)
  177. /*
  178. * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64.
  179. *
  180. * For OR2, need:
  181. * 64MB mask for AM, OR2[0:7] = 1111 1100
  182. * XAM, OR2[17:18] = 11
  183. * 9 columns OR2[19-21] = 010
  184. * 13 rows OR2[23-25] = 100
  185. * EAD set for extra time OR[31] = 1
  186. *
  187. * 0 4 8 12 16 20 24 28
  188. * 1111 1100 0000 0000 0110 1001 0000 0001 = FC006901
  189. */
  190. #define CONFIG_SYS_OR2_PRELIM (MEG_TO_AM(CONFIG_SYS_LBC_SDRAM_SIZE) \
  191. | OR_SDRAM_XAM \
  192. | ((9 - OR_SDRAM_MIN_COLS) << OR_SDRAM_COLS_SHIFT) \
  193. | ((13 - OR_SDRAM_MIN_ROWS) << OR_SDRAM_ROWS_SHIFT) \
  194. | OR_SDRAM_EAD)
  195. /* 0xFC006901 */
  196. /* LB sdram refresh timer, about 6us */
  197. #define CONFIG_SYS_LBC_LSRT 0x32000000
  198. /* LB refresh timer prescal, 266MHz/32 */
  199. #define CONFIG_SYS_LBC_MRTPR 0x20000000
  200. #define CONFIG_SYS_LBC_LSDMR_COMMON (LSDMR_RFEN \
  201. | LSDMR_BSMA1516 \
  202. | LSDMR_RFCR8 \
  203. | LSDMR_PRETOACT6 \
  204. | LSDMR_ACTTORW3 \
  205. | LSDMR_BL8 \
  206. | LSDMR_WRC3 \
  207. | LSDMR_CL3)
  208. /*
  209. * SDRAM Controller configuration sequence.
  210. */
  211. #define CONFIG_SYS_LBC_LSDMR_1 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_PCHALL)
  212. #define CONFIG_SYS_LBC_LSDMR_2 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH)
  213. #define CONFIG_SYS_LBC_LSDMR_3 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH)
  214. #define CONFIG_SYS_LBC_LSDMR_4 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_MRW)
  215. #define CONFIG_SYS_LBC_LSDMR_5 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_NORMAL)
  216. #endif
  217. /*
  218. * Serial Port
  219. */
  220. #define CONFIG_SYS_NS16550_SERIAL
  221. #define CONFIG_SYS_NS16550_REG_SIZE 1
  222. #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
  223. #define CONFIG_SYS_BAUDRATE_TABLE \
  224. {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
  225. #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
  226. #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
  227. /* I2C */
  228. #define CONFIG_SYS_I2C
  229. #define CONFIG_SYS_I2C_FSL
  230. #define CONFIG_SYS_FSL_I2C_SPEED 400000
  231. #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
  232. #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
  233. #define CONFIG_SYS_FSL_I2C2_SPEED 400000
  234. #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
  235. #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
  236. #define CONFIG_SYS_I2C_NOPROBES { {0, 0x69}, {1, 0x69} }
  237. /* could also use CONFIG_I2C_MULTI_BUS and CONFIG_SYS_SPD_BUS_NUM... */
  238. /* TSEC */
  239. #define CONFIG_SYS_TSEC1_OFFSET 0x24000
  240. #define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET)
  241. #define CONFIG_SYS_TSEC2_OFFSET 0x25000
  242. #define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET)
  243. /*
  244. * General PCI
  245. * Addresses are mapped 1-1.
  246. */
  247. #define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
  248. #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
  249. #define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */
  250. #define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000
  251. #define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE
  252. #define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */
  253. #define CONFIG_SYS_PCI1_IO_BASE 0x00000000
  254. #define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000
  255. #define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */
  256. #define CONFIG_SYS_PCI2_MEM_BASE 0xA0000000
  257. #define CONFIG_SYS_PCI2_MEM_PHYS CONFIG_SYS_PCI2_MEM_BASE
  258. #define CONFIG_SYS_PCI2_MEM_SIZE 0x10000000 /* 256M */
  259. #define CONFIG_SYS_PCI2_MMIO_BASE 0xB0000000
  260. #define CONFIG_SYS_PCI2_MMIO_PHYS CONFIG_SYS_PCI2_MMIO_BASE
  261. #define CONFIG_SYS_PCI2_MMIO_SIZE 0x10000000 /* 256M */
  262. #define CONFIG_SYS_PCI2_IO_BASE 0x00000000
  263. #define CONFIG_SYS_PCI2_IO_PHYS 0xE2100000
  264. #define CONFIG_SYS_PCI2_IO_SIZE 0x00100000 /* 1M */
  265. #if defined(CONFIG_PCI)
  266. #define PCI_64BIT
  267. #define PCI_ONE_PCI1
  268. #if defined(PCI_64BIT)
  269. #undef PCI_ALL_PCI1
  270. #undef PCI_TWO_PCI1
  271. #undef PCI_ONE_PCI1
  272. #endif
  273. #undef CONFIG_EEPRO100
  274. #undef CONFIG_TULIP
  275. #if !defined(CONFIG_PCI_PNP)
  276. #define PCI_ENET0_IOADDR 0xFIXME
  277. #define PCI_ENET0_MEMADDR 0xFIXME
  278. #define PCI_IDSEL_NUMBER 0xFIXME
  279. #endif
  280. #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
  281. #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */
  282. #endif /* CONFIG_PCI */
  283. /*
  284. * TSEC configuration
  285. */
  286. #if defined(CONFIG_TSEC_ENET)
  287. #define CONFIG_TSEC1 1
  288. #define CONFIG_TSEC1_NAME "TSEC0"
  289. #define CONFIG_TSEC2 1
  290. #define CONFIG_TSEC2_NAME "TSEC1"
  291. #define CONFIG_PHY_BCM5421S 1
  292. #define TSEC1_PHY_ADDR 0x19
  293. #define TSEC2_PHY_ADDR 0x1a
  294. #define TSEC1_PHYIDX 0
  295. #define TSEC2_PHYIDX 0
  296. #define TSEC1_FLAGS TSEC_GIGABIT
  297. #define TSEC2_FLAGS TSEC_GIGABIT
  298. /* Options are: TSEC[0-1] */
  299. #define CONFIG_ETHPRIME "TSEC0"
  300. #endif /* CONFIG_TSEC_ENET */
  301. /*
  302. * Environment
  303. */
  304. #ifndef CONFIG_SYS_RAMBOOT
  305. #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x40000)
  306. #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */
  307. #define CONFIG_ENV_SIZE 0x2000
  308. /* Address and size of Redundant Environment Sector */
  309. #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
  310. #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
  311. #else
  312. #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
  313. #define CONFIG_ENV_SIZE 0x2000
  314. #endif
  315. #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
  316. #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
  317. /*
  318. * BOOTP options
  319. */
  320. #define CONFIG_BOOTP_BOOTFILESIZE
  321. /*
  322. * Command line configuration.
  323. */
  324. #undef CONFIG_WATCHDOG /* watchdog disabled */
  325. /*
  326. * Miscellaneous configurable options
  327. */
  328. #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
  329. /*
  330. * For booting Linux, the board info and command line data
  331. * have to be in the first 256 MB of memory, since this is
  332. * the maximum mapped by the Linux kernel during initialization.
  333. */
  334. /* Initial Memory map for Linux*/
  335. #define CONFIG_SYS_BOOTMAPSZ (256 << 20)
  336. #define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST */
  337. #if 1 /*528/264*/
  338. #define CONFIG_SYS_HRCW_LOW (\
  339. HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
  340. HRCWL_DDR_TO_SCB_CLK_1X1 |\
  341. HRCWL_CSB_TO_CLKIN |\
  342. HRCWL_VCO_1X2 |\
  343. HRCWL_CORE_TO_CSB_2X1)
  344. #elif 0 /*396/132*/
  345. #define CONFIG_SYS_HRCW_LOW (\
  346. HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
  347. HRCWL_DDR_TO_SCB_CLK_1X1 |\
  348. HRCWL_CSB_TO_CLKIN |\
  349. HRCWL_VCO_1X4 |\
  350. HRCWL_CORE_TO_CSB_3X1)
  351. #elif 0 /*264/132*/
  352. #define CONFIG_SYS_HRCW_LOW (\
  353. HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
  354. HRCWL_DDR_TO_SCB_CLK_1X1 |\
  355. HRCWL_CSB_TO_CLKIN |\
  356. HRCWL_VCO_1X4 |\
  357. HRCWL_CORE_TO_CSB_2X1)
  358. #elif 0 /*132/132*/
  359. #define CONFIG_SYS_HRCW_LOW (\
  360. HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
  361. HRCWL_DDR_TO_SCB_CLK_1X1 |\
  362. HRCWL_CSB_TO_CLKIN |\
  363. HRCWL_VCO_1X4 |\
  364. HRCWL_CORE_TO_CSB_1X1)
  365. #elif 0 /*264/264 */
  366. #define CONFIG_SYS_HRCW_LOW (\
  367. HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
  368. HRCWL_DDR_TO_SCB_CLK_1X1 |\
  369. HRCWL_CSB_TO_CLKIN |\
  370. HRCWL_VCO_1X4 |\
  371. HRCWL_CORE_TO_CSB_1X1)
  372. #endif
  373. #if defined(PCI_64BIT)
  374. #define CONFIG_SYS_HRCW_HIGH (\
  375. HRCWH_PCI_HOST |\
  376. HRCWH_64_BIT_PCI |\
  377. HRCWH_PCI1_ARBITER_ENABLE |\
  378. HRCWH_PCI2_ARBITER_DISABLE |\
  379. HRCWH_CORE_ENABLE |\
  380. HRCWH_FROM_0X00000100 |\
  381. HRCWH_BOOTSEQ_DISABLE |\
  382. HRCWH_SW_WATCHDOG_DISABLE |\
  383. HRCWH_ROM_LOC_LOCAL_16BIT |\
  384. HRCWH_TSEC1M_IN_GMII |\
  385. HRCWH_TSEC2M_IN_GMII)
  386. #else
  387. #define CONFIG_SYS_HRCW_HIGH (\
  388. HRCWH_PCI_HOST |\
  389. HRCWH_32_BIT_PCI |\
  390. HRCWH_PCI1_ARBITER_ENABLE |\
  391. HRCWH_PCI2_ARBITER_ENABLE |\
  392. HRCWH_CORE_ENABLE |\
  393. HRCWH_FROM_0X00000100 |\
  394. HRCWH_BOOTSEQ_DISABLE |\
  395. HRCWH_SW_WATCHDOG_DISABLE |\
  396. HRCWH_ROM_LOC_LOCAL_16BIT |\
  397. HRCWH_TSEC1M_IN_GMII |\
  398. HRCWH_TSEC2M_IN_GMII)
  399. #endif
  400. /* System IO Config */
  401. #define CONFIG_SYS_SICRH 0
  402. #define CONFIG_SYS_SICRL SICRL_LDP_A
  403. #define CONFIG_SYS_HID0_INIT 0x000000000
  404. #define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK \
  405. | HID0_ENABLE_INSTRUCTION_CACHE)
  406. /* #define CONFIG_SYS_HID0_FINAL (\
  407. HID0_ENABLE_INSTRUCTION_CACHE |\
  408. HID0_ENABLE_M_BIT |\
  409. HID0_ENABLE_ADDRESS_BROADCAST) */
  410. #define CONFIG_SYS_HID2 HID2_HBE
  411. #define CONFIG_HIGH_BATS 1 /* High BATs supported */
  412. /* DDR @ 0x00000000 */
  413. #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE \
  414. | BATL_PP_RW \
  415. | BATL_MEMCOHERENCE)
  416. #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \
  417. | BATU_BL_256M \
  418. | BATU_VS \
  419. | BATU_VP)
  420. /* PCI @ 0x80000000 */
  421. #ifdef CONFIG_PCI
  422. #define CONFIG_PCI_INDIRECT_BRIDGE
  423. #define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_BASE \
  424. | BATL_PP_RW \
  425. | BATL_MEMCOHERENCE)
  426. #define CONFIG_SYS_IBAT1U (CONFIG_SYS_PCI1_MEM_BASE \
  427. | BATU_BL_256M \
  428. | BATU_VS \
  429. | BATU_VP)
  430. #define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MMIO_BASE \
  431. | BATL_PP_RW \
  432. | BATL_CACHEINHIBIT \
  433. | BATL_GUARDEDSTORAGE)
  434. #define CONFIG_SYS_IBAT2U (CONFIG_SYS_PCI1_MMIO_BASE \
  435. | BATU_BL_256M \
  436. | BATU_VS \
  437. | BATU_VP)
  438. #else
  439. #define CONFIG_SYS_IBAT1L (0)
  440. #define CONFIG_SYS_IBAT1U (0)
  441. #define CONFIG_SYS_IBAT2L (0)
  442. #define CONFIG_SYS_IBAT2U (0)
  443. #endif
  444. #ifdef CONFIG_MPC83XX_PCI2
  445. #define CONFIG_SYS_IBAT3L (CONFIG_SYS_PCI2_MEM_BASE \
  446. | BATL_PP_RW \
  447. | BATL_MEMCOHERENCE)
  448. #define CONFIG_SYS_IBAT3U (CONFIG_SYS_PCI2_MEM_BASE \
  449. | BATU_BL_256M \
  450. | BATU_VS \
  451. | BATU_VP)
  452. #define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCI2_MMIO_BASE \
  453. | BATL_PP_RW \
  454. | BATL_CACHEINHIBIT \
  455. | BATL_GUARDEDSTORAGE)
  456. #define CONFIG_SYS_IBAT4U (CONFIG_SYS_PCI2_MMIO_BASE \
  457. | BATU_BL_256M \
  458. | BATU_VS \
  459. | BATU_VP)
  460. #else
  461. #define CONFIG_SYS_IBAT3L (0)
  462. #define CONFIG_SYS_IBAT3U (0)
  463. #define CONFIG_SYS_IBAT4L (0)
  464. #define CONFIG_SYS_IBAT4U (0)
  465. #endif
  466. /* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 */
  467. #define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR \
  468. | BATL_PP_RW \
  469. | BATL_CACHEINHIBIT \
  470. | BATL_GUARDEDSTORAGE)
  471. #define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR \
  472. | BATU_BL_256M \
  473. | BATU_VS \
  474. | BATU_VP)
  475. /* LBC SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */
  476. #define CONFIG_SYS_IBAT6L (CONFIG_SYS_LBC_SDRAM_BASE \
  477. | BATL_PP_RW \
  478. | BATL_MEMCOHERENCE \
  479. | BATL_GUARDEDSTORAGE)
  480. #define CONFIG_SYS_IBAT6U (CONFIG_SYS_LBC_SDRAM_BASE \
  481. | BATU_BL_256M \
  482. | BATU_VS \
  483. | BATU_VP)
  484. #define CONFIG_SYS_IBAT7L (0)
  485. #define CONFIG_SYS_IBAT7U (0)
  486. #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
  487. #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
  488. #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
  489. #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
  490. #define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L
  491. #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
  492. #define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
  493. #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
  494. #define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L
  495. #define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U
  496. #define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L
  497. #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
  498. #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
  499. #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
  500. #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
  501. #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
  502. #if defined(CONFIG_CMD_KGDB)
  503. #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
  504. #endif
  505. /*
  506. * Environment Configuration
  507. */
  508. #define CONFIG_ENV_OVERWRITE
  509. #if defined(CONFIG_TSEC_ENET)
  510. #define CONFIG_HAS_ETH0
  511. #define CONFIG_HAS_ETH1
  512. #endif
  513. #define CONFIG_HOSTNAME "SBC8349"
  514. #define CONFIG_ROOTPATH "/tftpboot/rootfs"
  515. #define CONFIG_BOOTFILE "uImage"
  516. /* default location for tftp and bootm */
  517. #define CONFIG_LOADADDR 800000
  518. #define CONFIG_EXTRA_ENV_SETTINGS \
  519. "netdev=eth0\0" \
  520. "hostname=sbc8349\0" \
  521. "nfsargs=setenv bootargs root=/dev/nfs rw " \
  522. "nfsroot=${serverip}:${rootpath}\0" \
  523. "ramargs=setenv bootargs root=/dev/ram rw\0" \
  524. "addip=setenv bootargs ${bootargs} " \
  525. "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
  526. ":${hostname}:${netdev}:off panic=1\0" \
  527. "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
  528. "flash_nfs=run nfsargs addip addtty;" \
  529. "bootm ${kernel_addr}\0" \
  530. "flash_self=run ramargs addip addtty;" \
  531. "bootm ${kernel_addr} ${ramdisk_addr}\0" \
  532. "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \
  533. "bootm\0" \
  534. "load=tftp 100000 /tftpboot/sbc8349/u-boot.bin\0" \
  535. "update=protect off ff800000 ff83ffff; " \
  536. "era ff800000 ff83ffff; cp.b 100000 ff800000 ${filesize}\0" \
  537. "upd=run load update\0" \
  538. "fdtaddr=780000\0" \
  539. "fdtfile=sbc8349.dtb\0" \
  540. ""
  541. #define CONFIG_NFSBOOTCOMMAND \
  542. "setenv bootargs root=/dev/nfs rw " \
  543. "nfsroot=$serverip:$rootpath " \
  544. "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:" \
  545. "$netdev:off " \
  546. "console=$consoledev,$baudrate $othbootargs;" \
  547. "tftp $loadaddr $bootfile;" \
  548. "tftp $fdtaddr $fdtfile;" \
  549. "bootm $loadaddr - $fdtaddr"
  550. #define CONFIG_RAMBOOTCOMMAND \
  551. "setenv bootargs root=/dev/ram rw " \
  552. "console=$consoledev,$baudrate $othbootargs;" \
  553. "tftp $ramdiskaddr $ramdiskfile;" \
  554. "tftp $loadaddr $bootfile;" \
  555. "tftp $fdtaddr $fdtfile;" \
  556. "bootm $loadaddr $ramdiskaddr $fdtaddr"
  557. #define CONFIG_BOOTCOMMAND "run flash_self"
  558. #endif /* __CONFIG_H */