TQM834x.h 14 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * (C) Copyright 2005
  4. * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  5. */
  6. /*
  7. * TQM8349 board configuration file
  8. */
  9. #ifndef __CONFIG_H
  10. #define __CONFIG_H
  11. /*
  12. * High Level Configuration Options
  13. */
  14. #define CONFIG_E300 1 /* E300 Family */
  15. /* IMMR Base Address Register, use Freescale default: 0xff400000 */
  16. #define CONFIG_SYS_IMMR 0xff400000
  17. /* System clock. Primary input clock when in PCI host mode */
  18. #define CONFIG_83XX_CLKIN 66666000 /* 66,666 MHz */
  19. /*
  20. * Local Bus LCRR
  21. * LCRR: DLL bypass, Clock divider is 8
  22. *
  23. * for CSB = 266 MHz it gives LCB clock frequency = 33 MHz
  24. *
  25. * External Local Bus rate is
  26. * CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV
  27. */
  28. #define CONFIG_SYS_LCRR_DBYP LCRR_DBYP
  29. #define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_8
  30. /* board pre init: do not call, nothing to do */
  31. /* detect the number of flash banks */
  32. /*
  33. * DDR Setup
  34. */
  35. /* DDR is system memory*/
  36. #define CONFIG_SYS_DDR_BASE 0x00000000
  37. #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
  38. #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
  39. #define DDR_CASLAT_25 /* CASLAT set to 2.5 */
  40. #undef CONFIG_DDR_ECC /* only for ECC DDR module */
  41. #undef CONFIG_SPD_EEPROM /* do not use SPD EEPROM for DDR setup */
  42. #undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */
  43. #define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest region */
  44. #define CONFIG_SYS_MEMTEST_END 0x00100000
  45. /*
  46. * FLASH on the Local Bus
  47. */
  48. #undef CONFIG_SYS_FLASH_CHECKSUM
  49. #define CONFIG_SYS_FLASH_BASE 0x80000000 /* start of FLASH */
  50. #define CONFIG_SYS_FLASH_SIZE 8 /* FLASH size in MB */
  51. #define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sectors */
  52. /*
  53. * FLASH bank number detection
  54. */
  55. /*
  56. * When CONFIG_SYS_MAX_FLASH_BANKS_DETECT is defined, the actual number of
  57. * Flash banks has to be determined at runtime and stored in a gloabl variable
  58. * tqm834x_num_flash_banks. The value of CONFIG_SYS_MAX_FLASH_BANKS_DETECT is
  59. * only used instead of CONFIG_SYS_MAX_FLASH_BANKS to allocate the array
  60. * flash_info, and should be made sufficiently large to accomodate the number
  61. * of banks that might actually be detected. Since most (all?) Flash related
  62. * functions use CONFIG_SYS_MAX_FLASH_BANKS as the number of actual banks on
  63. * the board, it is defined as tqm834x_num_flash_banks.
  64. */
  65. #define CONFIG_SYS_MAX_FLASH_BANKS_DETECT 2
  66. #define CONFIG_SYS_MAX_FLASH_SECT 512 /* max sectors per device */
  67. /* 32 bit device at 0x80000000 via GPCM (0x8000_1801) */
  68. #define CONFIG_SYS_BR0_PRELIM ((CONFIG_SYS_FLASH_BASE & BR_BA) \
  69. | BR_MS_GPCM \
  70. | BR_PS_32 \
  71. | BR_V)
  72. /* FLASH timing (0x0000_0c54) */
  73. #define CONFIG_SYS_OR_TIMING_FLASH (OR_GPCM_CSNT \
  74. | OR_GPCM_ACS_DIV4 \
  75. | OR_GPCM_SCY_5 \
  76. | OR_GPCM_TRLX)
  77. #define CONFIG_SYS_PRELIM_OR_AM OR_AM_1GB /* OR addr mask: 1 GiB */
  78. #define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM \
  79. | CONFIG_SYS_OR_TIMING_FLASH)
  80. #define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_1GB)
  81. /* Window base at flash base */
  82. #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
  83. /* disable remaining mappings */
  84. #define CONFIG_SYS_BR1_PRELIM 0x00000000
  85. #define CONFIG_SYS_OR1_PRELIM 0x00000000
  86. #define CONFIG_SYS_LBLAWBAR1_PRELIM 0x00000000
  87. #define CONFIG_SYS_LBLAWAR1_PRELIM 0x00000000
  88. #define CONFIG_SYS_BR2_PRELIM 0x00000000
  89. #define CONFIG_SYS_OR2_PRELIM 0x00000000
  90. #define CONFIG_SYS_LBLAWBAR2_PRELIM 0x00000000
  91. #define CONFIG_SYS_LBLAWAR2_PRELIM 0x00000000
  92. #define CONFIG_SYS_BR3_PRELIM 0x00000000
  93. #define CONFIG_SYS_OR3_PRELIM 0x00000000
  94. #define CONFIG_SYS_LBLAWBAR3_PRELIM 0x00000000
  95. #define CONFIG_SYS_LBLAWAR3_PRELIM 0x00000000
  96. /*
  97. * Monitor config
  98. */
  99. #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
  100. #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
  101. # define CONFIG_SYS_RAMBOOT
  102. #else
  103. # undef CONFIG_SYS_RAMBOOT
  104. #endif
  105. #define CONFIG_SYS_INIT_RAM_LOCK 1
  106. #define CONFIG_SYS_INIT_RAM_ADDR 0x20000000 /* Initial RAM address */
  107. #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM*/
  108. #define CONFIG_SYS_GBL_DATA_OFFSET \
  109. (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
  110. #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
  111. /* Reserve 384 kB = 3 sect. for Mon */
  112. #define CONFIG_SYS_MONITOR_LEN (384 * 1024)
  113. /* Reserve 512 kB for malloc */
  114. #define CONFIG_SYS_MALLOC_LEN (512 * 1024)
  115. /*
  116. * Serial Port
  117. */
  118. #define CONFIG_SYS_NS16550_SERIAL
  119. #define CONFIG_SYS_NS16550_REG_SIZE 1
  120. #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
  121. #define CONFIG_SYS_BAUDRATE_TABLE \
  122. {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
  123. #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500)
  124. #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600)
  125. /*
  126. * I2C
  127. */
  128. #define CONFIG_SYS_I2C
  129. #define CONFIG_SYS_I2C_FSL
  130. #define CONFIG_SYS_FSL_I2C_SPEED 400000
  131. #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
  132. #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
  133. /* I2C EEPROM, configuration for onboard EEPROMs 24C256 and 24C32 */
  134. #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* 1010000x */
  135. #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* 16 bit */
  136. #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5 /* 32 bytes/write */
  137. #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 12 /* 10ms +/- 20% */
  138. /* I2C RTC */
  139. #define CONFIG_RTC_DS1337 /* use ds1337 rtc via i2c */
  140. #define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */
  141. /*
  142. * TSEC
  143. */
  144. #define CONFIG_SYS_TSEC1_OFFSET 0x24000
  145. #define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC1_OFFSET)
  146. #define CONFIG_SYS_TSEC2_OFFSET 0x25000
  147. #define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC2_OFFSET)
  148. #if defined(CONFIG_TSEC_ENET)
  149. #define CONFIG_TSEC1 1
  150. #define CONFIG_TSEC1_NAME "TSEC0"
  151. #define CONFIG_TSEC2 1
  152. #define CONFIG_TSEC2_NAME "TSEC1"
  153. #define TSEC1_PHY_ADDR 2
  154. #define TSEC2_PHY_ADDR 1
  155. #define TSEC1_PHYIDX 0
  156. #define TSEC2_PHYIDX 0
  157. #define TSEC1_FLAGS TSEC_GIGABIT
  158. #define TSEC2_FLAGS TSEC_GIGABIT
  159. /* Options are: TSEC[0-1] */
  160. #define CONFIG_ETHPRIME "TSEC0"
  161. #endif /* CONFIG_TSEC_ENET */
  162. #if defined(CONFIG_PCI)
  163. #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
  164. /* PCI1 host bridge */
  165. #define CONFIG_SYS_PCI1_MEM_BASE 0x90000000
  166. #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
  167. #define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */
  168. #define CONFIG_SYS_PCI1_MMIO_BASE \
  169. (CONFIG_SYS_PCI1_MEM_BASE + CONFIG_SYS_PCI1_MEM_SIZE)
  170. #define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE
  171. #define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */
  172. #define CONFIG_SYS_PCI1_IO_BASE 0xe2000000
  173. #define CONFIG_SYS_PCI1_IO_PHYS CONFIG_SYS_PCI1_IO_BASE
  174. #define CONFIG_SYS_PCI1_IO_SIZE 0x1000000 /* 16M */
  175. #undef CONFIG_EEPRO100
  176. #define CONFIG_EEPRO100
  177. #undef CONFIG_TULIP
  178. #if !defined(CONFIG_PCI_PNP)
  179. #define PCI_ENET0_IOADDR CONFIG_SYS_PCI1_IO_BASE
  180. #define PCI_ENET0_MEMADDR CONFIG_SYS_PCI1_MEM_BASE
  181. #define PCI_IDSEL_NUMBER 0x1c /* slot0 (IDSEL) = 28 */
  182. #endif
  183. #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */
  184. #endif /* CONFIG_PCI */
  185. /*
  186. * Environment
  187. */
  188. #define CONFIG_ENV_ADDR \
  189. (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
  190. #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) for env */
  191. #define CONFIG_ENV_SIZE 0x8000 /* 32K max size */
  192. #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
  193. #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
  194. #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
  195. #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
  196. /*
  197. * BOOTP options
  198. */
  199. #define CONFIG_BOOTP_BOOTFILESIZE
  200. /*
  201. * Miscellaneous configurable options
  202. */
  203. #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
  204. #undef CONFIG_WATCHDOG /* watchdog disabled */
  205. /*
  206. * For booting Linux, the board info and command line data
  207. * have to be in the first 256 MB of memory, since this is
  208. * the maximum mapped by the Linux kernel during initialization.
  209. */
  210. /* Initial Memory map for Linux */
  211. #define CONFIG_SYS_BOOTMAPSZ (256 << 20)
  212. #define CONFIG_SYS_HRCW_LOW (\
  213. HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
  214. HRCWL_DDR_TO_SCB_CLK_1X1 |\
  215. HRCWL_CSB_TO_CLKIN_4X1 |\
  216. HRCWL_VCO_1X2 |\
  217. HRCWL_CORE_TO_CSB_2X1)
  218. #if defined(PCI_64BIT)
  219. #define CONFIG_SYS_HRCW_HIGH (\
  220. HRCWH_PCI_HOST |\
  221. HRCWH_64_BIT_PCI |\
  222. HRCWH_PCI1_ARBITER_ENABLE |\
  223. HRCWH_PCI2_ARBITER_DISABLE |\
  224. HRCWH_CORE_ENABLE |\
  225. HRCWH_FROM_0X00000100 |\
  226. HRCWH_BOOTSEQ_DISABLE |\
  227. HRCWH_SW_WATCHDOG_DISABLE |\
  228. HRCWH_ROM_LOC_LOCAL_16BIT |\
  229. HRCWH_TSEC1M_IN_GMII |\
  230. HRCWH_TSEC2M_IN_GMII)
  231. #else
  232. #define CONFIG_SYS_HRCW_HIGH (\
  233. HRCWH_PCI_HOST |\
  234. HRCWH_32_BIT_PCI |\
  235. HRCWH_PCI1_ARBITER_ENABLE |\
  236. HRCWH_PCI2_ARBITER_DISABLE |\
  237. HRCWH_CORE_ENABLE |\
  238. HRCWH_FROM_0X00000100 |\
  239. HRCWH_BOOTSEQ_DISABLE |\
  240. HRCWH_SW_WATCHDOG_DISABLE |\
  241. HRCWH_ROM_LOC_LOCAL_16BIT |\
  242. HRCWH_TSEC1M_IN_GMII |\
  243. HRCWH_TSEC2M_IN_GMII)
  244. #endif
  245. /* System IO Config */
  246. #define CONFIG_SYS_SICRH 0
  247. #define CONFIG_SYS_SICRL SICRL_LDP_A
  248. /* i-cache and d-cache disabled */
  249. #define CONFIG_SYS_HID0_INIT 0x000000000
  250. #define CONFIG_SYS_HID0_FINAL (CONFIG_SYS_HID0_INIT | \
  251. HID0_ENABLE_INSTRUCTION_CACHE)
  252. #define CONFIG_SYS_HID2 HID2_HBE
  253. #define CONFIG_HIGH_BATS 1 /* High BATs supported */
  254. /* DDR 0 - 512M */
  255. #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE \
  256. | BATL_PP_RW \
  257. | BATL_MEMCOHERENCE)
  258. #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \
  259. | BATU_BL_256M \
  260. | BATU_VS \
  261. | BATU_VP)
  262. #define CONFIG_SYS_IBAT1L (CONFIG_SYS_SDRAM_BASE + 0x10000000 \
  263. | BATL_PP_RW \
  264. | BATL_MEMCOHERENCE)
  265. #define CONFIG_SYS_IBAT1U (CONFIG_SYS_SDRAM_BASE + 0x10000000 \
  266. | BATU_BL_256M \
  267. | BATU_VS \
  268. | BATU_VP)
  269. /* stack in DCACHE @ 512M (no backing mem) */
  270. #define CONFIG_SYS_IBAT2L (CONFIG_SYS_INIT_RAM_ADDR \
  271. | BATL_PP_RW \
  272. | BATL_MEMCOHERENCE)
  273. #define CONFIG_SYS_IBAT2U (CONFIG_SYS_INIT_RAM_ADDR \
  274. | BATU_BL_128K \
  275. | BATU_VS \
  276. | BATU_VP)
  277. /* PCI */
  278. #ifdef CONFIG_PCI
  279. #define CONFIG_PCI_INDIRECT_BRIDGE
  280. #define CONFIG_SYS_IBAT3L (CONFIG_SYS_PCI1_MEM_BASE \
  281. | BATL_PP_RW \
  282. | BATL_MEMCOHERENCE)
  283. #define CONFIG_SYS_IBAT3U (CONFIG_SYS_PCI1_MEM_BASE \
  284. | BATU_BL_256M \
  285. | BATU_VS \
  286. | BATU_VP)
  287. #define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCI1_MMIO_BASE \
  288. | BATL_PP_RW \
  289. | BATL_MEMCOHERENCE \
  290. | BATL_GUARDEDSTORAGE)
  291. #define CONFIG_SYS_IBAT4U (CONFIG_SYS_PCI1_MMIO_BASE \
  292. | BATU_BL_256M \
  293. | BATU_VS \
  294. | BATU_VP)
  295. #define CONFIG_SYS_IBAT5L (CONFIG_SYS_PCI1_IO_BASE \
  296. | BATL_PP_RW \
  297. | BATL_CACHEINHIBIT \
  298. | BATL_GUARDEDSTORAGE)
  299. #define CONFIG_SYS_IBAT5U (CONFIG_SYS_PCI1_IO_BASE \
  300. | BATU_BL_16M \
  301. | BATU_VS \
  302. | BATU_VP)
  303. #else
  304. #define CONFIG_SYS_IBAT3L (0)
  305. #define CONFIG_SYS_IBAT3U (0)
  306. #define CONFIG_SYS_IBAT4L (0)
  307. #define CONFIG_SYS_IBAT4U (0)
  308. #define CONFIG_SYS_IBAT5L (0)
  309. #define CONFIG_SYS_IBAT5U (0)
  310. #endif
  311. /* IMMRBAR */
  312. #define CONFIG_SYS_IBAT6L (CONFIG_SYS_IMMR \
  313. | BATL_PP_RW \
  314. | BATL_CACHEINHIBIT \
  315. | BATL_GUARDEDSTORAGE)
  316. #define CONFIG_SYS_IBAT6U (CONFIG_SYS_IMMR \
  317. | BATU_BL_1M \
  318. | BATU_VS \
  319. | BATU_VP)
  320. /* FLASH */
  321. #define CONFIG_SYS_IBAT7L (CONFIG_SYS_FLASH_BASE \
  322. | BATL_PP_RW \
  323. | BATL_CACHEINHIBIT \
  324. | BATL_GUARDEDSTORAGE)
  325. #define CONFIG_SYS_IBAT7U (CONFIG_SYS_FLASH_BASE \
  326. | BATU_BL_256M \
  327. | BATU_VS \
  328. | BATU_VP)
  329. #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
  330. #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
  331. #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
  332. #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
  333. #define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L
  334. #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
  335. #define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
  336. #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
  337. #define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L
  338. #define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U
  339. #define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L
  340. #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
  341. #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
  342. #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
  343. #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
  344. #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
  345. #if defined(CONFIG_CMD_KGDB)
  346. #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
  347. #endif
  348. /*
  349. * Environment Configuration
  350. */
  351. /* default location for tftp and bootm */
  352. #define CONFIG_LOADADDR 400000
  353. #define CONFIG_PREBOOT "echo;" \
  354. "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
  355. "echo"
  356. #define CONFIG_EXTRA_ENV_SETTINGS \
  357. "netdev=eth0\0" \
  358. "hostname=tqm834x\0" \
  359. "nfsargs=setenv bootargs root=/dev/nfs rw " \
  360. "nfsroot=${serverip}:${rootpath}\0" \
  361. "ramargs=setenv bootargs root=/dev/ram rw\0" \
  362. "addip=setenv bootargs ${bootargs} " \
  363. "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
  364. ":${hostname}:${netdev}:off panic=1\0" \
  365. "addcons=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0" \
  366. "flash_nfs_old=run nfsargs addip addcons;" \
  367. "bootm ${kernel_addr}\0" \
  368. "flash_nfs=run nfsargs addip addcons;" \
  369. "bootm ${kernel_addr} - ${fdt_addr}\0" \
  370. "flash_self_old=run ramargs addip addcons;" \
  371. "bootm ${kernel_addr} ${ramdisk_addr}\0" \
  372. "flash_self=run ramargs addip addcons;" \
  373. "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \
  374. "net_nfs_old=tftp 400000 ${bootfile};" \
  375. "run nfsargs addip addcons;bootm\0" \
  376. "net_nfs=tftp ${kernel_addr_r} ${bootfile}; " \
  377. "tftp ${fdt_addr_r} ${fdt_file}; " \
  378. "run nfsargs addip addcons; " \
  379. "bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \
  380. "rootpath=/opt/eldk/ppc_6xx\0" \
  381. "bootfile=tqm834x/uImage\0" \
  382. "fdtfile=tqm834x/tqm834x.dtb\0" \
  383. "kernel_addr_r=400000\0" \
  384. "fdt_addr_r=600000\0" \
  385. "ramdisk_addr_r=800000\0" \
  386. "kernel_addr=800C0000\0" \
  387. "fdt_addr=800A0000\0" \
  388. "ramdisk_addr=80300000\0" \
  389. "u-boot=tqm834x/u-boot.bin\0" \
  390. "load=tftp 200000 ${u-boot}\0" \
  391. "update=protect off 80000000 +${filesize};" \
  392. "era 80000000 +${filesize};" \
  393. "cp.b 200000 80000000 ${filesize}\0" \
  394. "upd=run load update\0" \
  395. ""
  396. #define CONFIG_BOOTCOMMAND "run flash_self"
  397. /*
  398. * JFFS2 partitions
  399. */
  400. /* mtdparts command line support */
  401. /* default mtd partition table */
  402. #endif /* __CONFIG_H */