MPC8349ITX.h 19 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright (C) Freescale Semiconductor, Inc. 2006.
  4. */
  5. /*
  6. MPC8349E-mITX and MPC8349E-mITX-GP board configuration file
  7. Memory map:
  8. 0x0000_0000-0x0FFF_FFFF DDR SDRAM (256 MB)
  9. 0x8000_0000-0x9FFF_FFFF PCI1 memory space (512 MB)
  10. 0xA000_0000-0xBFFF_FFFF PCI2 memory space (512 MB)
  11. 0xE000_0000-0xEFFF_FFFF IMMR (1 MB)
  12. 0xE200_0000-0xE2FF_FFFF PCI1 I/O space (16 MB)
  13. 0xE300_0000-0xE3FF_FFFF PCI2 I/O space (16 MB)
  14. 0xF000_0000-0xF000_FFFF Compact Flash (MPC8349E-mITX only)
  15. 0xF001_0000-0xF001_FFFF Local bus expansion slot
  16. 0xF800_0000-0xF801_FFFF Vitesse 7385 Parallel Interface (MPC8349E-mITX only)
  17. 0xFE00_0000-0xFE7F_FFFF First 8MB bank of Flash memory
  18. 0xFE80_0000-0xFEFF_FFFF Second 8MB bank of Flash memory (MPC8349E-mITX only)
  19. I2C address list:
  20. Align. Board
  21. Bus Addr Part No. Description Length Location
  22. ----------------------------------------------------------------
  23. I2C0 0x50 M24256-BWMN6P Board EEPROM 2 U64
  24. I2C1 0x20 PCF8574 I2C Expander 0 U8
  25. I2C1 0x21 PCF8574 I2C Expander 0 U10
  26. I2C1 0x38 PCF8574A I2C Expander 0 U8
  27. I2C1 0x39 PCF8574A I2C Expander 0 U10
  28. I2C1 0x51 (DDR) DDR EEPROM 1 U1
  29. I2C1 0x68 DS1339 RTC 1 U68
  30. Note that a given board has *either* a pair of 8574s or a pair of 8574As.
  31. */
  32. #ifndef __CONFIG_H
  33. #define __CONFIG_H
  34. #if (CONFIG_SYS_TEXT_BASE == 0xFE000000)
  35. #define CONFIG_SYS_LOWBOOT
  36. #endif
  37. /*
  38. * High Level Configuration Options
  39. */
  40. #define CONFIG_SYS_IMMR 0xE0000000 /* The IMMR is relocated to here */
  41. #define CONFIG_MISC_INIT_F
  42. /*
  43. * On-board devices
  44. */
  45. #ifdef CONFIG_MPC8349ITX
  46. /* The CF card interface on the back of the board */
  47. #define CONFIG_COMPACT_FLASH
  48. #define CONFIG_VSC7385_ENET /* VSC7385 ethernet support */
  49. #define CONFIG_SYS_USB_HOST /* use the EHCI USB controller */
  50. #endif
  51. #define CONFIG_RTC_DS1337
  52. #define CONFIG_SYS_I2C
  53. /*
  54. * Device configurations
  55. */
  56. /* I2C */
  57. #ifdef CONFIG_SYS_I2C
  58. #define CONFIG_SYS_I2C_FSL
  59. #define CONFIG_SYS_FSL_I2C_SPEED 400000
  60. #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
  61. #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
  62. #define CONFIG_SYS_FSL_I2C2_SPEED 400000
  63. #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
  64. #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
  65. #define CONFIG_SYS_SPD_BUS_NUM 1 /* The I2C bus for SPD */
  66. #define CONFIG_SYS_RTC_BUS_NUM 1 /* The I2C bus for RTC */
  67. #define CONFIG_SYS_I2C_8574_ADDR1 0x20 /* I2C1, PCF8574 */
  68. #define CONFIG_SYS_I2C_8574_ADDR2 0x21 /* I2C1, PCF8574 */
  69. #define CONFIG_SYS_I2C_8574A_ADDR1 0x38 /* I2C1, PCF8574A */
  70. #define CONFIG_SYS_I2C_8574A_ADDR2 0x39 /* I2C1, PCF8574A */
  71. #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* I2C0, Board EEPROM */
  72. #define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* I2C1, DS1339 RTC*/
  73. #define SPD_EEPROM_ADDRESS 0x51 /* I2C1, DDR */
  74. /* Don't probe these addresses: */
  75. #define CONFIG_SYS_I2C_NOPROBES { {1, CONFIG_SYS_I2C_8574_ADDR1}, \
  76. {1, CONFIG_SYS_I2C_8574_ADDR2}, \
  77. {1, CONFIG_SYS_I2C_8574A_ADDR1}, \
  78. {1, CONFIG_SYS_I2C_8574A_ADDR2} }
  79. /* Bit definitions for the 8574[A] I2C expander */
  80. /* Board revision, 00=0.0, 01=0.1, 10=1.0 */
  81. #define I2C_8574_REVISION 0x03
  82. #define I2C_8574_CF 0x08 /* 1=Compact flash absent, 0=present */
  83. #define I2C_8574_MPCICLKRN 0x10 /* MiniPCI Clk Run */
  84. #define I2C_8574_PCI66 0x20 /* 0=33MHz PCI, 1=66MHz PCI */
  85. #define I2C_8574_FLASHSIDE 0x40 /* 0=Reset vector from U4, 1=from U7*/
  86. #endif
  87. /* Compact Flash */
  88. #ifdef CONFIG_COMPACT_FLASH
  89. #define CONFIG_SYS_IDE_MAXBUS 1
  90. #define CONFIG_SYS_IDE_MAXDEVICE 1
  91. #define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
  92. #define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_CF_BASE
  93. #define CONFIG_SYS_ATA_DATA_OFFSET 0x0000
  94. #define CONFIG_SYS_ATA_REG_OFFSET 0
  95. #define CONFIG_SYS_ATA_ALT_OFFSET 0x0200
  96. #define CONFIG_SYS_ATA_STRIDE 2
  97. /* If a CF card is not inserted, time out quickly */
  98. #define ATA_RESET_TIME 1
  99. #endif
  100. /*
  101. * SATA
  102. */
  103. #ifdef CONFIG_SATA_SIL3114
  104. #define CONFIG_SYS_SATA_MAX_DEVICE 4
  105. #define CONFIG_LBA48
  106. #endif
  107. #ifdef CONFIG_SYS_USB_HOST
  108. /*
  109. * Support USB
  110. */
  111. #define CONFIG_USB_EHCI_FSL
  112. /* Current USB implementation supports the only USB controller,
  113. * so we have to choose between the MPH or the DR ones */
  114. #if 1
  115. #define CONFIG_HAS_FSL_MPH_USB
  116. #else
  117. #define CONFIG_HAS_FSL_DR_USB
  118. #endif
  119. #endif
  120. /*
  121. * DDR Setup
  122. */
  123. #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory*/
  124. #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
  125. #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
  126. #define CONFIG_SYS_83XX_DDR_USES_CS0
  127. #define CONFIG_SYS_MEMTEST_START 0x1000 /* memtest region */
  128. #define CONFIG_SYS_MEMTEST_END 0x2000
  129. #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN \
  130. | DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075)
  131. #define CONFIG_VERY_BIG_RAM
  132. #define CONFIG_MAX_MEM_MAPPED ((phys_size_t)256 << 20)
  133. #ifdef CONFIG_SYS_I2C
  134. #define CONFIG_SPD_EEPROM /* use SPD EEPROM for DDR setup*/
  135. #endif
  136. /* No SPD? Then manually set up DDR parameters */
  137. #ifndef CONFIG_SPD_EEPROM
  138. #define CONFIG_SYS_DDR_SIZE 256 /* Mb */
  139. #define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \
  140. | CSCONFIG_ROW_BIT_13 \
  141. | CSCONFIG_COL_BIT_10)
  142. #define CONFIG_SYS_DDR_TIMING_1 0x26242321
  143. #define CONFIG_SYS_DDR_TIMING_2 0x00000800 /* P9-45, may need tuning */
  144. #endif
  145. /*
  146. *Flash on the Local Bus
  147. */
  148. #define CONFIG_SYS_FLASH_BASE 0xFE000000 /* start of FLASH */
  149. #define CONFIG_SYS_FLASH_EMPTY_INFO
  150. /* 127 64KB sectors + 8 8KB sectors per device */
  151. #define CONFIG_SYS_MAX_FLASH_SECT 135
  152. #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
  153. #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
  154. #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
  155. /* The ITX has two flash chips, but the ITX-GP has only one. To support both
  156. boards, we say we have two, but don't display a message if we find only one. */
  157. #define CONFIG_SYS_FLASH_QUIET_TEST
  158. #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
  159. #define CONFIG_SYS_FLASH_BANKS_LIST \
  160. {CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE + 0x800000}
  161. #define CONFIG_SYS_FLASH_SIZE 16 /* FLASH size in MB */
  162. /* Vitesse 7385 */
  163. #ifdef CONFIG_VSC7385_ENET
  164. #define CONFIG_TSEC2
  165. /* The flash address and size of the VSC7385 firmware image */
  166. #define CONFIG_VSC7385_IMAGE 0xFEFFE000
  167. #define CONFIG_VSC7385_IMAGE_SIZE 8192
  168. #endif
  169. /*
  170. * BRx, ORx, LBLAWBARx, and LBLAWARx
  171. */
  172. /* Flash */
  173. #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \
  174. | BR_PS_16 \
  175. | BR_MS_GPCM \
  176. | BR_V)
  177. #define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
  178. | OR_UPM_XAM \
  179. | OR_GPCM_CSNT \
  180. | OR_GPCM_ACS_DIV2 \
  181. | OR_GPCM_XACS \
  182. | OR_GPCM_SCY_15 \
  183. | OR_GPCM_TRLX_SET \
  184. | OR_GPCM_EHTR_SET \
  185. | OR_GPCM_EAD)
  186. #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
  187. #define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_16MB)
  188. /* Vitesse 7385 */
  189. #define CONFIG_SYS_VSC7385_BASE 0xF8000000
  190. #ifdef CONFIG_VSC7385_ENET
  191. #define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_VSC7385_BASE \
  192. | BR_PS_8 \
  193. | BR_MS_GPCM \
  194. | BR_V)
  195. #define CONFIG_SYS_OR1_PRELIM (OR_AM_128KB \
  196. | OR_GPCM_CSNT \
  197. | OR_GPCM_XACS \
  198. | OR_GPCM_SCY_15 \
  199. | OR_GPCM_SETA \
  200. | OR_GPCM_TRLX_SET \
  201. | OR_GPCM_EHTR_SET \
  202. | OR_GPCM_EAD)
  203. #define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_VSC7385_BASE
  204. #define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_128KB)
  205. #endif
  206. /* LED */
  207. #define CONFIG_SYS_LED_BASE 0xF9000000
  208. #define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_LED_BASE \
  209. | BR_PS_8 \
  210. | BR_MS_GPCM \
  211. | BR_V)
  212. #define CONFIG_SYS_OR2_PRELIM (OR_AM_2MB \
  213. | OR_GPCM_CSNT \
  214. | OR_GPCM_ACS_DIV2 \
  215. | OR_GPCM_XACS \
  216. | OR_GPCM_SCY_9 \
  217. | OR_GPCM_TRLX_SET \
  218. | OR_GPCM_EHTR_SET \
  219. | OR_GPCM_EAD)
  220. /* Compact Flash */
  221. #ifdef CONFIG_COMPACT_FLASH
  222. #define CONFIG_SYS_CF_BASE 0xF0000000
  223. #define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_CF_BASE \
  224. | BR_PS_16 \
  225. | BR_MS_UPMA \
  226. | BR_V)
  227. #define CONFIG_SYS_OR3_PRELIM (OR_UPM_AM | OR_UPM_BI)
  228. #define CONFIG_SYS_LBLAWBAR3_PRELIM CONFIG_SYS_CF_BASE
  229. #define CONFIG_SYS_LBLAWAR3_PRELIM (LBLAWAR_EN | LBLAWAR_64KB)
  230. #endif
  231. /*
  232. * U-Boot memory configuration
  233. */
  234. #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
  235. #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
  236. #define CONFIG_SYS_RAMBOOT
  237. #else
  238. #undef CONFIG_SYS_RAMBOOT
  239. #endif
  240. #define CONFIG_SYS_INIT_RAM_LOCK
  241. #define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000 /* Initial RAM addr */
  242. #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM*/
  243. #define CONFIG_SYS_GBL_DATA_OFFSET \
  244. (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
  245. #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
  246. /* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
  247. #define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */
  248. #define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Reserved for malloc */
  249. /*
  250. * Local Bus LCRR and LBCR regs
  251. * LCRR: DLL bypass, Clock divider is 4
  252. * External Local Bus rate is
  253. * CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV
  254. */
  255. #define CONFIG_SYS_LCRR_DBYP LCRR_DBYP
  256. #define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4
  257. #define CONFIG_SYS_LBC_LBCR 0x00000000
  258. /* LB sdram refresh timer, about 6us */
  259. #define CONFIG_SYS_LBC_LSRT 0x32000000
  260. /* LB refresh timer prescal, 266MHz/32*/
  261. #define CONFIG_SYS_LBC_MRTPR 0x20000000
  262. /*
  263. * Serial Port
  264. */
  265. #define CONFIG_SYS_NS16550_SERIAL
  266. #define CONFIG_SYS_NS16550_REG_SIZE 1
  267. #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
  268. #define CONFIG_SYS_BAUDRATE_TABLE \
  269. {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
  270. #define CONSOLE ttyS0
  271. #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500)
  272. #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600)
  273. /*
  274. * PCI
  275. */
  276. #ifdef CONFIG_PCI
  277. #define CONFIG_PCI_INDIRECT_BRIDGE
  278. #define CONFIG_MPC83XX_PCI2
  279. /*
  280. * General PCI
  281. * Addresses are mapped 1-1.
  282. */
  283. #define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
  284. #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
  285. #define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */
  286. #define CONFIG_SYS_PCI1_MMIO_BASE \
  287. (CONFIG_SYS_PCI1_MEM_BASE + CONFIG_SYS_PCI1_MEM_SIZE)
  288. #define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE
  289. #define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */
  290. #define CONFIG_SYS_PCI1_IO_BASE 0x00000000
  291. #define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000
  292. #define CONFIG_SYS_PCI1_IO_SIZE 0x01000000 /* 16M */
  293. #ifdef CONFIG_MPC83XX_PCI2
  294. #define CONFIG_SYS_PCI2_MEM_BASE \
  295. (CONFIG_SYS_PCI1_MMIO_BASE + CONFIG_SYS_PCI1_MMIO_SIZE)
  296. #define CONFIG_SYS_PCI2_MEM_PHYS CONFIG_SYS_PCI2_MEM_BASE
  297. #define CONFIG_SYS_PCI2_MEM_SIZE 0x10000000 /* 256M */
  298. #define CONFIG_SYS_PCI2_MMIO_BASE \
  299. (CONFIG_SYS_PCI2_MEM_BASE + CONFIG_SYS_PCI2_MEM_SIZE)
  300. #define CONFIG_SYS_PCI2_MMIO_PHYS CONFIG_SYS_PCI2_MMIO_BASE
  301. #define CONFIG_SYS_PCI2_MMIO_SIZE 0x10000000 /* 256M */
  302. #define CONFIG_SYS_PCI2_IO_BASE 0x00000000
  303. #define CONFIG_SYS_PCI2_IO_PHYS \
  304. (CONFIG_SYS_PCI1_IO_PHYS + CONFIG_SYS_PCI1_IO_SIZE)
  305. #define CONFIG_SYS_PCI2_IO_SIZE 0x01000000 /* 16M */
  306. #endif
  307. #ifndef CONFIG_PCI_PNP
  308. #define PCI_ENET0_IOADDR 0x00000000
  309. #define PCI_ENET0_MEMADDR CONFIG_SYS_PCI2_MEM_BASE
  310. #define PCI_IDSEL_NUMBER 0x0f /* IDSEL = AD15 */
  311. #endif
  312. #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
  313. #endif
  314. #define CONFIG_PCI_66M
  315. #ifdef CONFIG_PCI_66M
  316. #define CONFIG_83XX_CLKIN 66666666 /* in Hz */
  317. #else
  318. #define CONFIG_83XX_CLKIN 33333333 /* in Hz */
  319. #endif
  320. /* TSEC */
  321. #ifdef CONFIG_TSEC_ENET
  322. #define CONFIG_TSEC1
  323. #ifdef CONFIG_TSEC1
  324. #define CONFIG_HAS_ETH0
  325. #define CONFIG_TSEC1_NAME "TSEC0"
  326. #define CONFIG_SYS_TSEC1_OFFSET 0x24000
  327. #define TSEC1_PHY_ADDR 0x1c /* VSC8201 uses address 0x1c */
  328. #define TSEC1_PHYIDX 0
  329. #define TSEC1_FLAGS TSEC_GIGABIT
  330. #endif
  331. #ifdef CONFIG_TSEC2
  332. #define CONFIG_HAS_ETH1
  333. #define CONFIG_TSEC2_NAME "TSEC1"
  334. #define CONFIG_SYS_TSEC2_OFFSET 0x25000
  335. #define TSEC2_PHY_ADDR 4
  336. #define TSEC2_PHYIDX 0
  337. #define TSEC2_FLAGS TSEC_GIGABIT
  338. #endif
  339. #define CONFIG_ETHPRIME "Freescale TSEC"
  340. #endif
  341. /*
  342. * Environment
  343. */
  344. #define CONFIG_ENV_OVERWRITE
  345. #ifndef CONFIG_SYS_RAMBOOT
  346. #define CONFIG_ENV_ADDR \
  347. (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
  348. #define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K (one sector) for environment */
  349. #define CONFIG_ENV_SIZE 0x2000
  350. #else
  351. #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
  352. #define CONFIG_ENV_SIZE 0x2000
  353. #endif
  354. #define CONFIG_LOADS_ECHO /* echo on for serial download */
  355. #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
  356. /*
  357. * BOOTP options
  358. */
  359. #define CONFIG_BOOTP_BOOTFILESIZE
  360. /* Watchdog */
  361. #undef CONFIG_WATCHDOG /* watchdog disabled */
  362. /*
  363. * Miscellaneous configurable options
  364. */
  365. #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
  366. #define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */
  367. /*
  368. * For booting Linux, the board info and command line data
  369. * have to be in the first 256 MB of memory, since this is
  370. * the maximum mapped by the Linux kernel during initialization.
  371. */
  372. /* Initial Memory map for Linux*/
  373. #define CONFIG_SYS_BOOTMAPSZ (256 << 20)
  374. #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
  375. #define CONFIG_SYS_HRCW_LOW (\
  376. HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
  377. HRCWL_DDR_TO_SCB_CLK_1X1 |\
  378. HRCWL_CSB_TO_CLKIN_4X1 |\
  379. HRCWL_VCO_1X2 |\
  380. HRCWL_CORE_TO_CSB_2X1)
  381. #ifdef CONFIG_SYS_LOWBOOT
  382. #define CONFIG_SYS_HRCW_HIGH (\
  383. HRCWH_PCI_HOST |\
  384. HRCWH_32_BIT_PCI |\
  385. HRCWH_PCI1_ARBITER_ENABLE |\
  386. HRCWH_PCI2_ARBITER_ENABLE |\
  387. HRCWH_CORE_ENABLE |\
  388. HRCWH_FROM_0X00000100 |\
  389. HRCWH_BOOTSEQ_DISABLE |\
  390. HRCWH_SW_WATCHDOG_DISABLE |\
  391. HRCWH_ROM_LOC_LOCAL_16BIT |\
  392. HRCWH_TSEC1M_IN_GMII |\
  393. HRCWH_TSEC2M_IN_GMII)
  394. #else
  395. #define CONFIG_SYS_HRCW_HIGH (\
  396. HRCWH_PCI_HOST |\
  397. HRCWH_32_BIT_PCI |\
  398. HRCWH_PCI1_ARBITER_ENABLE |\
  399. HRCWH_PCI2_ARBITER_ENABLE |\
  400. HRCWH_CORE_ENABLE |\
  401. HRCWH_FROM_0XFFF00100 |\
  402. HRCWH_BOOTSEQ_DISABLE |\
  403. HRCWH_SW_WATCHDOG_DISABLE |\
  404. HRCWH_ROM_LOC_LOCAL_16BIT |\
  405. HRCWH_TSEC1M_IN_GMII |\
  406. HRCWH_TSEC2M_IN_GMII)
  407. #endif
  408. /*
  409. * System performance
  410. */
  411. #define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */
  412. #define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */
  413. #define CONFIG_SYS_SPCR_TSEC1EP 3 /* TSEC1 emergency priority (0-3) */
  414. #define CONFIG_SYS_SPCR_TSEC2EP 3 /* TSEC2 emergency priority (0-3) */
  415. #define CONFIG_SYS_SCCR_TSEC1CM 1 /* TSEC1 clock mode (0-3) */
  416. #define CONFIG_SYS_SCCR_TSEC2CM 1 /* TSEC2 & I2C0 clock mode (0-3) */
  417. #define CONFIG_SYS_SCCR_USBMPHCM 3 /* USB MPH controller's clock */
  418. #define CONFIG_SYS_SCCR_USBDRCM 0 /* USB DR controller's clock */
  419. /*
  420. * System IO Config
  421. */
  422. /* Needed for gigabit to work on TSEC 1 */
  423. #define CONFIG_SYS_SICRH SICRH_TSOBI1
  424. /* USB DR as device + USB MPH as host */
  425. #define CONFIG_SYS_SICRL (SICRL_LDP_A | SICRL_USB1)
  426. #define CONFIG_SYS_HID0_INIT 0x00000000
  427. #define CONFIG_SYS_HID0_FINAL HID0_ENABLE_INSTRUCTION_CACHE
  428. #define CONFIG_SYS_HID2 HID2_HBE
  429. #define CONFIG_HIGH_BATS 1 /* High BATs supported */
  430. /* DDR */
  431. #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE \
  432. | BATL_PP_RW \
  433. | BATL_MEMCOHERENCE)
  434. #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \
  435. | BATU_BL_256M \
  436. | BATU_VS \
  437. | BATU_VP)
  438. /* PCI */
  439. #ifdef CONFIG_PCI
  440. #define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_BASE \
  441. | BATL_PP_RW \
  442. | BATL_MEMCOHERENCE)
  443. #define CONFIG_SYS_IBAT1U (CONFIG_SYS_PCI1_MEM_BASE \
  444. | BATU_BL_256M \
  445. | BATU_VS \
  446. | BATU_VP)
  447. #define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MMIO_BASE \
  448. | BATL_PP_RW \
  449. | BATL_CACHEINHIBIT \
  450. | BATL_GUARDEDSTORAGE)
  451. #define CONFIG_SYS_IBAT2U (CONFIG_SYS_PCI1_MMIO_BASE \
  452. | BATU_BL_256M \
  453. | BATU_VS \
  454. | BATU_VP)
  455. #else
  456. #define CONFIG_SYS_IBAT1L 0
  457. #define CONFIG_SYS_IBAT1U 0
  458. #define CONFIG_SYS_IBAT2L 0
  459. #define CONFIG_SYS_IBAT2U 0
  460. #endif
  461. #ifdef CONFIG_MPC83XX_PCI2
  462. #define CONFIG_SYS_IBAT3L (CONFIG_SYS_PCI2_MEM_BASE \
  463. | BATL_PP_RW \
  464. | BATL_MEMCOHERENCE)
  465. #define CONFIG_SYS_IBAT3U (CONFIG_SYS_PCI2_MEM_BASE \
  466. | BATU_BL_256M \
  467. | BATU_VS \
  468. | BATU_VP)
  469. #define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCI2_MMIO_BASE \
  470. | BATL_PP_RW \
  471. | BATL_CACHEINHIBIT \
  472. | BATL_GUARDEDSTORAGE)
  473. #define CONFIG_SYS_IBAT4U (CONFIG_SYS_PCI2_MMIO_BASE \
  474. | BATU_BL_256M \
  475. | BATU_VS \
  476. | BATU_VP)
  477. #else
  478. #define CONFIG_SYS_IBAT3L 0
  479. #define CONFIG_SYS_IBAT3U 0
  480. #define CONFIG_SYS_IBAT4L 0
  481. #define CONFIG_SYS_IBAT4U 0
  482. #endif
  483. /* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000 */
  484. #define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR \
  485. | BATL_PP_RW \
  486. | BATL_CACHEINHIBIT \
  487. | BATL_GUARDEDSTORAGE)
  488. #define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR \
  489. | BATU_BL_256M \
  490. | BATU_VS \
  491. | BATU_VP)
  492. /* SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */
  493. #define CONFIG_SYS_IBAT6L (0xF0000000 \
  494. | BATL_PP_RW \
  495. | BATL_MEMCOHERENCE \
  496. | BATL_GUARDEDSTORAGE)
  497. #define CONFIG_SYS_IBAT6U (0xF0000000 \
  498. | BATU_BL_256M \
  499. | BATU_VS \
  500. | BATU_VP)
  501. #define CONFIG_SYS_IBAT7L 0
  502. #define CONFIG_SYS_IBAT7U 0
  503. #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
  504. #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
  505. #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
  506. #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
  507. #define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L
  508. #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
  509. #define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
  510. #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
  511. #define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L
  512. #define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U
  513. #define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L
  514. #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
  515. #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
  516. #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
  517. #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
  518. #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
  519. #if defined(CONFIG_CMD_KGDB)
  520. #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
  521. #endif
  522. /*
  523. * Environment Configuration
  524. */
  525. #define CONFIG_ENV_OVERWRITE
  526. #define CONFIG_NETDEV "eth0"
  527. /* Default path and filenames */
  528. #define CONFIG_ROOTPATH "/nfsroot/rootfs"
  529. #define CONFIG_BOOTFILE "uImage"
  530. /* U-Boot image on TFTP server */
  531. #define CONFIG_UBOOTPATH "u-boot.bin"
  532. #ifdef CONFIG_MPC8349ITX
  533. #define CONFIG_FDTFILE "mpc8349emitx.dtb"
  534. #else
  535. #define CONFIG_FDTFILE "mpc8349emitxgp.dtb"
  536. #endif
  537. #define CONFIG_EXTRA_ENV_SETTINGS \
  538. "console=" __stringify(CONSOLE) "\0" \
  539. "netdev=" CONFIG_NETDEV "\0" \
  540. "uboot=" CONFIG_UBOOTPATH "\0" \
  541. "tftpflash=tftpboot $loadaddr $uboot; " \
  542. "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \
  543. " +$filesize; " \
  544. "erase " __stringify(CONFIG_SYS_TEXT_BASE) \
  545. " +$filesize; " \
  546. "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
  547. " $filesize; " \
  548. "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \
  549. " +$filesize; " \
  550. "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
  551. " $filesize\0" \
  552. "fdtaddr=780000\0" \
  553. "fdtfile=" CONFIG_FDTFILE "\0"
  554. #define CONFIG_NFSBOOTCOMMAND \
  555. "setenv bootargs root=/dev/nfs rw nfsroot=$serverip:$rootpath" \
  556. " ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off "\
  557. " console=$console,$baudrate $othbootargs; " \
  558. "tftp $loadaddr $bootfile;" \
  559. "tftp $fdtaddr $fdtfile;" \
  560. "bootm $loadaddr - $fdtaddr"
  561. #define CONFIG_RAMBOOTCOMMAND \
  562. "setenv bootargs root=/dev/ram rw" \
  563. " console=$console,$baudrate $othbootargs; " \
  564. "tftp $ramdiskaddr $ramdiskfile;" \
  565. "tftp $loadaddr $bootfile;" \
  566. "tftp $fdtaddr $fdtfile;" \
  567. "bootm $loadaddr $ramdiskaddr $fdtaddr"
  568. #endif