MPC8349EMDS.h 21 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * (C) Copyright 2006-2010
  4. * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  5. */
  6. /*
  7. * mpc8349emds board configuration file
  8. *
  9. */
  10. #ifndef __CONFIG_H
  11. #define __CONFIG_H
  12. /*
  13. * High Level Configuration Options
  14. */
  15. #define CONFIG_E300 1 /* E300 Family */
  16. #define CONFIG_PCI_66M
  17. #ifdef CONFIG_PCI_66M
  18. #define CONFIG_83XX_CLKIN 66000000 /* in Hz */
  19. #else
  20. #define CONFIG_83XX_CLKIN 33000000 /* in Hz */
  21. #endif
  22. #ifdef CONFIG_PCISLAVE
  23. #define CONFIG_83XX_PCICLK 66666666 /* in Hz */
  24. #endif /* CONFIG_PCISLAVE */
  25. #ifndef CONFIG_SYS_CLK_FREQ
  26. #ifdef CONFIG_PCI_66M
  27. #define CONFIG_SYS_CLK_FREQ 66000000
  28. #define HRCWL_CSB_TO_CLKIN HRCWL_CSB_TO_CLKIN_4X1
  29. #else
  30. #define CONFIG_SYS_CLK_FREQ 33000000
  31. #define HRCWL_CSB_TO_CLKIN HRCWL_CSB_TO_CLKIN_8X1
  32. #endif
  33. #endif
  34. #define CONFIG_SYS_IMMR 0xE0000000
  35. #undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */
  36. #define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest region */
  37. #define CONFIG_SYS_MEMTEST_END 0x00100000
  38. /*
  39. * DDR Setup
  40. */
  41. #define CONFIG_DDR_ECC /* support DDR ECC function */
  42. #define CONFIG_DDR_ECC_CMD /* use DDR ECC user commands */
  43. #define CONFIG_SPD_EEPROM /* use SPD EEPROM for DDR setup*/
  44. /*
  45. * SYS_FSL_DDR2 is selected in Kconfig to use unified DDR driver
  46. * unselect it to use old spd_sdram.c
  47. */
  48. #define CONFIG_SYS_SPD_BUS_NUM 0
  49. #define SPD_EEPROM_ADDRESS1 0x52
  50. #define SPD_EEPROM_ADDRESS2 0x51
  51. #define CONFIG_DIMM_SLOTS_PER_CTLR 2
  52. #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
  53. #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
  54. #define CONFIG_MEM_INIT_VALUE 0xDeadBeef
  55. /*
  56. * 32-bit data path mode.
  57. *
  58. * Please note that using this mode for devices with the real density of 64-bit
  59. * effectively reduces the amount of available memory due to the effect of
  60. * wrapping around while translating address to row/columns, for example in the
  61. * 256MB module the upper 128MB get aliased with contents of the lower
  62. * 128MB); normally this define should be used for devices with real 32-bit
  63. * data path.
  64. */
  65. #undef CONFIG_DDR_32BIT
  66. #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory*/
  67. #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
  68. #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
  69. #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN \
  70. | DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
  71. #undef CONFIG_DDR_2T_TIMING
  72. /*
  73. * DDRCDR - DDR Control Driver Register
  74. */
  75. #define CONFIG_SYS_DDRCDR_VALUE 0x80080001
  76. #if defined(CONFIG_SPD_EEPROM)
  77. /*
  78. * Determine DDR configuration from I2C interface.
  79. */
  80. #define SPD_EEPROM_ADDRESS 0x51 /* DDR DIMM */
  81. #else
  82. /*
  83. * Manually set up DDR parameters
  84. */
  85. #define CONFIG_SYS_DDR_SIZE 256 /* MB */
  86. #if defined(CONFIG_DDR_II)
  87. #define CONFIG_SYS_DDRCDR 0x80080001
  88. #define CONFIG_SYS_DDR_CS2_BNDS 0x0000000f
  89. #define CONFIG_SYS_DDR_CS2_CONFIG 0x80330102
  90. #define CONFIG_SYS_DDR_TIMING_0 0x00220802
  91. #define CONFIG_SYS_DDR_TIMING_1 0x38357322
  92. #define CONFIG_SYS_DDR_TIMING_2 0x2f9048c8
  93. #define CONFIG_SYS_DDR_TIMING_3 0x00000000
  94. #define CONFIG_SYS_DDR_CLK_CNTL 0x02000000
  95. #define CONFIG_SYS_DDR_MODE 0x47d00432
  96. #define CONFIG_SYS_DDR_MODE2 0x8000c000
  97. #define CONFIG_SYS_DDR_INTERVAL 0x03cf0080
  98. #define CONFIG_SYS_DDR_SDRAM_CFG 0x43000000
  99. #define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000
  100. #else
  101. #define CONFIG_SYS_DDR_CS2_CONFIG (CSCONFIG_EN \
  102. | CSCONFIG_ROW_BIT_13 \
  103. | CSCONFIG_COL_BIT_10)
  104. #define CONFIG_SYS_DDR_TIMING_1 0x36332321
  105. #define CONFIG_SYS_DDR_TIMING_2 0x00000800 /* P9-45,may need tuning */
  106. #define CONFIG_SYS_DDR_CONTROL 0xc2000000 /* unbuffered,no DYN_PWR */
  107. #define CONFIG_SYS_DDR_INTERVAL 0x04060100 /* autocharge,no open page */
  108. #if defined(CONFIG_DDR_32BIT)
  109. /* set burst length to 8 for 32-bit data path */
  110. /* DLL,normal,seq,4/2.5, 8 burst len */
  111. #define CONFIG_SYS_DDR_MODE 0x00000023
  112. #else
  113. /* the default burst length is 4 - for 64-bit data path */
  114. /* DLL,normal,seq,4/2.5, 4 burst len */
  115. #define CONFIG_SYS_DDR_MODE 0x00000022
  116. #endif
  117. #endif
  118. #endif
  119. /*
  120. * SDRAM on the Local Bus
  121. */
  122. #define CONFIG_SYS_LBC_SDRAM_BASE 0xF0000000 /* Localbus SDRAM */
  123. #define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */
  124. /*
  125. * FLASH on the Local Bus
  126. */
  127. #define CONFIG_SYS_FLASH_BASE 0xFE000000 /* start of FLASH */
  128. #define CONFIG_SYS_FLASH_SIZE 32 /* max flash size in MB */
  129. #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \
  130. | BR_PS_16 /* 16 bit port */ \
  131. | BR_MS_GPCM /* MSEL = GPCM */ \
  132. | BR_V) /* valid */
  133. #define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
  134. | OR_UPM_XAM \
  135. | OR_GPCM_CSNT \
  136. | OR_GPCM_ACS_DIV2 \
  137. | OR_GPCM_XACS \
  138. | OR_GPCM_SCY_15 \
  139. | OR_GPCM_TRLX_SET \
  140. | OR_GPCM_EHTR_SET \
  141. | OR_GPCM_EAD)
  142. /* window base at flash base */
  143. #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
  144. #define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_32MB)
  145. #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
  146. #define CONFIG_SYS_MAX_FLASH_SECT 256 /* max sectors per device */
  147. #undef CONFIG_SYS_FLASH_CHECKSUM
  148. #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
  149. #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
  150. #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
  151. #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
  152. #define CONFIG_SYS_RAMBOOT
  153. #else
  154. #undef CONFIG_SYS_RAMBOOT
  155. #endif
  156. /*
  157. * BCSR register on local bus 32KB, 8-bit wide for MDS config reg
  158. */
  159. #define CONFIG_SYS_BCSR 0xE2400000
  160. /* Access window base at BCSR base */
  161. #define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_BCSR
  162. #define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_32KB)
  163. #define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_BCSR \
  164. | BR_PS_8 \
  165. | BR_MS_GPCM \
  166. | BR_V)
  167. /* 0x00000801 */
  168. #define CONFIG_SYS_OR1_PRELIM (OR_AM_32KB \
  169. | OR_GPCM_XAM \
  170. | OR_GPCM_CSNT \
  171. | OR_GPCM_SCY_15 \
  172. | OR_GPCM_TRLX_CLEAR \
  173. | OR_GPCM_EHTR_CLEAR)
  174. /* 0xFFFFE8F0 */
  175. #define CONFIG_SYS_INIT_RAM_LOCK 1
  176. #define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000 /* Initial RAM addr */
  177. #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM*/
  178. #define CONFIG_SYS_GBL_DATA_OFFSET \
  179. (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
  180. #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
  181. #define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */
  182. #define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Reserved for malloc */
  183. /*
  184. * Local Bus LCRR and LBCR regs
  185. * LCRR: DLL bypass, Clock divider is 4
  186. * External Local Bus rate is
  187. * CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV
  188. */
  189. #define CONFIG_SYS_LCRR_DBYP LCRR_DBYP
  190. #define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4
  191. #define CONFIG_SYS_LBC_LBCR 0x00000000
  192. /*
  193. * The MPC834xEA MDS for 834xE rev3.1 may not be assembled SDRAM memory.
  194. * if board has SRDAM on local bus, you can define CONFIG_SYS_LB_SDRAM
  195. */
  196. #undef CONFIG_SYS_LB_SDRAM
  197. #ifdef CONFIG_SYS_LB_SDRAM
  198. /* Local bus BR2, OR2 definition for SDRAM if soldered on the MDS board */
  199. /*
  200. * Base Register 2 and Option Register 2 configure SDRAM.
  201. * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000.
  202. *
  203. * For BR2, need:
  204. * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0
  205. * port-size = 32-bits = BR2[19:20] = 11
  206. * no parity checking = BR2[21:22] = 00
  207. * SDRAM for MSEL = BR2[24:26] = 011
  208. * Valid = BR[31] = 1
  209. *
  210. * 0 4 8 12 16 20 24 28
  211. * 1111 0000 0000 0000 0001 1000 0110 0001 = F0001861
  212. */
  213. #define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_LBC_SDRAM_BASE \
  214. | BR_PS_32 /* 32-bit port */ \
  215. | BR_MS_SDRAM /* MSEL = SDRAM */ \
  216. | BR_V) /* Valid */
  217. /* 0xF0001861 */
  218. #define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_LBC_SDRAM_BASE
  219. #define CONFIG_SYS_LBLAWAR2_PRELIM (LBLAWAR_EN | LBLAWAR_64MB)
  220. /*
  221. * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64.
  222. *
  223. * For OR2, need:
  224. * 64MB mask for AM, OR2[0:7] = 1111 1100
  225. * XAM, OR2[17:18] = 11
  226. * 9 columns OR2[19-21] = 010
  227. * 13 rows OR2[23-25] = 100
  228. * EAD set for extra time OR[31] = 1
  229. *
  230. * 0 4 8 12 16 20 24 28
  231. * 1111 1100 0000 0000 0110 1001 0000 0001 = FC006901
  232. */
  233. #define CONFIG_SYS_OR2_PRELIM (OR_AM_64MB \
  234. | OR_SDRAM_XAM \
  235. | ((9 - OR_SDRAM_MIN_COLS) << OR_SDRAM_COLS_SHIFT) \
  236. | ((13 - OR_SDRAM_MIN_ROWS) << OR_SDRAM_ROWS_SHIFT) \
  237. | OR_SDRAM_EAD)
  238. /* 0xFC006901 */
  239. /* LB sdram refresh timer, about 6us */
  240. #define CONFIG_SYS_LBC_LSRT 0x32000000
  241. /* LB refresh timer prescal, 266MHz/32 */
  242. #define CONFIG_SYS_LBC_MRTPR 0x20000000
  243. #define CONFIG_SYS_LBC_LSDMR_COMMON (LSDMR_RFEN \
  244. | LSDMR_BSMA1516 \
  245. | LSDMR_RFCR8 \
  246. | LSDMR_PRETOACT6 \
  247. | LSDMR_ACTTORW3 \
  248. | LSDMR_BL8 \
  249. | LSDMR_WRC3 \
  250. | LSDMR_CL3)
  251. /*
  252. * SDRAM Controller configuration sequence.
  253. */
  254. #define CONFIG_SYS_LBC_LSDMR_1 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_PCHALL)
  255. #define CONFIG_SYS_LBC_LSDMR_2 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH)
  256. #define CONFIG_SYS_LBC_LSDMR_3 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH)
  257. #define CONFIG_SYS_LBC_LSDMR_4 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_MRW)
  258. #define CONFIG_SYS_LBC_LSDMR_5 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_NORMAL)
  259. #endif
  260. /*
  261. * Serial Port
  262. */
  263. #define CONFIG_SYS_NS16550_SERIAL
  264. #define CONFIG_SYS_NS16550_REG_SIZE 1
  265. #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
  266. #define CONFIG_SYS_BAUDRATE_TABLE \
  267. {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
  268. #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
  269. #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
  270. /* I2C */
  271. #define CONFIG_SYS_I2C
  272. #define CONFIG_SYS_I2C_FSL
  273. #define CONFIG_SYS_FSL_I2C_SPEED 400000
  274. #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
  275. #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
  276. #define CONFIG_SYS_FSL_I2C2_SPEED 400000
  277. #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
  278. #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
  279. #define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} }
  280. /* SPI */
  281. #undef CONFIG_SOFT_SPI /* SPI bit-banged */
  282. /* GPIOs. Used as SPI chip selects */
  283. #define CONFIG_SYS_GPIO1_PRELIM
  284. #define CONFIG_SYS_GPIO1_DIR 0xC0000000 /* SPI CS on 0, LED on 1 */
  285. #define CONFIG_SYS_GPIO1_DAT 0xC0000000 /* Both are active LOW */
  286. /* TSEC */
  287. #define CONFIG_SYS_TSEC1_OFFSET 0x24000
  288. #define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET)
  289. #define CONFIG_SYS_TSEC2_OFFSET 0x25000
  290. #define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET)
  291. /* USB */
  292. #define CONFIG_SYS_USE_MPC834XSYS_USB_PHY 1 /* Use SYS board PHY */
  293. /*
  294. * General PCI
  295. * Addresses are mapped 1-1.
  296. */
  297. #define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
  298. #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
  299. #define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */
  300. #define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000
  301. #define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE
  302. #define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */
  303. #define CONFIG_SYS_PCI1_IO_BASE 0x00000000
  304. #define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000
  305. #define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */
  306. #define CONFIG_SYS_PCI2_MEM_BASE 0xA0000000
  307. #define CONFIG_SYS_PCI2_MEM_PHYS CONFIG_SYS_PCI2_MEM_BASE
  308. #define CONFIG_SYS_PCI2_MEM_SIZE 0x10000000 /* 256M */
  309. #define CONFIG_SYS_PCI2_MMIO_BASE 0xB0000000
  310. #define CONFIG_SYS_PCI2_MMIO_PHYS CONFIG_SYS_PCI2_MMIO_BASE
  311. #define CONFIG_SYS_PCI2_MMIO_SIZE 0x10000000 /* 256M */
  312. #define CONFIG_SYS_PCI2_IO_BASE 0x00000000
  313. #define CONFIG_SYS_PCI2_IO_PHYS 0xE2100000
  314. #define CONFIG_SYS_PCI2_IO_SIZE 0x00100000 /* 1M */
  315. #if defined(CONFIG_PCI)
  316. #define PCI_ONE_PCI1
  317. #if defined(PCI_64BIT)
  318. #undef PCI_ALL_PCI1
  319. #undef PCI_TWO_PCI1
  320. #undef PCI_ONE_PCI1
  321. #endif
  322. #define CONFIG_83XX_PCI_STREAMING
  323. #undef CONFIG_EEPRO100
  324. #undef CONFIG_TULIP
  325. #if !defined(CONFIG_PCI_PNP)
  326. #define PCI_ENET0_IOADDR 0xFIXME
  327. #define PCI_ENET0_MEMADDR 0xFIXME
  328. #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */
  329. #endif
  330. #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
  331. #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */
  332. #endif /* CONFIG_PCI */
  333. /*
  334. * TSEC configuration
  335. */
  336. #if defined(CONFIG_TSEC_ENET)
  337. #define CONFIG_GMII 1 /* MII PHY management */
  338. #define CONFIG_TSEC1 1
  339. #define CONFIG_TSEC1_NAME "TSEC0"
  340. #define CONFIG_TSEC2 1
  341. #define CONFIG_TSEC2_NAME "TSEC1"
  342. #define TSEC1_PHY_ADDR 0
  343. #define TSEC2_PHY_ADDR 1
  344. #define TSEC1_PHYIDX 0
  345. #define TSEC2_PHYIDX 0
  346. #define TSEC1_FLAGS TSEC_GIGABIT
  347. #define TSEC2_FLAGS TSEC_GIGABIT
  348. /* Options are: TSEC[0-1] */
  349. #define CONFIG_ETHPRIME "TSEC0"
  350. #endif /* CONFIG_TSEC_ENET */
  351. /*
  352. * Configure on-board RTC
  353. */
  354. #define CONFIG_RTC_DS1374 /* use ds1374 rtc via i2c */
  355. #define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */
  356. /*
  357. * Environment
  358. */
  359. #ifndef CONFIG_SYS_RAMBOOT
  360. #define CONFIG_ENV_ADDR \
  361. (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
  362. #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */
  363. #define CONFIG_ENV_SIZE 0x2000
  364. /* Address and size of Redundant Environment Sector */
  365. #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
  366. #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
  367. #else
  368. #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
  369. #define CONFIG_ENV_SIZE 0x2000
  370. #endif
  371. #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
  372. #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
  373. /*
  374. * BOOTP options
  375. */
  376. #define CONFIG_BOOTP_BOOTFILESIZE
  377. /*
  378. * Command line configuration.
  379. */
  380. #undef CONFIG_WATCHDOG /* watchdog disabled */
  381. /*
  382. * Miscellaneous configurable options
  383. */
  384. #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
  385. /*
  386. * For booting Linux, the board info and command line data
  387. * have to be in the first 256 MB of memory, since this is
  388. * the maximum mapped by the Linux kernel during initialization.
  389. */
  390. /* Initial Memory map for Linux*/
  391. #define CONFIG_SYS_BOOTMAPSZ (256 << 20)
  392. #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
  393. #define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST */
  394. #if 1 /*528/264*/
  395. #define CONFIG_SYS_HRCW_LOW (\
  396. HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
  397. HRCWL_DDR_TO_SCB_CLK_1X1 |\
  398. HRCWL_CSB_TO_CLKIN |\
  399. HRCWL_VCO_1X2 |\
  400. HRCWL_CORE_TO_CSB_2X1)
  401. #elif 0 /*396/132*/
  402. #define CONFIG_SYS_HRCW_LOW (\
  403. HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
  404. HRCWL_DDR_TO_SCB_CLK_1X1 |\
  405. HRCWL_CSB_TO_CLKIN |\
  406. HRCWL_VCO_1X4 |\
  407. HRCWL_CORE_TO_CSB_3X1)
  408. #elif 0 /*264/132*/
  409. #define CONFIG_SYS_HRCW_LOW (\
  410. HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
  411. HRCWL_DDR_TO_SCB_CLK_1X1 |\
  412. HRCWL_CSB_TO_CLKIN |\
  413. HRCWL_VCO_1X4 |\
  414. HRCWL_CORE_TO_CSB_2X1)
  415. #elif 0 /*132/132*/
  416. #define CONFIG_SYS_HRCW_LOW (\
  417. HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
  418. HRCWL_DDR_TO_SCB_CLK_1X1 |\
  419. HRCWL_CSB_TO_CLKIN |\
  420. HRCWL_VCO_1X4 |\
  421. HRCWL_CORE_TO_CSB_1X1)
  422. #elif 0 /*264/264 */
  423. #define CONFIG_SYS_HRCW_LOW (\
  424. HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
  425. HRCWL_DDR_TO_SCB_CLK_1X1 |\
  426. HRCWL_CSB_TO_CLKIN |\
  427. HRCWL_VCO_1X4 |\
  428. HRCWL_CORE_TO_CSB_1X1)
  429. #endif
  430. #ifdef CONFIG_PCISLAVE
  431. #define CONFIG_SYS_HRCW_HIGH (\
  432. HRCWH_PCI_AGENT |\
  433. HRCWH_64_BIT_PCI |\
  434. HRCWH_PCI1_ARBITER_DISABLE |\
  435. HRCWH_PCI2_ARBITER_DISABLE |\
  436. HRCWH_CORE_ENABLE |\
  437. HRCWH_FROM_0X00000100 |\
  438. HRCWH_BOOTSEQ_DISABLE |\
  439. HRCWH_SW_WATCHDOG_DISABLE |\
  440. HRCWH_ROM_LOC_LOCAL_16BIT |\
  441. HRCWH_TSEC1M_IN_GMII |\
  442. HRCWH_TSEC2M_IN_GMII)
  443. #else
  444. #if defined(PCI_64BIT)
  445. #define CONFIG_SYS_HRCW_HIGH (\
  446. HRCWH_PCI_HOST |\
  447. HRCWH_64_BIT_PCI |\
  448. HRCWH_PCI1_ARBITER_ENABLE |\
  449. HRCWH_PCI2_ARBITER_DISABLE |\
  450. HRCWH_CORE_ENABLE |\
  451. HRCWH_FROM_0X00000100 |\
  452. HRCWH_BOOTSEQ_DISABLE |\
  453. HRCWH_SW_WATCHDOG_DISABLE |\
  454. HRCWH_ROM_LOC_LOCAL_16BIT |\
  455. HRCWH_TSEC1M_IN_GMII |\
  456. HRCWH_TSEC2M_IN_GMII)
  457. #else
  458. #define CONFIG_SYS_HRCW_HIGH (\
  459. HRCWH_PCI_HOST |\
  460. HRCWH_32_BIT_PCI |\
  461. HRCWH_PCI1_ARBITER_ENABLE |\
  462. HRCWH_PCI2_ARBITER_ENABLE |\
  463. HRCWH_CORE_ENABLE |\
  464. HRCWH_FROM_0X00000100 |\
  465. HRCWH_BOOTSEQ_DISABLE |\
  466. HRCWH_SW_WATCHDOG_DISABLE |\
  467. HRCWH_ROM_LOC_LOCAL_16BIT |\
  468. HRCWH_TSEC1M_IN_GMII |\
  469. HRCWH_TSEC2M_IN_GMII)
  470. #endif /* PCI_64BIT */
  471. #endif /* CONFIG_PCISLAVE */
  472. /*
  473. * System performance
  474. */
  475. #define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */
  476. #define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */
  477. #define CONFIG_SYS_SPCR_TSEC1EP 3 /* TSEC1 emergency priority (0-3) */
  478. #define CONFIG_SYS_SPCR_TSEC2EP 3 /* TSEC2 emergency priority (0-3) */
  479. #define CONFIG_SYS_SCCR_TSEC1CM 1 /* TSEC1 clock mode (0-3) */
  480. #define CONFIG_SYS_SCCR_TSEC2CM 1 /* TSEC2 & I2C0 clock mode (0-3) */
  481. /* System IO Config */
  482. #define CONFIG_SYS_SICRH 0
  483. #define CONFIG_SYS_SICRL SICRL_LDP_A
  484. #define CONFIG_SYS_HID0_INIT 0x000000000
  485. #define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK \
  486. | HID0_ENABLE_INSTRUCTION_CACHE)
  487. /* #define CONFIG_SYS_HID0_FINAL (\
  488. HID0_ENABLE_INSTRUCTION_CACHE |\
  489. HID0_ENABLE_M_BIT |\
  490. HID0_ENABLE_ADDRESS_BROADCAST) */
  491. #define CONFIG_SYS_HID2 HID2_HBE
  492. #define CONFIG_HIGH_BATS 1 /* High BATs supported */
  493. /* DDR @ 0x00000000 */
  494. #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE \
  495. | BATL_PP_RW \
  496. | BATL_MEMCOHERENCE)
  497. #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \
  498. | BATU_BL_256M \
  499. | BATU_VS \
  500. | BATU_VP)
  501. /* PCI @ 0x80000000 */
  502. #ifdef CONFIG_PCI
  503. #define CONFIG_PCI_INDIRECT_BRIDGE
  504. #define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_BASE \
  505. | BATL_PP_RW \
  506. | BATL_MEMCOHERENCE)
  507. #define CONFIG_SYS_IBAT1U (CONFIG_SYS_PCI1_MEM_BASE \
  508. | BATU_BL_256M \
  509. | BATU_VS \
  510. | BATU_VP)
  511. #define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MMIO_BASE \
  512. | BATL_PP_RW \
  513. | BATL_CACHEINHIBIT \
  514. | BATL_GUARDEDSTORAGE)
  515. #define CONFIG_SYS_IBAT2U (CONFIG_SYS_PCI1_MMIO_BASE \
  516. | BATU_BL_256M \
  517. | BATU_VS \
  518. | BATU_VP)
  519. #else
  520. #define CONFIG_SYS_IBAT1L (0)
  521. #define CONFIG_SYS_IBAT1U (0)
  522. #define CONFIG_SYS_IBAT2L (0)
  523. #define CONFIG_SYS_IBAT2U (0)
  524. #endif
  525. #ifdef CONFIG_MPC83XX_PCI2
  526. #define CONFIG_SYS_IBAT3L (CONFIG_SYS_PCI2_MEM_BASE \
  527. | BATL_PP_RW \
  528. | BATL_MEMCOHERENCE)
  529. #define CONFIG_SYS_IBAT3U (CONFIG_SYS_PCI2_MEM_BASE \
  530. | BATU_BL_256M \
  531. | BATU_VS \
  532. | BATU_VP)
  533. #define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCI2_MMIO_BASE \
  534. | BATL_PP_RW \
  535. | BATL_CACHEINHIBIT \
  536. | BATL_GUARDEDSTORAGE)
  537. #define CONFIG_SYS_IBAT4U (CONFIG_SYS_PCI2_MMIO_BASE \
  538. | BATU_BL_256M \
  539. | BATU_VS \
  540. | BATU_VP)
  541. #else
  542. #define CONFIG_SYS_IBAT3L (0)
  543. #define CONFIG_SYS_IBAT3U (0)
  544. #define CONFIG_SYS_IBAT4L (0)
  545. #define CONFIG_SYS_IBAT4U (0)
  546. #endif
  547. /* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000 */
  548. #define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR \
  549. | BATL_PP_RW \
  550. | BATL_CACHEINHIBIT \
  551. | BATL_GUARDEDSTORAGE)
  552. #define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR \
  553. | BATU_BL_256M \
  554. | BATU_VS \
  555. | BATU_VP)
  556. /* SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */
  557. #define CONFIG_SYS_IBAT6L (0xF0000000 \
  558. | BATL_PP_RW \
  559. | BATL_MEMCOHERENCE \
  560. | BATL_GUARDEDSTORAGE)
  561. #define CONFIG_SYS_IBAT6U (0xF0000000 \
  562. | BATU_BL_256M \
  563. | BATU_VS \
  564. | BATU_VP)
  565. #define CONFIG_SYS_IBAT7L (0)
  566. #define CONFIG_SYS_IBAT7U (0)
  567. #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
  568. #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
  569. #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
  570. #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
  571. #define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L
  572. #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
  573. #define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
  574. #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
  575. #define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L
  576. #define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U
  577. #define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L
  578. #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
  579. #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
  580. #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
  581. #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
  582. #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
  583. #if defined(CONFIG_CMD_KGDB)
  584. #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
  585. #endif
  586. /*
  587. * Environment Configuration
  588. */
  589. #define CONFIG_ENV_OVERWRITE
  590. #if defined(CONFIG_TSEC_ENET)
  591. #define CONFIG_HAS_ETH1
  592. #define CONFIG_HAS_ETH0
  593. #endif
  594. #define CONFIG_HOSTNAME "mpc8349emds"
  595. #define CONFIG_ROOTPATH "/nfsroot/rootfs"
  596. #define CONFIG_BOOTFILE "uImage"
  597. #define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */
  598. #define CONFIG_PREBOOT "echo;" \
  599. "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
  600. "echo"
  601. #define CONFIG_EXTRA_ENV_SETTINGS \
  602. "netdev=eth0\0" \
  603. "hostname=mpc8349emds\0" \
  604. "nfsargs=setenv bootargs root=/dev/nfs rw " \
  605. "nfsroot=${serverip}:${rootpath}\0" \
  606. "ramargs=setenv bootargs root=/dev/ram rw\0" \
  607. "addip=setenv bootargs ${bootargs} " \
  608. "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
  609. ":${hostname}:${netdev}:off panic=1\0" \
  610. "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
  611. "flash_nfs=run nfsargs addip addtty;" \
  612. "bootm ${kernel_addr}\0" \
  613. "flash_self=run ramargs addip addtty;" \
  614. "bootm ${kernel_addr} ${ramdisk_addr}\0" \
  615. "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \
  616. "bootm\0" \
  617. "load=tftp 100000 /tftpboot/mpc8349emds/u-boot.bin\0" \
  618. "update=protect off fe000000 fe03ffff; " \
  619. "era fe000000 fe03ffff; cp.b 100000 fe000000 ${filesize}\0"\
  620. "upd=run load update\0" \
  621. "fdtaddr=780000\0" \
  622. "fdtfile=mpc834x_mds.dtb\0" \
  623. ""
  624. #define CONFIG_NFSBOOTCOMMAND \
  625. "setenv bootargs root=/dev/nfs rw " \
  626. "nfsroot=$serverip:$rootpath " \
  627. "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:" \
  628. "$netdev:off " \
  629. "console=$consoledev,$baudrate $othbootargs;" \
  630. "tftp $loadaddr $bootfile;" \
  631. "tftp $fdtaddr $fdtfile;" \
  632. "bootm $loadaddr - $fdtaddr"
  633. #define CONFIG_RAMBOOTCOMMAND \
  634. "setenv bootargs root=/dev/ram rw " \
  635. "console=$consoledev,$baudrate $othbootargs;" \
  636. "tftp $ramdiskaddr $ramdiskfile;" \
  637. "tftp $loadaddr $bootfile;" \
  638. "tftp $fdtaddr $fdtfile;" \
  639. "bootm $loadaddr $ramdiskaddr $fdtaddr"
  640. #define CONFIG_BOOTCOMMAND "run flash_self"
  641. #endif /* __CONFIG_H */