immap_83xx.h 28 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright 2004-2011 Freescale Semiconductor, Inc.
  4. *
  5. * MPC83xx Internal Memory Map
  6. *
  7. * Contributors:
  8. * Dave Liu <daveliu@freescale.com>
  9. * Tanya Jiang <tanya.jiang@freescale.com>
  10. * Mandy Lavi <mandy.lavi@freescale.com>
  11. * Eran Liberty <liberty@freescale.com>
  12. */
  13. #ifndef __IMMAP_83xx__
  14. #define __IMMAP_83xx__
  15. #include <fsl_immap.h>
  16. #include <asm/types.h>
  17. #include <asm/fsl_i2c.h>
  18. #include <asm/mpc8xxx_spi.h>
  19. #include <asm/fsl_lbc.h>
  20. #include <asm/fsl_dma.h>
  21. /*
  22. * Local Access Window
  23. */
  24. typedef struct law83xx {
  25. u32 bar; /* LBIU local access window base address register */
  26. u32 ar; /* LBIU local access window attribute register */
  27. } law83xx_t;
  28. /*
  29. * System configuration registers
  30. */
  31. typedef struct sysconf83xx {
  32. u32 immrbar; /* Internal memory map base address register */
  33. u8 res0[0x04];
  34. u32 altcbar; /* Alternate configuration base address register */
  35. u8 res1[0x14];
  36. law83xx_t lblaw[4]; /* LBIU local access window */
  37. u8 res2[0x20];
  38. law83xx_t pcilaw[2]; /* PCI local access window */
  39. u8 res3[0x10];
  40. law83xx_t pcielaw[2]; /* PCI Express local access window */
  41. u8 res4[0x10];
  42. law83xx_t ddrlaw[2]; /* DDR local access window */
  43. u8 res5[0x50];
  44. u32 sgprl; /* System General Purpose Register Low */
  45. u32 sgprh; /* System General Purpose Register High */
  46. u32 spridr; /* System Part and Revision ID Register */
  47. u8 res6[0x04];
  48. u32 spcr; /* System Priority Configuration Register */
  49. u32 sicrl; /* System I/O Configuration Register Low */
  50. u32 sicrh; /* System I/O Configuration Register High */
  51. u8 res7[0x04];
  52. u32 sidcr0; /* System I/O Delay Configuration Register 0 */
  53. u32 sidcr1; /* System I/O Delay Configuration Register 1 */
  54. u32 ddrcdr; /* DDR Control Driver Register */
  55. u32 ddrdsr; /* DDR Debug Status Register */
  56. u32 obir; /* Output Buffer Impedance Register */
  57. u8 res8[0xC];
  58. u32 pecr1; /* PCI Express control register 1 */
  59. #if defined(CONFIG_ARCH_MPC830X)
  60. u32 sdhccr; /* eSDHC Control Registers for MPC830x */
  61. #else
  62. u32 pecr2; /* PCI Express control register 2 */
  63. #endif
  64. #if defined(CONFIG_ARCH_MPC8309)
  65. u32 can_dbg_ctrl;
  66. u32 res9a;
  67. u32 gpr1;
  68. u8 res9b[0xAC];
  69. #else
  70. u8 res9[0xB8];
  71. #endif
  72. } sysconf83xx_t;
  73. /*
  74. * Watch Dog Timer (WDT) Registers
  75. */
  76. typedef struct wdt83xx {
  77. u8 res0[4];
  78. u32 swcrr; /* System watchdog control register */
  79. u32 swcnr; /* System watchdog count register */
  80. u8 res1[2];
  81. u16 swsrr; /* System watchdog service register */
  82. u8 res2[0xF0];
  83. } wdt83xx_t;
  84. /*
  85. * RTC/PIT Module Registers
  86. */
  87. typedef struct rtclk83xx {
  88. u32 cnr; /* control register */
  89. u32 ldr; /* load register */
  90. u32 psr; /* prescale register */
  91. u32 ctr; /* counter value field register */
  92. u32 evr; /* event register */
  93. u32 alr; /* alarm register */
  94. u8 res0[0xE8];
  95. } rtclk83xx_t;
  96. /*
  97. * Global timer module
  98. */
  99. typedef struct gtm83xx {
  100. u8 cfr1; /* Timer1/2 Configuration */
  101. u8 res0[3];
  102. u8 cfr2; /* Timer3/4 Configuration */
  103. u8 res1[11];
  104. u16 mdr1; /* Timer1 Mode Register */
  105. u16 mdr2; /* Timer2 Mode Register */
  106. u16 rfr1; /* Timer1 Reference Register */
  107. u16 rfr2; /* Timer2 Reference Register */
  108. u16 cpr1; /* Timer1 Capture Register */
  109. u16 cpr2; /* Timer2 Capture Register */
  110. u16 cnr1; /* Timer1 Counter Register */
  111. u16 cnr2; /* Timer2 Counter Register */
  112. u16 mdr3; /* Timer3 Mode Register */
  113. u16 mdr4; /* Timer4 Mode Register */
  114. u16 rfr3; /* Timer3 Reference Register */
  115. u16 rfr4; /* Timer4 Reference Register */
  116. u16 cpr3; /* Timer3 Capture Register */
  117. u16 cpr4; /* Timer4 Capture Register */
  118. u16 cnr3; /* Timer3 Counter Register */
  119. u16 cnr4; /* Timer4 Counter Register */
  120. u16 evr1; /* Timer1 Event Register */
  121. u16 evr2; /* Timer2 Event Register */
  122. u16 evr3; /* Timer3 Event Register */
  123. u16 evr4; /* Timer4 Event Register */
  124. u16 psr1; /* Timer1 Prescaler Register */
  125. u16 psr2; /* Timer2 Prescaler Register */
  126. u16 psr3; /* Timer3 Prescaler Register */
  127. u16 psr4; /* Timer4 Prescaler Register */
  128. u8 res[0xC0];
  129. } gtm83xx_t;
  130. /*
  131. * Integrated Programmable Interrupt Controller
  132. */
  133. typedef struct ipic83xx {
  134. u32 sicfr; /* System Global Interrupt Configuration Register */
  135. u32 sivcr; /* System Global Interrupt Vector Register */
  136. u32 sipnr_h; /* System Internal Interrupt Pending Register - High */
  137. u32 sipnr_l; /* System Internal Interrupt Pending Register - Low */
  138. u32 siprr_a; /* System Internal Interrupt Group A Priority Register */
  139. u32 siprr_b; /* System Internal Interrupt Group B Priority Register */
  140. u32 siprr_c; /* System Internal Interrupt Group C Priority Register */
  141. u32 siprr_d; /* System Internal Interrupt Group D Priority Register */
  142. u32 simsr_h; /* System Internal Interrupt Mask Register - High */
  143. u32 simsr_l; /* System Internal Interrupt Mask Register - Low */
  144. u32 sicnr; /* System Internal Interrupt Control Register */
  145. u32 sepnr; /* System External Interrupt Pending Register */
  146. u32 smprr_a; /* System Mixed Interrupt Group A Priority Register */
  147. u32 smprr_b; /* System Mixed Interrupt Group B Priority Register */
  148. u32 semsr; /* System External Interrupt Mask Register */
  149. u32 secnr; /* System External Interrupt Control Register */
  150. u32 sersr; /* System Error Status Register */
  151. u32 sermr; /* System Error Mask Register */
  152. u32 sercr; /* System Error Control Register */
  153. u32 sepcr; /* System External Interrupt Polarity Control Register */
  154. u32 sifcr_h; /* System Internal Interrupt Force Register - High */
  155. u32 sifcr_l; /* System Internal Interrupt Force Register - Low */
  156. u32 sefcr; /* System External Interrupt Force Register */
  157. u32 serfr; /* System Error Force Register */
  158. u32 scvcr; /* System Critical Interrupt Vector Register */
  159. u32 smvcr; /* System Management Interrupt Vector Register */
  160. u8 res[0x98];
  161. } ipic83xx_t;
  162. /*
  163. * System Arbiter Registers
  164. */
  165. typedef struct arbiter83xx {
  166. u32 acr; /* Arbiter Configuration Register */
  167. u32 atr; /* Arbiter Timers Register */
  168. u8 res[4];
  169. u32 aer; /* Arbiter Event Register */
  170. u32 aidr; /* Arbiter Interrupt Definition Register */
  171. u32 amr; /* Arbiter Mask Register */
  172. u32 aeatr; /* Arbiter Event Attributes Register */
  173. u32 aeadr; /* Arbiter Event Address Register */
  174. u32 aerr; /* Arbiter Event Response Register */
  175. u8 res1[0xDC];
  176. } arbiter83xx_t;
  177. /*
  178. * Reset Module
  179. */
  180. typedef struct reset83xx {
  181. u32 rcwl; /* Reset Configuration Word Low Register */
  182. u32 rcwh; /* Reset Configuration Word High Register */
  183. u8 res0[8];
  184. u32 rsr; /* Reset Status Register */
  185. u32 rmr; /* Reset Mode Register */
  186. u32 rpr; /* Reset protection Register */
  187. u32 rcr; /* Reset Control Register */
  188. u32 rcer; /* Reset Control Enable Register */
  189. u8 res1[0xDC];
  190. } reset83xx_t;
  191. /*
  192. * Clock Module
  193. */
  194. typedef struct clk83xx {
  195. u32 spmr; /* system PLL mode Register */
  196. u32 occr; /* output clock control Register */
  197. u32 sccr; /* system clock control Register */
  198. u8 res0[0xF4];
  199. } clk83xx_t;
  200. /*
  201. * Power Management Control Module
  202. */
  203. typedef struct pmc83xx {
  204. u32 pmccr; /* PMC Configuration Register */
  205. u32 pmcer; /* PMC Event Register */
  206. u32 pmcmr; /* PMC Mask Register */
  207. u32 pmccr1; /* PMC Configuration Register 1 */
  208. u32 pmccr2; /* PMC Configuration Register 2 */
  209. u8 res0[0xEC];
  210. } pmc83xx_t;
  211. /*
  212. * General purpose I/O module
  213. */
  214. typedef struct gpio83xx {
  215. u32 dir; /* direction register */
  216. u32 odr; /* open drain register */
  217. u32 dat; /* data register */
  218. u32 ier; /* interrupt event register */
  219. u32 imr; /* interrupt mask register */
  220. u32 icr; /* external interrupt control register */
  221. u8 res0[0xE8];
  222. } gpio83xx_t;
  223. /*
  224. * QE Ports Interrupts Registers
  225. */
  226. typedef struct qepi83xx {
  227. u8 res0[0xC];
  228. u32 qepier; /* QE Ports Interrupt Event Register */
  229. u32 qepimr; /* QE Ports Interrupt Mask Register */
  230. u32 qepicr; /* QE Ports Interrupt Control Register */
  231. u8 res1[0xE8];
  232. } qepi83xx_t;
  233. /*
  234. * QE Parallel I/O Ports
  235. */
  236. typedef struct gpio_n {
  237. u32 podr; /* Open Drain Register */
  238. u32 pdat; /* Data Register */
  239. u32 dir1; /* direction register 1 */
  240. u32 dir2; /* direction register 2 */
  241. u32 ppar1; /* Pin Assignment Register 1 */
  242. u32 ppar2; /* Pin Assignment Register 2 */
  243. } gpio_n_t;
  244. typedef struct qegpio83xx {
  245. gpio_n_t ioport[0x7];
  246. u8 res0[0x358];
  247. } qepio83xx_t;
  248. /*
  249. * QE Secondary Bus Access Windows
  250. */
  251. typedef struct qesba83xx {
  252. u32 lbmcsar; /* Local bus memory controller start address */
  253. u32 sdmcsar; /* Secondary DDR memory controller start address */
  254. u8 res0[0x38];
  255. u32 lbmcear; /* Local bus memory controller end address */
  256. u32 sdmcear; /* Secondary DDR memory controller end address */
  257. u8 res1[0x38];
  258. u32 lbmcar; /* Local bus memory controller attributes */
  259. u32 sdmcar; /* Secondary DDR memory controller attributes */
  260. u8 res2[0x378];
  261. } qesba83xx_t;
  262. /*
  263. * DDR Memory Controller Memory Map for DDR1
  264. * The structure of DDR2, or DDR3 is defined in fsl_immap.h
  265. */
  266. #if !defined(CONFIG_SYS_FSL_DDR2) && !defined(CONFIG_SYS_FSL_DDR3)
  267. typedef struct ddr_cs_bnds {
  268. u32 csbnds;
  269. u8 res0[4];
  270. } ddr_cs_bnds_t;
  271. typedef struct ddr83xx {
  272. ddr_cs_bnds_t csbnds[4];/* Chip Select x Memory Bounds */
  273. u8 res0[0x60];
  274. u32 cs_config[4]; /* Chip Select x Configuration */
  275. u8 res1[0x70];
  276. u32 timing_cfg_3; /* SDRAM Timing Configuration 3 */
  277. u32 timing_cfg_0; /* SDRAM Timing Configuration 0 */
  278. u32 timing_cfg_1; /* SDRAM Timing Configuration 1 */
  279. u32 timing_cfg_2; /* SDRAM Timing Configuration 2 */
  280. u32 sdram_cfg; /* SDRAM Control Configuration */
  281. u32 sdram_cfg2; /* SDRAM Control Configuration 2 */
  282. u32 sdram_mode; /* SDRAM Mode Configuration */
  283. u32 sdram_mode2; /* SDRAM Mode Configuration 2 */
  284. u32 sdram_md_cntl; /* SDRAM Mode Control */
  285. u32 sdram_interval; /* SDRAM Interval Configuration */
  286. u32 ddr_data_init; /* SDRAM Data Initialization */
  287. u8 res2[4];
  288. u32 sdram_clk_cntl; /* SDRAM Clock Control */
  289. u8 res3[0x14];
  290. u32 ddr_init_addr; /* DDR training initialization address */
  291. u32 ddr_init_ext_addr; /* DDR training initialization extended address */
  292. u8 res4[0xAA8];
  293. u32 ddr_ip_rev1; /* DDR IP block revision 1 */
  294. u32 ddr_ip_rev2; /* DDR IP block revision 2 */
  295. u8 res5[0x200];
  296. u32 data_err_inject_hi; /* Memory Data Path Error Injection Mask High */
  297. u32 data_err_inject_lo; /* Memory Data Path Error Injection Mask Low */
  298. u32 ecc_err_inject; /* Memory Data Path Error Injection Mask ECC */
  299. u8 res6[0x14];
  300. u32 capture_data_hi; /* Memory Data Path Read Capture High */
  301. u32 capture_data_lo; /* Memory Data Path Read Capture Low */
  302. u32 capture_ecc; /* Memory Data Path Read Capture ECC */
  303. u8 res7[0x14];
  304. u32 err_detect; /* Memory Error Detect */
  305. u32 err_disable; /* Memory Error Disable */
  306. u32 err_int_en; /* Memory Error Interrupt Enable */
  307. u32 capture_attributes; /* Memory Error Attributes Capture */
  308. u32 capture_address; /* Memory Error Address Capture */
  309. u32 capture_ext_address;/* Memory Error Extended Address Capture */
  310. u32 err_sbe; /* Memory Single-Bit ECC Error Management */
  311. u8 res8[0xA4];
  312. u32 debug_reg;
  313. u8 res9[0xFC];
  314. } ddr83xx_t;
  315. #endif
  316. /*
  317. * DUART
  318. */
  319. typedef struct duart83xx {
  320. u8 urbr_ulcr_udlb; /* combined register for URBR, UTHR and UDLB */
  321. u8 uier_udmb; /* combined register for UIER and UDMB */
  322. u8 uiir_ufcr_uafr; /* combined register for UIIR, UFCR and UAFR */
  323. u8 ulcr; /* line control register */
  324. u8 umcr; /* MODEM control register */
  325. u8 ulsr; /* line status register */
  326. u8 umsr; /* MODEM status register */
  327. u8 uscr; /* scratch register */
  328. u8 res0[8];
  329. u8 udsr; /* DMA status register */
  330. u8 res1[3];
  331. u8 res2[0xEC];
  332. } duart83xx_t;
  333. /*
  334. * DMA/Messaging Unit
  335. */
  336. typedef struct dma83xx {
  337. u32 res0[0xC]; /* 0x0-0x29 reseverd */
  338. u32 omisr; /* 0x30 Outbound message interrupt status register */
  339. u32 omimr; /* 0x34 Outbound message interrupt mask register */
  340. u32 res1[0x6]; /* 0x38-0x49 reserved */
  341. u32 imr0; /* 0x50 Inbound message register 0 */
  342. u32 imr1; /* 0x54 Inbound message register 1 */
  343. u32 omr0; /* 0x58 Outbound message register 0 */
  344. u32 omr1; /* 0x5C Outbound message register 1 */
  345. u32 odr; /* 0x60 Outbound doorbell register */
  346. u32 res2; /* 0x64-0x67 reserved */
  347. u32 idr; /* 0x68 Inbound doorbell register */
  348. u32 res3[0x5]; /* 0x6C-0x79 reserved */
  349. u32 imisr; /* 0x80 Inbound message interrupt status register */
  350. u32 imimr; /* 0x84 Inbound message interrupt mask register */
  351. u32 res4[0x1E]; /* 0x88-0x99 reserved */
  352. struct fsl_dma dma[4];
  353. } dma83xx_t;
  354. /*
  355. * PCI Software Configuration Registers
  356. */
  357. typedef struct pciconf83xx {
  358. u32 config_address;
  359. u32 config_data;
  360. u32 int_ack;
  361. u8 res[116];
  362. } pciconf83xx_t;
  363. /*
  364. * PCI Outbound Translation Register
  365. */
  366. typedef struct pci_outbound_window {
  367. u32 potar;
  368. u8 res0[4];
  369. u32 pobar;
  370. u8 res1[4];
  371. u32 pocmr;
  372. u8 res2[4];
  373. } pot83xx_t;
  374. /*
  375. * Sequencer
  376. */
  377. typedef struct ios83xx {
  378. pot83xx_t pot[6];
  379. u8 res0[0x60];
  380. u32 pmcr;
  381. u8 res1[4];
  382. u32 dtcr;
  383. u8 res2[4];
  384. } ios83xx_t;
  385. /*
  386. * PCI Controller Control and Status Registers
  387. */
  388. typedef struct pcictrl83xx {
  389. u32 esr;
  390. u32 ecdr;
  391. u32 eer;
  392. u32 eatcr;
  393. u32 eacr;
  394. u32 eeacr;
  395. u32 edlcr;
  396. u32 edhcr;
  397. u32 gcr;
  398. u32 ecr;
  399. u32 gsr;
  400. u8 res0[12];
  401. u32 pitar2;
  402. u8 res1[4];
  403. u32 pibar2;
  404. u32 piebar2;
  405. u32 piwar2;
  406. u8 res2[4];
  407. u32 pitar1;
  408. u8 res3[4];
  409. u32 pibar1;
  410. u32 piebar1;
  411. u32 piwar1;
  412. u8 res4[4];
  413. u32 pitar0;
  414. u8 res5[4];
  415. u32 pibar0;
  416. u8 res6[4];
  417. u32 piwar0;
  418. u8 res7[132];
  419. } pcictrl83xx_t;
  420. /*
  421. * USB
  422. */
  423. typedef struct usb83xx {
  424. u8 fixme[0x1000];
  425. } usb83xx_t;
  426. /*
  427. * TSEC
  428. */
  429. typedef struct tsec83xx {
  430. u8 fixme[0x1000];
  431. } tsec83xx_t;
  432. /*
  433. * Security
  434. */
  435. typedef struct security83xx {
  436. u8 fixme[0x10000];
  437. } security83xx_t;
  438. /*
  439. * PCI Express
  440. */
  441. struct pex_inbound_window {
  442. u32 ar;
  443. u32 tar;
  444. u32 barl;
  445. u32 barh;
  446. };
  447. struct pex_outbound_window {
  448. u32 ar;
  449. u32 bar;
  450. u32 tarl;
  451. u32 tarh;
  452. };
  453. struct pex_csb_bridge {
  454. u32 pex_csb_ver;
  455. u32 pex_csb_cab;
  456. u32 pex_csb_ctrl;
  457. u8 res0[8];
  458. u32 pex_dms_dstmr;
  459. u8 res1[4];
  460. u32 pex_cbs_stat;
  461. u8 res2[0x20];
  462. u32 pex_csb_obctrl;
  463. u32 pex_csb_obstat;
  464. u8 res3[0x98];
  465. u32 pex_csb_ibctrl;
  466. u32 pex_csb_ibstat;
  467. u8 res4[0xb8];
  468. u32 pex_wdma_ctrl;
  469. u32 pex_wdma_addr;
  470. u32 pex_wdma_stat;
  471. u8 res5[0x94];
  472. u32 pex_rdma_ctrl;
  473. u32 pex_rdma_addr;
  474. u32 pex_rdma_stat;
  475. u8 res6[0xd4];
  476. u32 pex_ombcr;
  477. u32 pex_ombdr;
  478. u8 res7[0x38];
  479. u32 pex_imbcr;
  480. u32 pex_imbdr;
  481. u8 res8[0x38];
  482. u32 pex_int_enb;
  483. u32 pex_int_stat;
  484. u32 pex_int_apio_vec1;
  485. u32 pex_int_apio_vec2;
  486. u8 res9[0x10];
  487. u32 pex_int_ppio_vec1;
  488. u32 pex_int_ppio_vec2;
  489. u32 pex_int_wdma_vec1;
  490. u32 pex_int_wdma_vec2;
  491. u32 pex_int_rdma_vec1;
  492. u32 pex_int_rdma_vec2;
  493. u32 pex_int_misc_vec;
  494. u8 res10[4];
  495. u32 pex_int_axi_pio_enb;
  496. u32 pex_int_axi_wdma_enb;
  497. u32 pex_int_axi_rdma_enb;
  498. u32 pex_int_axi_misc_enb;
  499. u32 pex_int_axi_pio_stat;
  500. u32 pex_int_axi_wdma_stat;
  501. u32 pex_int_axi_rdma_stat;
  502. u32 pex_int_axi_misc_stat;
  503. u8 res11[0xa0];
  504. struct pex_outbound_window pex_outbound_win[4];
  505. u8 res12[0x100];
  506. u32 pex_epiwtar0;
  507. u32 pex_epiwtar1;
  508. u32 pex_epiwtar2;
  509. u32 pex_epiwtar3;
  510. u8 res13[0x70];
  511. struct pex_inbound_window pex_inbound_win[4];
  512. };
  513. typedef struct pex83xx {
  514. u8 pex_cfg_header[0x404];
  515. u32 pex_ltssm_stat;
  516. u8 res0[0x30];
  517. u32 pex_ack_replay_timeout;
  518. u8 res1[4];
  519. u32 pex_gclk_ratio;
  520. u8 res2[0xc];
  521. u32 pex_pm_timer;
  522. u32 pex_pme_timeout;
  523. u8 res3[4];
  524. u32 pex_aspm_req_timer;
  525. u8 res4[0x18];
  526. u32 pex_ssvid_update;
  527. u8 res5[0x34];
  528. u32 pex_cfg_ready;
  529. u8 res6[0x24];
  530. u32 pex_bar_sizel;
  531. u8 res7[4];
  532. u32 pex_bar_sel;
  533. u8 res8[0x20];
  534. u32 pex_bar_pf;
  535. u8 res9[0x88];
  536. u32 pex_pme_to_ack_tor;
  537. u8 res10[0xc];
  538. u32 pex_ss_intr_mask;
  539. u8 res11[0x25c];
  540. struct pex_csb_bridge bridge;
  541. u8 res12[0x160];
  542. } pex83xx_t;
  543. /*
  544. * SATA
  545. */
  546. typedef struct sata83xx {
  547. u8 fixme[0x1000];
  548. } sata83xx_t;
  549. /*
  550. * eSDHC
  551. */
  552. typedef struct sdhc83xx {
  553. u8 fixme[0x1000];
  554. } sdhc83xx_t;
  555. /*
  556. * SerDes
  557. */
  558. typedef struct serdes83xx {
  559. u32 srdscr0;
  560. u32 srdscr1;
  561. u32 srdscr2;
  562. u32 srdscr3;
  563. u32 srdscr4;
  564. u8 res0[0xc];
  565. u32 srdsrstctl;
  566. u8 res1[0xdc];
  567. } serdes83xx_t;
  568. /*
  569. * On Chip ROM
  570. */
  571. typedef struct rom83xx {
  572. #if defined(CONFIG_ARCH_MPC8309)
  573. u8 mem[0x8000];
  574. #else
  575. u8 mem[0x10000];
  576. #endif
  577. } rom83xx_t;
  578. /*
  579. * TDM
  580. */
  581. typedef struct tdm83xx {
  582. u8 fixme[0x200];
  583. } tdm83xx_t;
  584. /*
  585. * TDM DMAC
  586. */
  587. typedef struct tdmdmac83xx {
  588. u8 fixme[0x2000];
  589. } tdmdmac83xx_t;
  590. #if defined(CONFIG_ARCH_MPC834X)
  591. typedef struct immap {
  592. sysconf83xx_t sysconf; /* System configuration */
  593. wdt83xx_t wdt; /* Watch Dog Timer (WDT) Registers */
  594. rtclk83xx_t rtc; /* Real Time Clock Module Registers */
  595. rtclk83xx_t pit; /* Periodic Interval Timer */
  596. gtm83xx_t gtm[2]; /* Global Timers Module */
  597. ipic83xx_t ipic; /* Integrated Programmable Interrupt Controller */
  598. arbiter83xx_t arbiter; /* System Arbiter Registers */
  599. reset83xx_t reset; /* Reset Module */
  600. clk83xx_t clk; /* System Clock Module */
  601. pmc83xx_t pmc; /* Power Management Control Module */
  602. gpio83xx_t gpio[2]; /* General purpose I/O module */
  603. u8 res0[0x200];
  604. u8 dll_ddr[0x100];
  605. u8 dll_lbc[0x100];
  606. u8 res1[0xE00];
  607. #if defined(CONFIG_SYS_FSL_DDR2) || defined(CONFIG_SYS_FSL_DDR3)
  608. struct ccsr_ddr ddr; /* DDR Memory Controller Memory */
  609. #else
  610. ddr83xx_t ddr; /* DDR Memory Controller Memory */
  611. #endif
  612. fsl_i2c_t i2c[2]; /* I2C Controllers */
  613. u8 res2[0x1300];
  614. duart83xx_t duart[2]; /* DUART */
  615. u8 res3[0x900];
  616. fsl_lbc_t im_lbc; /* Local Bus Controller Regs */
  617. u8 res4[0x1000];
  618. spi8xxx_t spi; /* Serial Peripheral Interface */
  619. dma83xx_t dma; /* DMA */
  620. pciconf83xx_t pci_conf[2]; /* PCI Software Configuration Registers */
  621. ios83xx_t ios; /* Sequencer */
  622. pcictrl83xx_t pci_ctrl[2]; /* PCI Controller Control and Status Registers */
  623. u8 res5[0x19900];
  624. usb83xx_t usb[2];
  625. tsec83xx_t tsec[2];
  626. u8 res6[0xA000];
  627. security83xx_t security;
  628. u8 res7[0xC0000];
  629. } immap_t;
  630. #ifndef CONFIG_ARCH_MPC834X
  631. #ifdef CONFIG_HAS_FSL_MPH_USB
  632. #define CONFIG_SYS_MPC83xx_USB1_OFFSET 0x22000 /* use the MPH controller */
  633. #define CONFIG_SYS_MPC83xx_USB2_OFFSET 0
  634. #else
  635. #define CONFIG_SYS_MPC83xx_USB1_OFFSET 0
  636. #define CONFIG_SYS_MPC83xx_USB2_OFFSET 0x23000 /* use the DR controller */
  637. #endif
  638. #else
  639. #define CONFIG_SYS_MPC83xx_USB1_OFFSET 0x22000
  640. #define CONFIG_SYS_MPC83xx_USB2_OFFSET 0x23000
  641. #endif
  642. #elif defined(CONFIG_ARCH_MPC8313)
  643. typedef struct immap {
  644. sysconf83xx_t sysconf; /* System configuration */
  645. wdt83xx_t wdt; /* Watch Dog Timer (WDT) Registers */
  646. rtclk83xx_t rtc; /* Real Time Clock Module Registers */
  647. rtclk83xx_t pit; /* Periodic Interval Timer */
  648. gtm83xx_t gtm[2]; /* Global Timers Module */
  649. ipic83xx_t ipic; /* Integrated Programmable Interrupt Controller */
  650. arbiter83xx_t arbiter; /* System Arbiter Registers */
  651. reset83xx_t reset; /* Reset Module */
  652. clk83xx_t clk; /* System Clock Module */
  653. pmc83xx_t pmc; /* Power Management Control Module */
  654. gpio83xx_t gpio[1]; /* General purpose I/O module */
  655. u8 res0[0x1300];
  656. ddr83xx_t ddr; /* DDR Memory Controller Memory */
  657. fsl_i2c_t i2c[2]; /* I2C Controllers */
  658. u8 res1[0x1300];
  659. duart83xx_t duart[2]; /* DUART */
  660. u8 res2[0x900];
  661. fsl_lbc_t im_lbc; /* Local Bus Controller Regs */
  662. u8 res3[0x1000];
  663. spi8xxx_t spi; /* Serial Peripheral Interface */
  664. dma83xx_t dma; /* DMA */
  665. pciconf83xx_t pci_conf[1]; /* PCI Software Configuration Registers */
  666. u8 res4[0x80];
  667. ios83xx_t ios; /* Sequencer */
  668. pcictrl83xx_t pci_ctrl[1]; /* PCI Controller Control and Status Registers */
  669. u8 res5[0x1aa00];
  670. usb83xx_t usb[1];
  671. tsec83xx_t tsec[2];
  672. u8 res6[0xA000];
  673. security83xx_t security;
  674. u8 res7[0xC0000];
  675. } immap_t;
  676. #elif defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC8315)
  677. typedef struct immap {
  678. sysconf83xx_t sysconf; /* System configuration */
  679. wdt83xx_t wdt; /* Watch Dog Timer (WDT) Registers */
  680. rtclk83xx_t rtc; /* Real Time Clock Module Registers */
  681. rtclk83xx_t pit; /* Periodic Interval Timer */
  682. gtm83xx_t gtm[2]; /* Global Timers Module */
  683. ipic83xx_t ipic; /* Integrated Programmable Interrupt Controller */
  684. arbiter83xx_t arbiter; /* System Arbiter Registers */
  685. reset83xx_t reset; /* Reset Module */
  686. clk83xx_t clk; /* System Clock Module */
  687. pmc83xx_t pmc; /* Power Management Control Module */
  688. gpio83xx_t gpio[1]; /* General purpose I/O module */
  689. u8 res0[0x1300];
  690. ddr83xx_t ddr; /* DDR Memory Controller Memory */
  691. fsl_i2c_t i2c[2]; /* I2C Controllers */
  692. u8 res1[0x1300];
  693. duart83xx_t duart[2]; /* DUART */
  694. u8 res2[0x900];
  695. fsl_lbc_t im_lbc; /* Local Bus Controller Regs */
  696. u8 res3[0x1000];
  697. spi8xxx_t spi; /* Serial Peripheral Interface */
  698. dma83xx_t dma; /* DMA */
  699. pciconf83xx_t pci_conf[1]; /* PCI Software Configuration Registers */
  700. u8 res4[0x80];
  701. ios83xx_t ios; /* Sequencer */
  702. pcictrl83xx_t pci_ctrl[1]; /* PCI Controller Control and Status Registers */
  703. u8 res5[0xa00];
  704. pex83xx_t pciexp[2]; /* PCI Express Controller */
  705. u8 res6[0xb000];
  706. tdm83xx_t tdm; /* TDM Controller */
  707. u8 res7[0x1e00];
  708. sata83xx_t sata[2]; /* SATA Controller */
  709. u8 res8[0x9000];
  710. usb83xx_t usb[1]; /* USB DR Controller */
  711. tsec83xx_t tsec[2];
  712. u8 res9[0x6000];
  713. tdmdmac83xx_t tdmdmac; /* TDM DMAC */
  714. u8 res10[0x2000];
  715. security83xx_t security;
  716. u8 res11[0xA3000];
  717. serdes83xx_t serdes[1]; /* SerDes Registers */
  718. u8 res12[0x1CF00];
  719. } immap_t;
  720. #elif defined(CONFIG_MPC837x)
  721. typedef struct immap {
  722. sysconf83xx_t sysconf; /* System configuration */
  723. wdt83xx_t wdt; /* Watch Dog Timer (WDT) Registers */
  724. rtclk83xx_t rtc; /* Real Time Clock Module Registers */
  725. rtclk83xx_t pit; /* Periodic Interval Timer */
  726. gtm83xx_t gtm[2]; /* Global Timers Module */
  727. ipic83xx_t ipic; /* Integrated Programmable Interrupt Controller */
  728. arbiter83xx_t arbiter; /* System Arbiter Registers */
  729. reset83xx_t reset; /* Reset Module */
  730. clk83xx_t clk; /* System Clock Module */
  731. pmc83xx_t pmc; /* Power Management Control Module */
  732. gpio83xx_t gpio[2]; /* General purpose I/O module */
  733. u8 res0[0x1200];
  734. ddr83xx_t ddr; /* DDR Memory Controller Memory */
  735. fsl_i2c_t i2c[2]; /* I2C Controllers */
  736. u8 res1[0x1300];
  737. duart83xx_t duart[2]; /* DUART */
  738. u8 res2[0x900];
  739. fsl_lbc_t im_lbc; /* Local Bus Controller Regs */
  740. u8 res3[0x1000];
  741. spi8xxx_t spi; /* Serial Peripheral Interface */
  742. dma83xx_t dma; /* DMA */
  743. pciconf83xx_t pci_conf[1]; /* PCI Software Configuration Registers */
  744. u8 res4[0x80];
  745. ios83xx_t ios; /* Sequencer */
  746. pcictrl83xx_t pci_ctrl[1]; /* PCI Controller Control and Status Registers */
  747. u8 res5[0xa00];
  748. pex83xx_t pciexp[2]; /* PCI Express Controller */
  749. u8 res6[0xd000];
  750. sata83xx_t sata[4]; /* SATA Controller */
  751. u8 res7[0x7000];
  752. usb83xx_t usb[1]; /* USB DR Controller */
  753. tsec83xx_t tsec[2];
  754. u8 res8[0x8000];
  755. sdhc83xx_t sdhc; /* SDHC Controller */
  756. u8 res9[0x1000];
  757. security83xx_t security;
  758. u8 res10[0xA3000];
  759. serdes83xx_t serdes[2]; /* SerDes Registers */
  760. u8 res11[0xCE00];
  761. rom83xx_t rom; /* On Chip ROM */
  762. } immap_t;
  763. #elif defined(CONFIG_MPC8360)
  764. typedef struct immap {
  765. sysconf83xx_t sysconf; /* System configuration */
  766. wdt83xx_t wdt; /* Watch Dog Timer (WDT) Registers */
  767. rtclk83xx_t rtc; /* Real Time Clock Module Registers */
  768. rtclk83xx_t pit; /* Periodic Interval Timer */
  769. u8 res0[0x200];
  770. ipic83xx_t ipic; /* Integrated Programmable Interrupt Controller */
  771. arbiter83xx_t arbiter; /* System Arbiter Registers */
  772. reset83xx_t reset; /* Reset Module */
  773. clk83xx_t clk; /* System Clock Module */
  774. pmc83xx_t pmc; /* Power Management Control Module */
  775. qepi83xx_t qepi; /* QE Ports Interrupts Registers */
  776. u8 res1[0x300];
  777. u8 dll_ddr[0x100];
  778. u8 dll_lbc[0x100];
  779. u8 res2[0x200];
  780. qepio83xx_t qepio; /* QE Parallel I/O ports */
  781. qesba83xx_t qesba; /* QE Secondary Bus Access Windows */
  782. u8 res3[0x400];
  783. ddr83xx_t ddr; /* DDR Memory Controller Memory */
  784. fsl_i2c_t i2c[2]; /* I2C Controllers */
  785. u8 res4[0x1300];
  786. duart83xx_t duart[2]; /* DUART */
  787. u8 res5[0x900];
  788. fsl_lbc_t im_lbc; /* Local Bus Controller Regs */
  789. u8 res6[0x2000];
  790. dma83xx_t dma; /* DMA */
  791. pciconf83xx_t pci_conf[1]; /* PCI Software Configuration Registers */
  792. u8 res7[128];
  793. ios83xx_t ios; /* Sequencer (IOS) */
  794. pcictrl83xx_t pci_ctrl[1]; /* PCI Controller Control and Status Registers */
  795. u8 res8[0x4A00];
  796. ddr83xx_t ddr_secondary; /* Secondary DDR Memory Controller Memory Map */
  797. u8 res9[0x22000];
  798. security83xx_t security;
  799. u8 res10[0xC0000];
  800. u8 qe[0x100000]; /* QE block */
  801. } immap_t;
  802. #elif defined(CONFIG_ARCH_MPC832X)
  803. typedef struct immap {
  804. sysconf83xx_t sysconf; /* System configuration */
  805. wdt83xx_t wdt; /* Watch Dog Timer (WDT) Registers */
  806. rtclk83xx_t rtc; /* Real Time Clock Module Registers */
  807. rtclk83xx_t pit; /* Periodic Interval Timer */
  808. gtm83xx_t gtm[2]; /* Global Timers Module */
  809. ipic83xx_t ipic; /* Integrated Programmable Interrupt Controller */
  810. arbiter83xx_t arbiter; /* System Arbiter Registers */
  811. reset83xx_t reset; /* Reset Module */
  812. clk83xx_t clk; /* System Clock Module */
  813. pmc83xx_t pmc; /* Power Management Control Module */
  814. qepi83xx_t qepi; /* QE Ports Interrupts Registers */
  815. u8 res0[0x300];
  816. u8 dll_ddr[0x100];
  817. u8 dll_lbc[0x100];
  818. u8 res1[0x200];
  819. qepio83xx_t qepio; /* QE Parallel I/O ports */
  820. u8 res2[0x800];
  821. ddr83xx_t ddr; /* DDR Memory Controller Memory */
  822. fsl_i2c_t i2c[2]; /* I2C Controllers */
  823. u8 res3[0x1300];
  824. duart83xx_t duart[2]; /* DUART */
  825. u8 res4[0x900];
  826. fsl_lbc_t im_lbc; /* Local Bus Controller Regs */
  827. u8 res5[0x2000];
  828. dma83xx_t dma; /* DMA */
  829. pciconf83xx_t pci_conf[1]; /* PCI Software Configuration Registers */
  830. u8 res6[128];
  831. ios83xx_t ios; /* Sequencer (IOS) */
  832. pcictrl83xx_t pci_ctrl[1]; /* PCI Controller Control and Status Registers */
  833. u8 res7[0x27A00];
  834. security83xx_t security;
  835. u8 res8[0xC0000];
  836. u8 qe[0x100000]; /* QE block */
  837. } immap_t;
  838. #elif defined(CONFIG_ARCH_MPC8309)
  839. typedef struct immap {
  840. sysconf83xx_t sysconf; /* System configuration */
  841. wdt83xx_t wdt; /* Watch Dog Timer (WDT) Registers */
  842. rtclk83xx_t rtc; /* Real Time Clock Module Registers */
  843. rtclk83xx_t pit; /* Periodic Interval Timer */
  844. gtm83xx_t gtm[2]; /* Global Timers Module */
  845. ipic83xx_t ipic; /* Integrated Programmable Interrupt Controller */
  846. arbiter83xx_t arbiter; /* System Arbiter Registers */
  847. reset83xx_t reset; /* Reset Module */
  848. clk83xx_t clk; /* System Clock Module */
  849. pmc83xx_t pmc; /* Power Management Control Module */
  850. gpio83xx_t gpio[2]; /* General purpose I/O module */
  851. u8 res0[0x500]; /* res0 1.25 KBytes added for 8309 */
  852. qepi83xx_t qepi; /* QE Ports Interrupts Registers */
  853. qepio83xx_t qepio; /* QE Parallel I/O ports */
  854. u8 res1[0x800];
  855. ddr83xx_t ddr; /* DDR Memory Controller Memory */
  856. fsl_i2c_t i2c[2]; /* I2C Controllers */
  857. u8 res2[0x1300];
  858. duart83xx_t duart[2]; /* DUART */
  859. u8 res3[0x200];
  860. duart83xx_t duart1[2]; /* DUART */
  861. u8 res4[0x500];
  862. fsl_lbc_t im_lbc; /* Local Bus Controller Regs */
  863. u8 res5[0x1000];
  864. u8 spi[0x100];
  865. u8 res6[0xf00];
  866. dma83xx_t dma; /* DMA */
  867. pciconf83xx_t pci_conf[1]; /* PCI Configuration Registers */
  868. u8 res7[0x80];
  869. ios83xx_t ios; /* Sequencer (IOS) */
  870. pcictrl83xx_t pci_ctrl[1]; /* PCI Control & Status Registers */
  871. u8 res8[0x13A00];
  872. u8 can1[0x1000]; /* Flexcan 1 */
  873. u8 can2[0x1000]; /* Flexcan 2 */
  874. u8 res9[0x5000];
  875. usb83xx_t usb;
  876. u8 res10[0x5000];
  877. u8 can3[0x1000]; /* Flexcan 3 */
  878. u8 can4[0x1000]; /* Flexcan 4 */
  879. u8 res11[0x1000];
  880. u8 dma1[0x2000]; /* DMA */
  881. sdhc83xx_t sdhc; /* SDHC Controller */
  882. u8 res12[0xC1000];
  883. rom83xx_t rom; /* On Chip ROM */
  884. u8 res13[0x8000];
  885. u8 qe[0x100000]; /* QE block */
  886. u8 res14[0xE00000];/* Added for 8309 */
  887. } immap_t;
  888. #endif
  889. #define CONFIG_SYS_MPC8xxx_DDR_OFFSET (0x2000)
  890. #define CONFIG_SYS_FSL_DDR_ADDR \
  891. (CONFIG_SYS_IMMR + CONFIG_SYS_MPC8xxx_DDR_OFFSET)
  892. #define CONFIG_SYS_MPC83xx_DMA_OFFSET (0x8000)
  893. #define CONFIG_SYS_MPC83xx_DMA_ADDR \
  894. (CONFIG_SYS_IMMR + CONFIG_SYS_MPC83xx_DMA_OFFSET)
  895. #define CONFIG_SYS_MPC83xx_ESDHC_OFFSET (0x2e000)
  896. #define CONFIG_SYS_MPC83xx_ESDHC_ADDR \
  897. (CONFIG_SYS_IMMR + CONFIG_SYS_MPC83xx_ESDHC_OFFSET)
  898. #ifndef CONFIG_SYS_MPC83xx_USB1_OFFSET
  899. #define CONFIG_SYS_MPC83xx_USB1_OFFSET 0x23000
  900. #endif
  901. #define CONFIG_SYS_MPC83xx_USB1_ADDR \
  902. (CONFIG_SYS_IMMR + CONFIG_SYS_MPC83xx_USB1_OFFSET)
  903. #if defined(CONFIG_ARCH_MPC834X)
  904. #define CONFIG_SYS_MPC83xx_USB2_ADDR \
  905. (CONFIG_SYS_IMMR + CONFIG_SYS_MPC83xx_USB2_OFFSET)
  906. #endif
  907. #define CONFIG_SYS_LBC_ADDR (&((immap_t *)CONFIG_SYS_IMMR)->im_lbc)
  908. #define CONFIG_SYS_TSEC1_OFFSET 0x24000
  909. #define CONFIG_SYS_MDIO1_OFFSET 0x24000
  910. #define TSEC_BASE_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC1_OFFSET)
  911. #define MDIO_BASE_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MDIO1_OFFSET)
  912. #endif /* __IMMAP_83xx__ */