spd_sdram.c 25 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712713714715716717718719720721722723724725726727728729730731732733734735736737738739740741742743744745746747748749750751752753754755756757758759760761762763764765766767768769770771772773774775776777778779780781782783784785786787788789790791792793794795796797798799800801802803804805806807808809810811812813814815816817818819820821822823824825826827828829830831832833834835836837838839840841842843844845846847848849850851852853854855856857858859860861862863864865866867868869870871872873874875876877878879880881882883884885886887888889890891892893894895896897898899900901902903904905906907908909910911912913914915916917918919920921922923924925926927928929930
  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2006-2007 Freescale Semiconductor, Inc.
  4. *
  5. * (C) Copyright 2006
  6. * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  7. *
  8. * Copyright (C) 2004-2006 Freescale Semiconductor, Inc.
  9. * (C) Copyright 2003 Motorola Inc.
  10. * Xianghua Xiao (X.Xiao@motorola.com)
  11. */
  12. #ifndef CONFIG_MPC83XX_SDRAM
  13. #include <common.h>
  14. #include <asm/processor.h>
  15. #include <asm/io.h>
  16. #include <i2c.h>
  17. #include <spd.h>
  18. #include <asm/mmu.h>
  19. #include <spd_sdram.h>
  20. DECLARE_GLOBAL_DATA_PTR;
  21. void board_add_ram_info(int use_default)
  22. {
  23. volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
  24. volatile ddr83xx_t *ddr = &immap->ddr;
  25. char buf[32];
  26. printf(" (DDR%d", ((ddr->sdram_cfg & SDRAM_CFG_SDRAM_TYPE_MASK)
  27. >> SDRAM_CFG_SDRAM_TYPE_SHIFT) - 1);
  28. #if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X)
  29. if ((ddr->sdram_cfg & SDRAM_CFG_DBW_MASK) == SDRAM_CFG_DBW_16)
  30. puts(", 16-bit");
  31. else if ((ddr->sdram_cfg & SDRAM_CFG_DBW_MASK) == SDRAM_CFG_DBW_32)
  32. puts(", 32-bit");
  33. else
  34. puts(", unknown width");
  35. #else
  36. if (ddr->sdram_cfg & SDRAM_CFG_32_BE)
  37. puts(", 32-bit");
  38. else
  39. puts(", 64-bit");
  40. #endif
  41. if (ddr->sdram_cfg & SDRAM_CFG_ECC_EN)
  42. puts(", ECC on");
  43. else
  44. puts(", ECC off");
  45. printf(", %s MHz)", strmhz(buf, gd->mem_clk));
  46. #if defined(CONFIG_SYS_LB_SDRAM) && defined(CONFIG_SYS_LBC_SDRAM_SIZE)
  47. puts("\nSDRAM: ");
  48. print_size (CONFIG_SYS_LBC_SDRAM_SIZE * 1024 * 1024, " (local bus)");
  49. #endif
  50. }
  51. #ifdef CONFIG_SPD_EEPROM
  52. #ifndef CONFIG_SYS_READ_SPD
  53. #define CONFIG_SYS_READ_SPD i2c_read
  54. #endif
  55. #ifndef SPD_EEPROM_OFFSET
  56. #define SPD_EEPROM_OFFSET 0
  57. #endif
  58. #ifndef SPD_EEPROM_ADDR_LEN
  59. #define SPD_EEPROM_ADDR_LEN 1
  60. #endif
  61. /*
  62. * Convert picoseconds into clock cycles (rounding up if needed).
  63. */
  64. int
  65. picos_to_clk(int picos)
  66. {
  67. unsigned int mem_bus_clk;
  68. int clks;
  69. mem_bus_clk = gd->mem_clk >> 1;
  70. clks = picos / (1000000000 / (mem_bus_clk / 1000));
  71. if (picos % (1000000000 / (mem_bus_clk / 1000)) != 0)
  72. clks++;
  73. return clks;
  74. }
  75. unsigned int banksize(unsigned char row_dens)
  76. {
  77. return ((row_dens >> 2) | ((row_dens & 3) << 6)) << 24;
  78. }
  79. int read_spd(uint addr)
  80. {
  81. return ((int) addr);
  82. }
  83. #undef SPD_DEBUG
  84. #ifdef SPD_DEBUG
  85. static void spd_debug(spd_eeprom_t *spd)
  86. {
  87. printf ("\nDIMM type: %-18.18s\n", spd->mpart);
  88. printf ("SPD size: %d\n", spd->info_size);
  89. printf ("EEPROM size: %d\n", 1 << spd->chip_size);
  90. printf ("Memory type: %d\n", spd->mem_type);
  91. printf ("Row addr: %d\n", spd->nrow_addr);
  92. printf ("Column addr: %d\n", spd->ncol_addr);
  93. printf ("# of rows: %d\n", spd->nrows);
  94. printf ("Row density: %d\n", spd->row_dens);
  95. printf ("# of banks: %d\n", spd->nbanks);
  96. printf ("Data width: %d\n",
  97. 256 * spd->dataw_msb + spd->dataw_lsb);
  98. printf ("Chip width: %d\n", spd->primw);
  99. printf ("Refresh rate: %02X\n", spd->refresh);
  100. printf ("CAS latencies: %02X\n", spd->cas_lat);
  101. printf ("Write latencies: %02X\n", spd->write_lat);
  102. printf ("tRP: %d\n", spd->trp);
  103. printf ("tRCD: %d\n", spd->trcd);
  104. printf ("\n");
  105. }
  106. #endif /* SPD_DEBUG */
  107. long int spd_sdram()
  108. {
  109. volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
  110. volatile ddr83xx_t *ddr = &immap->ddr;
  111. volatile law83xx_t *ecm = &immap->sysconf.ddrlaw[0];
  112. spd_eeprom_t spd;
  113. unsigned int n_ranks;
  114. unsigned int odt_rd_cfg, odt_wr_cfg;
  115. unsigned char twr_clk, twtr_clk;
  116. unsigned int sdram_type;
  117. unsigned int memsize;
  118. unsigned int law_size;
  119. unsigned char caslat, caslat_ctrl;
  120. unsigned int trfc, trfc_clk, trfc_low;
  121. unsigned int trcd_clk, trtp_clk;
  122. unsigned char cke_min_clk;
  123. unsigned char add_lat, wr_lat;
  124. unsigned char wr_data_delay;
  125. unsigned char four_act;
  126. unsigned char cpo;
  127. unsigned char burstlen;
  128. unsigned char odt_cfg, mode_odt_enable;
  129. unsigned int max_bus_clk;
  130. unsigned int max_data_rate, effective_data_rate;
  131. unsigned int ddrc_clk;
  132. unsigned int refresh_clk;
  133. unsigned int sdram_cfg;
  134. unsigned int ddrc_ecc_enable;
  135. unsigned int pvr = get_pvr();
  136. /*
  137. * First disable the memory controller (could be enabled
  138. * by the debugger)
  139. */
  140. clrsetbits_be32(&ddr->sdram_cfg, SDRAM_CFG_MEM_EN, 0);
  141. sync();
  142. isync();
  143. /* Read SPD parameters with I2C */
  144. CONFIG_SYS_READ_SPD(SPD_EEPROM_ADDRESS, SPD_EEPROM_OFFSET,
  145. SPD_EEPROM_ADDR_LEN, (uchar *) &spd, sizeof(spd));
  146. #ifdef SPD_DEBUG
  147. spd_debug(&spd);
  148. #endif
  149. /* Check the memory type */
  150. if (spd.mem_type != SPD_MEMTYPE_DDR && spd.mem_type != SPD_MEMTYPE_DDR2) {
  151. debug("DDR: Module mem type is %02X\n", spd.mem_type);
  152. return 0;
  153. }
  154. /* Check the number of physical bank */
  155. if (spd.mem_type == SPD_MEMTYPE_DDR) {
  156. n_ranks = spd.nrows;
  157. } else {
  158. n_ranks = (spd.nrows & 0x7) + 1;
  159. }
  160. if (n_ranks > 2) {
  161. printf("DDR: The number of physical bank is %02X\n", n_ranks);
  162. return 0;
  163. }
  164. /* Check if the number of row of the module is in the range of DDRC */
  165. if (spd.nrow_addr < 12 || spd.nrow_addr > 15) {
  166. printf("DDR: Row number is out of range of DDRC, row=%02X\n",
  167. spd.nrow_addr);
  168. return 0;
  169. }
  170. /* Check if the number of col of the module is in the range of DDRC */
  171. if (spd.ncol_addr < 8 || spd.ncol_addr > 11) {
  172. printf("DDR: Col number is out of range of DDRC, col=%02X\n",
  173. spd.ncol_addr);
  174. return 0;
  175. }
  176. #ifdef CONFIG_SYS_DDRCDR_VALUE
  177. /*
  178. * Adjust DDR II IO voltage biasing. It just makes it work.
  179. */
  180. if(spd.mem_type == SPD_MEMTYPE_DDR2) {
  181. immap->sysconf.ddrcdr = CONFIG_SYS_DDRCDR_VALUE;
  182. }
  183. udelay(50000);
  184. #endif
  185. /*
  186. * ODT configuration recommendation from DDR Controller Chapter.
  187. */
  188. odt_rd_cfg = 0; /* Never assert ODT */
  189. odt_wr_cfg = 0; /* Never assert ODT */
  190. if (spd.mem_type == SPD_MEMTYPE_DDR2) {
  191. odt_wr_cfg = 1; /* Assert ODT on writes to CSn */
  192. }
  193. /* Setup DDR chip select register */
  194. #ifdef CONFIG_SYS_83XX_DDR_USES_CS0
  195. ddr->csbnds[0].csbnds = (banksize(spd.row_dens) >> 24) - 1;
  196. ddr->cs_config[0] = ( 1 << 31
  197. | (odt_rd_cfg << 20)
  198. | (odt_wr_cfg << 16)
  199. | ((spd.nbanks == 8 ? 1 : 0) << 14)
  200. | ((spd.nrow_addr - 12) << 8)
  201. | (spd.ncol_addr - 8) );
  202. debug("\n");
  203. debug("cs0_bnds = 0x%08x\n",ddr->csbnds[0].csbnds);
  204. debug("cs0_config = 0x%08x\n",ddr->cs_config[0]);
  205. if (n_ranks == 2) {
  206. ddr->csbnds[1].csbnds = ( (banksize(spd.row_dens) >> 8)
  207. | ((banksize(spd.row_dens) >> 23) - 1) );
  208. ddr->cs_config[1] = ( 1<<31
  209. | (odt_rd_cfg << 20)
  210. | (odt_wr_cfg << 16)
  211. | ((spd.nbanks == 8 ? 1 : 0) << 14)
  212. | ((spd.nrow_addr - 12) << 8)
  213. | (spd.ncol_addr - 8) );
  214. debug("cs1_bnds = 0x%08x\n",ddr->csbnds[1].csbnds);
  215. debug("cs1_config = 0x%08x\n",ddr->cs_config[1]);
  216. }
  217. #else
  218. ddr->csbnds[2].csbnds = (banksize(spd.row_dens) >> 24) - 1;
  219. ddr->cs_config[2] = ( 1 << 31
  220. | (odt_rd_cfg << 20)
  221. | (odt_wr_cfg << 16)
  222. | ((spd.nbanks == 8 ? 1 : 0) << 14)
  223. | ((spd.nrow_addr - 12) << 8)
  224. | (spd.ncol_addr - 8) );
  225. debug("\n");
  226. debug("cs2_bnds = 0x%08x\n",ddr->csbnds[2].csbnds);
  227. debug("cs2_config = 0x%08x\n",ddr->cs_config[2]);
  228. if (n_ranks == 2) {
  229. ddr->csbnds[3].csbnds = ( (banksize(spd.row_dens) >> 8)
  230. | ((banksize(spd.row_dens) >> 23) - 1) );
  231. ddr->cs_config[3] = ( 1<<31
  232. | (odt_rd_cfg << 20)
  233. | (odt_wr_cfg << 16)
  234. | ((spd.nbanks == 8 ? 1 : 0) << 14)
  235. | ((spd.nrow_addr - 12) << 8)
  236. | (spd.ncol_addr - 8) );
  237. debug("cs3_bnds = 0x%08x\n",ddr->csbnds[3].csbnds);
  238. debug("cs3_config = 0x%08x\n",ddr->cs_config[3]);
  239. }
  240. #endif
  241. /*
  242. * Figure out memory size in Megabytes.
  243. */
  244. memsize = n_ranks * banksize(spd.row_dens) / 0x100000;
  245. /*
  246. * First supported LAW size is 16M, at LAWAR_SIZE_16M == 23.
  247. */
  248. law_size = 19 + __ilog2(memsize);
  249. /*
  250. * Set up LAWBAR for all of DDR.
  251. */
  252. ecm->bar = CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000;
  253. ecm->ar = (LAWAR_EN | LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & law_size));
  254. debug("DDR:bar=0x%08x\n", ecm->bar);
  255. debug("DDR:ar=0x%08x\n", ecm->ar);
  256. /*
  257. * Find the largest CAS by locating the highest 1 bit
  258. * in the spd.cas_lat field. Translate it to a DDR
  259. * controller field value:
  260. *
  261. * CAS Lat DDR I DDR II Ctrl
  262. * Clocks SPD Bit SPD Bit Value
  263. * ------- ------- ------- -----
  264. * 1.0 0 0001
  265. * 1.5 1 0010
  266. * 2.0 2 2 0011
  267. * 2.5 3 0100
  268. * 3.0 4 3 0101
  269. * 3.5 5 0110
  270. * 4.0 6 4 0111
  271. * 4.5 1000
  272. * 5.0 5 1001
  273. */
  274. caslat = __ilog2(spd.cas_lat);
  275. if ((spd.mem_type == SPD_MEMTYPE_DDR)
  276. && (caslat > 6)) {
  277. printf("DDR I: Invalid SPD CAS Latency: 0x%x.\n", spd.cas_lat);
  278. return 0;
  279. } else if (spd.mem_type == SPD_MEMTYPE_DDR2
  280. && (caslat < 2 || caslat > 5)) {
  281. printf("DDR II: Invalid SPD CAS Latency: 0x%x.\n",
  282. spd.cas_lat);
  283. return 0;
  284. }
  285. debug("DDR: caslat SPD bit is %d\n", caslat);
  286. max_bus_clk = 1000 *10 / (((spd.clk_cycle & 0xF0) >> 4) * 10
  287. + (spd.clk_cycle & 0x0f));
  288. max_data_rate = max_bus_clk * 2;
  289. debug("DDR:Module maximum data rate is: %d MHz\n", max_data_rate);
  290. ddrc_clk = gd->mem_clk / 1000000;
  291. effective_data_rate = 0;
  292. if (max_data_rate >= 460) { /* it is DDR2-800, 667, 533 */
  293. if (spd.cas_lat & 0x08)
  294. caslat = 3;
  295. else
  296. caslat = 4;
  297. if (ddrc_clk <= 460 && ddrc_clk > 350)
  298. effective_data_rate = 400;
  299. else if (ddrc_clk <=350 && ddrc_clk > 280)
  300. effective_data_rate = 333;
  301. else if (ddrc_clk <= 280 && ddrc_clk > 230)
  302. effective_data_rate = 266;
  303. else
  304. effective_data_rate = 200;
  305. } else if (max_data_rate >= 390 && max_data_rate < 460) { /* it is DDR 400 */
  306. if (ddrc_clk <= 460 && ddrc_clk > 350) {
  307. /* DDR controller clk at 350~460 */
  308. effective_data_rate = 400; /* 5ns */
  309. caslat = caslat;
  310. } else if (ddrc_clk <= 350 && ddrc_clk > 280) {
  311. /* DDR controller clk at 280~350 */
  312. effective_data_rate = 333; /* 6ns */
  313. if (spd.clk_cycle2 == 0x60)
  314. caslat = caslat - 1;
  315. else
  316. caslat = caslat;
  317. } else if (ddrc_clk <= 280 && ddrc_clk > 230) {
  318. /* DDR controller clk at 230~280 */
  319. effective_data_rate = 266; /* 7.5ns */
  320. if (spd.clk_cycle3 == 0x75)
  321. caslat = caslat - 2;
  322. else if (spd.clk_cycle2 == 0x75)
  323. caslat = caslat - 1;
  324. else
  325. caslat = caslat;
  326. } else if (ddrc_clk <= 230 && ddrc_clk > 90) {
  327. /* DDR controller clk at 90~230 */
  328. effective_data_rate = 200; /* 10ns */
  329. if (spd.clk_cycle3 == 0xa0)
  330. caslat = caslat - 2;
  331. else if (spd.clk_cycle2 == 0xa0)
  332. caslat = caslat - 1;
  333. else
  334. caslat = caslat;
  335. }
  336. } else if (max_data_rate >= 323) { /* it is DDR 333 */
  337. if (ddrc_clk <= 350 && ddrc_clk > 280) {
  338. /* DDR controller clk at 280~350 */
  339. effective_data_rate = 333; /* 6ns */
  340. caslat = caslat;
  341. } else if (ddrc_clk <= 280 && ddrc_clk > 230) {
  342. /* DDR controller clk at 230~280 */
  343. effective_data_rate = 266; /* 7.5ns */
  344. if (spd.clk_cycle2 == 0x75)
  345. caslat = caslat - 1;
  346. else
  347. caslat = caslat;
  348. } else if (ddrc_clk <= 230 && ddrc_clk > 90) {
  349. /* DDR controller clk at 90~230 */
  350. effective_data_rate = 200; /* 10ns */
  351. if (spd.clk_cycle3 == 0xa0)
  352. caslat = caslat - 2;
  353. else if (spd.clk_cycle2 == 0xa0)
  354. caslat = caslat - 1;
  355. else
  356. caslat = caslat;
  357. }
  358. } else if (max_data_rate >= 256) { /* it is DDR 266 */
  359. if (ddrc_clk <= 350 && ddrc_clk > 280) {
  360. /* DDR controller clk at 280~350 */
  361. printf("DDR: DDR controller freq is more than "
  362. "max data rate of the module\n");
  363. return 0;
  364. } else if (ddrc_clk <= 280 && ddrc_clk > 230) {
  365. /* DDR controller clk at 230~280 */
  366. effective_data_rate = 266; /* 7.5ns */
  367. caslat = caslat;
  368. } else if (ddrc_clk <= 230 && ddrc_clk > 90) {
  369. /* DDR controller clk at 90~230 */
  370. effective_data_rate = 200; /* 10ns */
  371. if (spd.clk_cycle2 == 0xa0)
  372. caslat = caslat - 1;
  373. }
  374. } else if (max_data_rate >= 190) { /* it is DDR 200 */
  375. if (ddrc_clk <= 350 && ddrc_clk > 230) {
  376. /* DDR controller clk at 230~350 */
  377. printf("DDR: DDR controller freq is more than "
  378. "max data rate of the module\n");
  379. return 0;
  380. } else if (ddrc_clk <= 230 && ddrc_clk > 90) {
  381. /* DDR controller clk at 90~230 */
  382. effective_data_rate = 200; /* 10ns */
  383. caslat = caslat;
  384. }
  385. }
  386. debug("DDR:Effective data rate is: %dMHz\n", effective_data_rate);
  387. debug("DDR:The MSB 1 of CAS Latency is: %d\n", caslat);
  388. /*
  389. * Errata DDR6 work around: input enable 2 cycles earlier.
  390. * including MPC834X Rev1.0/1.1 and MPC8360 Rev1.1/1.2.
  391. */
  392. if(PVR_MAJ(pvr) <= 1 && spd.mem_type == SPD_MEMTYPE_DDR){
  393. if (caslat == 2)
  394. ddr->debug_reg = 0x201c0000; /* CL=2 */
  395. else if (caslat == 3)
  396. ddr->debug_reg = 0x202c0000; /* CL=2.5 */
  397. else if (caslat == 4)
  398. ddr->debug_reg = 0x202c0000; /* CL=3.0 */
  399. __asm__ __volatile__ ("sync");
  400. debug("Errata DDR6 (debug_reg=0x%08x)\n", ddr->debug_reg);
  401. }
  402. /*
  403. * Convert caslat clocks to DDR controller value.
  404. * Force caslat_ctrl to be DDR Controller field-sized.
  405. */
  406. if (spd.mem_type == SPD_MEMTYPE_DDR) {
  407. caslat_ctrl = (caslat + 1) & 0x07;
  408. } else {
  409. caslat_ctrl = (2 * caslat - 1) & 0x0f;
  410. }
  411. debug("DDR: effective data rate is %d MHz\n", effective_data_rate);
  412. debug("DDR: caslat SPD bit is %d, controller field is 0x%x\n",
  413. caslat, caslat_ctrl);
  414. /*
  415. * Timing Config 0.
  416. * Avoid writing for DDR I.
  417. */
  418. if (spd.mem_type == SPD_MEMTYPE_DDR2) {
  419. unsigned char taxpd_clk = 8; /* By the book. */
  420. unsigned char tmrd_clk = 2; /* By the book. */
  421. unsigned char act_pd_exit = 2; /* Empirical? */
  422. unsigned char pre_pd_exit = 6; /* Empirical? */
  423. ddr->timing_cfg_0 = (0
  424. | ((act_pd_exit & 0x7) << 20) /* ACT_PD_EXIT */
  425. | ((pre_pd_exit & 0x7) << 16) /* PRE_PD_EXIT */
  426. | ((taxpd_clk & 0xf) << 8) /* ODT_PD_EXIT */
  427. | ((tmrd_clk & 0xf) << 0) /* MRS_CYC */
  428. );
  429. debug("DDR: timing_cfg_0 = 0x%08x\n", ddr->timing_cfg_0);
  430. }
  431. /*
  432. * For DDR I, WRREC(Twr) and WRTORD(Twtr) are not in SPD,
  433. * use conservative value.
  434. * For DDR II, they are bytes 36 and 37, in quarter nanos.
  435. */
  436. if (spd.mem_type == SPD_MEMTYPE_DDR) {
  437. twr_clk = 3; /* Clocks */
  438. twtr_clk = 1; /* Clocks */
  439. } else {
  440. twr_clk = picos_to_clk(spd.twr * 250);
  441. twtr_clk = picos_to_clk(spd.twtr * 250);
  442. if (twtr_clk < 2)
  443. twtr_clk = 2;
  444. }
  445. /*
  446. * Calculate Trfc, in picos.
  447. * DDR I: Byte 42 straight up in ns.
  448. * DDR II: Byte 40 and 42 swizzled some, in ns.
  449. */
  450. if (spd.mem_type == SPD_MEMTYPE_DDR) {
  451. trfc = spd.trfc * 1000; /* up to ps */
  452. } else {
  453. unsigned int byte40_table_ps[8] = {
  454. 0,
  455. 250,
  456. 330,
  457. 500,
  458. 660,
  459. 750,
  460. 0,
  461. 0
  462. };
  463. trfc = (((spd.trctrfc_ext & 0x1) * 256) + spd.trfc) * 1000
  464. + byte40_table_ps[(spd.trctrfc_ext >> 1) & 0x7];
  465. }
  466. trfc_clk = picos_to_clk(trfc);
  467. /*
  468. * Trcd, Byte 29, from quarter nanos to ps and clocks.
  469. */
  470. trcd_clk = picos_to_clk(spd.trcd * 250) & 0x7;
  471. /*
  472. * Convert trfc_clk to DDR controller fields. DDR I should
  473. * fit in the REFREC field (16-19) of TIMING_CFG_1, but the
  474. * 83xx controller has an extended REFREC field of three bits.
  475. * The controller automatically adds 8 clocks to this value,
  476. * so preadjust it down 8 first before splitting it up.
  477. */
  478. trfc_low = (trfc_clk - 8) & 0xf;
  479. ddr->timing_cfg_1 =
  480. (((picos_to_clk(spd.trp * 250) & 0x07) << 28 ) | /* PRETOACT */
  481. ((picos_to_clk(spd.tras * 1000) & 0x0f ) << 24 ) | /* ACTTOPRE */
  482. (trcd_clk << 20 ) | /* ACTTORW */
  483. (caslat_ctrl << 16 ) | /* CASLAT */
  484. (trfc_low << 12 ) | /* REFEC */
  485. ((twr_clk & 0x07) << 8) | /* WRRREC */
  486. ((picos_to_clk(spd.trrd * 250) & 0x07) << 4) | /* ACTTOACT */
  487. ((twtr_clk & 0x07) << 0) /* WRTORD */
  488. );
  489. /*
  490. * Additive Latency
  491. * For DDR I, 0.
  492. * For DDR II, with ODT enabled, use "a value" less than ACTTORW,
  493. * which comes from Trcd, and also note that:
  494. * add_lat + caslat must be >= 4
  495. */
  496. add_lat = 0;
  497. if (spd.mem_type == SPD_MEMTYPE_DDR2
  498. && (odt_wr_cfg || odt_rd_cfg)
  499. && (caslat < 4)) {
  500. add_lat = 4 - caslat;
  501. if ((add_lat + caslat) < 4) {
  502. add_lat = 0;
  503. }
  504. }
  505. /*
  506. * Write Data Delay
  507. * Historically 0x2 == 4/8 clock delay.
  508. * Empirically, 0x3 == 6/8 clock delay is suggested for DDR I 266.
  509. */
  510. wr_data_delay = 2;
  511. #ifdef CONFIG_SYS_DDR_WRITE_DATA_DELAY
  512. wr_data_delay = CONFIG_SYS_DDR_WRITE_DATA_DELAY;
  513. #endif
  514. /*
  515. * Write Latency
  516. * Read to Precharge
  517. * Minimum CKE Pulse Width.
  518. * Four Activate Window
  519. */
  520. if (spd.mem_type == SPD_MEMTYPE_DDR) {
  521. /*
  522. * This is a lie. It should really be 1, but if it is
  523. * set to 1, bits overlap into the old controller's
  524. * otherwise unused ACSM field. If we leave it 0, then
  525. * the HW will magically treat it as 1 for DDR 1. Oh Yea.
  526. */
  527. wr_lat = 0;
  528. trtp_clk = 2; /* By the book. */
  529. cke_min_clk = 1; /* By the book. */
  530. four_act = 1; /* By the book. */
  531. } else {
  532. wr_lat = caslat - 1;
  533. /* Convert SPD value from quarter nanos to picos. */
  534. trtp_clk = picos_to_clk(spd.trtp * 250);
  535. if (trtp_clk < 2)
  536. trtp_clk = 2;
  537. trtp_clk += add_lat;
  538. cke_min_clk = 3; /* By the book. */
  539. four_act = picos_to_clk(37500); /* By the book. 1k pages? */
  540. }
  541. /*
  542. * Empirically set ~MCAS-to-preamble override for DDR 2.
  543. * Your mileage will vary.
  544. */
  545. cpo = 0;
  546. if (spd.mem_type == SPD_MEMTYPE_DDR2) {
  547. #ifdef CONFIG_SYS_DDR_CPO
  548. cpo = CONFIG_SYS_DDR_CPO;
  549. #else
  550. if (effective_data_rate == 266) {
  551. cpo = 0x4; /* READ_LAT + 1/2 */
  552. } else if (effective_data_rate == 333) {
  553. cpo = 0x6; /* READ_LAT + 1 */
  554. } else if (effective_data_rate == 400) {
  555. cpo = 0x7; /* READ_LAT + 5/4 */
  556. } else {
  557. /* Automatic calibration */
  558. cpo = 0x1f;
  559. }
  560. #endif
  561. }
  562. ddr->timing_cfg_2 = (0
  563. | ((add_lat & 0x7) << 28) /* ADD_LAT */
  564. | ((cpo & 0x1f) << 23) /* CPO */
  565. | ((wr_lat & 0x7) << 19) /* WR_LAT */
  566. | ((trtp_clk & 0x7) << 13) /* RD_TO_PRE */
  567. | ((wr_data_delay & 0x7) << 10) /* WR_DATA_DELAY */
  568. | ((cke_min_clk & 0x7) << 6) /* CKE_PLS */
  569. | ((four_act & 0x1f) << 0) /* FOUR_ACT */
  570. );
  571. debug("DDR:timing_cfg_1=0x%08x\n", ddr->timing_cfg_1);
  572. debug("DDR:timing_cfg_2=0x%08x\n", ddr->timing_cfg_2);
  573. /* Check DIMM data bus width */
  574. if (spd.dataw_lsb < 64) {
  575. if (spd.mem_type == SPD_MEMTYPE_DDR)
  576. burstlen = 0x03; /* 32 bit data bus, burst len is 8 */
  577. else
  578. burstlen = 0x02; /* 32 bit data bus, burst len is 4 */
  579. debug("\n DDR DIMM: data bus width is 32 bit");
  580. } else {
  581. burstlen = 0x02; /* Others act as 64 bit bus, burst len is 4 */
  582. debug("\n DDR DIMM: data bus width is 64 bit");
  583. }
  584. /* Is this an ECC DDR chip? */
  585. if (spd.config == 0x02)
  586. debug(" with ECC\n");
  587. else
  588. debug(" without ECC\n");
  589. /* Burst length is always 4 for 64 bit data bus, 8 for 32 bit data bus,
  590. Burst type is sequential
  591. */
  592. if (spd.mem_type == SPD_MEMTYPE_DDR) {
  593. switch (caslat) {
  594. case 1:
  595. ddr->sdram_mode = 0x50 | burstlen; /* CL=1.5 */
  596. break;
  597. case 2:
  598. ddr->sdram_mode = 0x20 | burstlen; /* CL=2.0 */
  599. break;
  600. case 3:
  601. ddr->sdram_mode = 0x60 | burstlen; /* CL=2.5 */
  602. break;
  603. case 4:
  604. ddr->sdram_mode = 0x30 | burstlen; /* CL=3.0 */
  605. break;
  606. default:
  607. printf("DDR:only CL 1.5, 2.0, 2.5, 3.0 is supported\n");
  608. return 0;
  609. }
  610. } else {
  611. mode_odt_enable = 0x0; /* Default disabled */
  612. if (odt_wr_cfg || odt_rd_cfg) {
  613. /*
  614. * Bits 6 and 2 in Extended MRS(1)
  615. * Bit 2 == 0x04 == 75 Ohm, with 2 DIMM modules.
  616. * Bit 6 == 0x40 == 150 Ohm, with 1 DIMM module.
  617. */
  618. mode_odt_enable = 0x40; /* 150 Ohm */
  619. }
  620. ddr->sdram_mode =
  621. (0
  622. | (1 << (16 + 10)) /* DQS Differential disable */
  623. #ifdef CONFIG_SYS_DDR_MODE_WEAK
  624. | (1 << (16 + 1)) /* weak driver (~60%) */
  625. #endif
  626. | (add_lat << (16 + 3)) /* Additive Latency in EMRS1 */
  627. | (mode_odt_enable << 16) /* ODT Enable in EMRS1 */
  628. | ((twr_clk - 1) << 9) /* Write Recovery Autopre */
  629. | (caslat << 4) /* caslat */
  630. | (burstlen << 0) /* Burst length */
  631. );
  632. }
  633. debug("DDR:sdram_mode=0x%08x\n", ddr->sdram_mode);
  634. /*
  635. * Clear EMRS2 and EMRS3.
  636. */
  637. ddr->sdram_mode2 = 0;
  638. debug("DDR: sdram_mode2 = 0x%08x\n", ddr->sdram_mode2);
  639. switch (spd.refresh) {
  640. case 0x00:
  641. case 0x80:
  642. refresh_clk = picos_to_clk(15625000);
  643. break;
  644. case 0x01:
  645. case 0x81:
  646. refresh_clk = picos_to_clk(3900000);
  647. break;
  648. case 0x02:
  649. case 0x82:
  650. refresh_clk = picos_to_clk(7800000);
  651. break;
  652. case 0x03:
  653. case 0x83:
  654. refresh_clk = picos_to_clk(31300000);
  655. break;
  656. case 0x04:
  657. case 0x84:
  658. refresh_clk = picos_to_clk(62500000);
  659. break;
  660. case 0x05:
  661. case 0x85:
  662. refresh_clk = picos_to_clk(125000000);
  663. break;
  664. default:
  665. refresh_clk = 0x512;
  666. break;
  667. }
  668. /*
  669. * Set BSTOPRE to 0x100 for page mode
  670. * If auto-charge is used, set BSTOPRE = 0
  671. */
  672. ddr->sdram_interval = ((refresh_clk & 0x3fff) << 16) | 0x100;
  673. debug("DDR:sdram_interval=0x%08x\n", ddr->sdram_interval);
  674. /*
  675. * SDRAM Cfg 2
  676. */
  677. odt_cfg = 0;
  678. #ifndef CONFIG_NEVER_ASSERT_ODT_TO_CPU
  679. if (odt_rd_cfg | odt_wr_cfg) {
  680. odt_cfg = 0x2; /* ODT to IOs during reads */
  681. }
  682. #endif
  683. if (spd.mem_type == SPD_MEMTYPE_DDR2) {
  684. ddr->sdram_cfg2 = (0
  685. | (0 << 26) /* True DQS */
  686. | (odt_cfg << 21) /* ODT only read */
  687. | (1 << 12) /* 1 refresh at a time */
  688. );
  689. debug("DDR: sdram_cfg2 = 0x%08x\n", ddr->sdram_cfg2);
  690. }
  691. #ifdef CONFIG_SYS_DDR_SDRAM_CLK_CNTL /* Optional platform specific value */
  692. ddr->sdram_clk_cntl = CONFIG_SYS_DDR_SDRAM_CLK_CNTL;
  693. #endif
  694. debug("DDR:sdram_clk_cntl=0x%08x\n", ddr->sdram_clk_cntl);
  695. asm("sync;isync");
  696. udelay(600);
  697. /*
  698. * Figure out the settings for the sdram_cfg register. Build up
  699. * the value in 'sdram_cfg' before writing since the write into
  700. * the register will actually enable the memory controller, and all
  701. * settings must be done before enabling.
  702. *
  703. * sdram_cfg[0] = 1 (ddr sdram logic enable)
  704. * sdram_cfg[1] = 1 (self-refresh-enable)
  705. * sdram_cfg[5:7] = (SDRAM type = DDR SDRAM)
  706. * 010 DDR 1 SDRAM
  707. * 011 DDR 2 SDRAM
  708. * sdram_cfg[12] = 0 (32_BE =0 , 64 bit bus mode)
  709. * sdram_cfg[13] = 0 (8_BE =0, 4-beat bursts)
  710. */
  711. if (spd.mem_type == SPD_MEMTYPE_DDR)
  712. sdram_type = SDRAM_CFG_SDRAM_TYPE_DDR1;
  713. else
  714. sdram_type = SDRAM_CFG_SDRAM_TYPE_DDR2;
  715. sdram_cfg = (0
  716. | SDRAM_CFG_MEM_EN /* DDR enable */
  717. | SDRAM_CFG_SREN /* Self refresh */
  718. | sdram_type /* SDRAM type */
  719. );
  720. /* sdram_cfg[3] = RD_EN - registered DIMM enable */
  721. if (spd.mod_attr & 0x02)
  722. sdram_cfg |= SDRAM_CFG_RD_EN;
  723. /* The DIMM is 32bit width */
  724. if (spd.dataw_lsb < 64) {
  725. if (spd.mem_type == SPD_MEMTYPE_DDR)
  726. sdram_cfg |= SDRAM_CFG_32_BE | SDRAM_CFG_8_BE;
  727. if (spd.mem_type == SPD_MEMTYPE_DDR2)
  728. sdram_cfg |= SDRAM_CFG_32_BE;
  729. }
  730. ddrc_ecc_enable = 0;
  731. #if defined(CONFIG_DDR_ECC)
  732. /* Enable ECC with sdram_cfg[2] */
  733. if (spd.config == 0x02) {
  734. sdram_cfg |= 0x20000000;
  735. ddrc_ecc_enable = 1;
  736. /* disable error detection */
  737. ddr->err_disable = ~ECC_ERROR_ENABLE;
  738. /* set single bit error threshold to maximum value,
  739. * reset counter to zero */
  740. ddr->err_sbe = (255 << ECC_ERROR_MAN_SBET_SHIFT) |
  741. (0 << ECC_ERROR_MAN_SBEC_SHIFT);
  742. }
  743. debug("DDR:err_disable=0x%08x\n", ddr->err_disable);
  744. debug("DDR:err_sbe=0x%08x\n", ddr->err_sbe);
  745. #endif
  746. debug(" DDRC ECC mode: %s\n", ddrc_ecc_enable ? "ON":"OFF");
  747. #if defined(CONFIG_DDR_2T_TIMING)
  748. /*
  749. * Enable 2T timing by setting sdram_cfg[16].
  750. */
  751. sdram_cfg |= SDRAM_CFG_2T_EN;
  752. #endif
  753. /* Enable controller, and GO! */
  754. ddr->sdram_cfg = sdram_cfg;
  755. asm("sync;isync");
  756. udelay(500);
  757. debug("DDR:sdram_cfg=0x%08x\n", ddr->sdram_cfg);
  758. return memsize; /*in MBytes*/
  759. }
  760. #endif /* CONFIG_SPD_EEPROM */
  761. #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
  762. /*
  763. * Use timebase counter, get_timer() is not available
  764. * at this point of initialization yet.
  765. */
  766. static __inline__ unsigned long get_tbms (void)
  767. {
  768. unsigned long tbl;
  769. unsigned long tbu1, tbu2;
  770. unsigned long ms;
  771. unsigned long long tmp;
  772. ulong tbclk = get_tbclk();
  773. /* get the timebase ticks */
  774. do {
  775. asm volatile ("mftbu %0":"=r" (tbu1):);
  776. asm volatile ("mftb %0":"=r" (tbl):);
  777. asm volatile ("mftbu %0":"=r" (tbu2):);
  778. } while (tbu1 != tbu2);
  779. /* convert ticks to ms */
  780. tmp = (unsigned long long)(tbu1);
  781. tmp = (tmp << 32);
  782. tmp += (unsigned long long)(tbl);
  783. ms = tmp/(tbclk/1000);
  784. return ms;
  785. }
  786. /*
  787. * Initialize all of memory for ECC, then enable errors.
  788. */
  789. void ddr_enable_ecc(unsigned int dram_size)
  790. {
  791. volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
  792. volatile ddr83xx_t *ddr= &immap->ddr;
  793. unsigned long t_start, t_end;
  794. register u64 *p;
  795. register uint size;
  796. unsigned int pattern[2];
  797. icache_enable();
  798. t_start = get_tbms();
  799. pattern[0] = 0xdeadbeef;
  800. pattern[1] = 0xdeadbeef;
  801. #if defined(CONFIG_DDR_ECC_INIT_VIA_DMA)
  802. dma_meminit(pattern[0], dram_size);
  803. #else
  804. debug("ddr init: CPU FP write method\n");
  805. size = dram_size;
  806. for (p = 0; p < (u64*)(size); p++) {
  807. ppcDWstore((u32*)p, pattern);
  808. }
  809. __asm__ __volatile__ ("sync");
  810. #endif
  811. t_end = get_tbms();
  812. icache_disable();
  813. debug("\nREADY!!\n");
  814. debug("ddr init duration: %ld ms\n", t_end - t_start);
  815. /* Clear All ECC Errors */
  816. if ((ddr->err_detect & ECC_ERROR_DETECT_MME) == ECC_ERROR_DETECT_MME)
  817. ddr->err_detect |= ECC_ERROR_DETECT_MME;
  818. if ((ddr->err_detect & ECC_ERROR_DETECT_MBE) == ECC_ERROR_DETECT_MBE)
  819. ddr->err_detect |= ECC_ERROR_DETECT_MBE;
  820. if ((ddr->err_detect & ECC_ERROR_DETECT_SBE) == ECC_ERROR_DETECT_SBE)
  821. ddr->err_detect |= ECC_ERROR_DETECT_SBE;
  822. if ((ddr->err_detect & ECC_ERROR_DETECT_MSE) == ECC_ERROR_DETECT_MSE)
  823. ddr->err_detect |= ECC_ERROR_DETECT_MSE;
  824. /* Disable ECC-Interrupts */
  825. ddr->err_int_en &= ECC_ERR_INT_DISABLE;
  826. /* Enable errors for ECC */
  827. ddr->err_disable &= ECC_ERROR_ENABLE;
  828. __asm__ __volatile__ ("sync");
  829. __asm__ __volatile__ ("isync");
  830. }
  831. #endif /* CONFIG_DDR_ECC */
  832. #endif /* !CONFIG_MPC83XX_SDRAM */