pinctrl-mvebu.c 6.4 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright (C) 2016 Marvell International Ltd.
  4. * https://spdx.org/licenses
  5. */
  6. #include <common.h>
  7. #include <config.h>
  8. #include <fdtdec.h>
  9. #include <errno.h>
  10. #include <dm.h>
  11. #include <log.h>
  12. #include <dm/pinctrl.h>
  13. #include <dm/root.h>
  14. #include <asm/system.h>
  15. #include <asm/io.h>
  16. #include <asm/arch-armada8k/soc-info.h>
  17. #include <linux/bitops.h>
  18. #include "pinctrl-mvebu.h"
  19. #define AP_EMMC_PHY_CTRL_REG 0x100
  20. #define CP_EMMC_PHY_CTRL_REG 0x424
  21. #define EMMC_PHY_CTRL_SDPHY_EN BIT(0)
  22. #define AP806_EMMC_CLK_PIN_ID 0
  23. #define AP806_EMMC_CLK_FUNC 0x1
  24. #define CP110_EMMC_CLK_PIN_ID 56
  25. #define CP110_EMMC_CLK_FUNC 0xe
  26. DECLARE_GLOBAL_DATA_PTR;
  27. /* mvebu_pinctl_emmc_set_mux: configure sd/mmc PHY mux
  28. * To enable SDIO/eMMC in Armada-APN806/CP110, need to configure PHY mux.
  29. * eMMC/SD PHY register responsible for muxing between MPPs and SD/eMMC
  30. * controller:
  31. * - Bit0 enabled SDIO/eMMC PHY is used as a MPP muxltiplexer,
  32. * - Bit0 disabled SDIO/eMMC PHY is connected to SDIO/eMMC controller
  33. * If pin function is set to eMMC/SD, then configure the eMMC/SD PHY
  34. * muxltiplexer register to be on SDIO/eMMC controller
  35. */
  36. void mvebu_pinctl_emmc_set_mux(struct udevice *dev, u32 pin, u32 func)
  37. {
  38. const void *blob = gd->fdt_blob;
  39. int node = dev_of_offset(dev);
  40. struct mvebu_pinctrl_priv *priv = dev_get_priv(dev);
  41. if (!fdt_node_check_compatible(blob, node, "marvell,ap806-pinctrl")) {
  42. if ((pin == AP806_EMMC_CLK_PIN_ID) &&
  43. (func == AP806_EMMC_CLK_FUNC)) {
  44. clrbits_le32(priv->base_reg + AP_EMMC_PHY_CTRL_REG,
  45. EMMC_PHY_CTRL_SDPHY_EN);
  46. }
  47. } else if (!fdt_node_check_compatible(blob, node,
  48. "marvell,armada-8k-cpm-pinctrl")) {
  49. if ((pin == CP110_EMMC_CLK_PIN_ID) &&
  50. (func == CP110_EMMC_CLK_FUNC)) {
  51. clrbits_le32(priv->base_reg + CP_EMMC_PHY_CTRL_REG,
  52. EMMC_PHY_CTRL_SDPHY_EN);
  53. }
  54. }
  55. }
  56. /*
  57. * mvebu_pinctrl_set_state: configure pin functions.
  58. * @dev: the pinctrl device to be configured.
  59. * @config: the state to be configured.
  60. * @return: 0 in success
  61. */
  62. int mvebu_pinctrl_set_state(struct udevice *dev, struct udevice *config)
  63. {
  64. const void *blob = gd->fdt_blob;
  65. int node = dev_of_offset(config);
  66. struct mvebu_pinctrl_priv *priv;
  67. u32 pin_arr[MVEBU_MAX_PINS_PER_BANK];
  68. u32 function;
  69. int i, pin_count;
  70. priv = dev_get_priv(dev);
  71. pin_count = fdtdec_get_int_array_count(blob, node,
  72. "marvell,pins",
  73. pin_arr,
  74. MVEBU_MAX_PINS_PER_BANK);
  75. if (pin_count <= 0) {
  76. debug("Failed reading pins array for pinconfig %s (%d)\n",
  77. config->name, pin_count);
  78. return -EINVAL;
  79. }
  80. function = fdtdec_get_int(blob, node, "marvell,function", 0xff);
  81. /*
  82. * Check if setup of PHY mux is needed for this pins group.
  83. * Only the first pin id in array is tested, all the rest use the same
  84. * pin function.
  85. */
  86. mvebu_pinctl_emmc_set_mux(dev, pin_arr[0], function);
  87. for (i = 0; i < pin_count; i++) {
  88. int reg_offset;
  89. int field_offset;
  90. int pin = pin_arr[i];
  91. if (function > priv->max_func) {
  92. debug("Illegal function %d for pinconfig %s\n",
  93. function, config->name);
  94. return -EINVAL;
  95. }
  96. /* Calculate register address and bit in register */
  97. reg_offset = priv->reg_direction * 4 *
  98. (pin >> (PIN_REG_SHIFT));
  99. field_offset = (BITS_PER_PIN) * (pin & PIN_FIELD_MASK);
  100. clrsetbits_le32(priv->base_reg + reg_offset,
  101. PIN_FUNC_MASK << field_offset,
  102. (function & PIN_FUNC_MASK) << field_offset);
  103. }
  104. return 0;
  105. }
  106. /*
  107. * mvebu_pinctrl_set_state_all: configure the entire bank pin functions.
  108. * @dev: the pinctrl device to be configured.
  109. * @config: the state to be configured.
  110. * @return: 0 in success
  111. */
  112. static int mvebu_pinctrl_set_state_all(struct udevice *dev,
  113. struct udevice *config)
  114. {
  115. const void *blob = gd->fdt_blob;
  116. int node = dev_of_offset(config);
  117. struct mvebu_pinctrl_priv *priv;
  118. u32 func_arr[MVEBU_MAX_PINS_PER_BANK];
  119. int pin, err;
  120. priv = dev_get_priv(dev);
  121. err = fdtdec_get_int_array(blob, node, "pin-func",
  122. func_arr, priv->pin_cnt);
  123. if (err) {
  124. debug("Failed reading pin functions for bank %s\n",
  125. priv->bank_name);
  126. return -EINVAL;
  127. }
  128. /* Check if setup of PHY mux is needed for this pins group. */
  129. if (priv->pin_cnt < CP110_EMMC_CLK_PIN_ID)
  130. mvebu_pinctl_emmc_set_mux(dev, AP806_EMMC_CLK_PIN_ID,
  131. func_arr[AP806_EMMC_CLK_PIN_ID]);
  132. else
  133. mvebu_pinctl_emmc_set_mux(dev, CP110_EMMC_CLK_PIN_ID,
  134. func_arr[CP110_EMMC_CLK_PIN_ID]);
  135. for (pin = 0; pin < priv->pin_cnt; pin++) {
  136. int reg_offset;
  137. int field_offset;
  138. u32 func = func_arr[pin];
  139. /* Bypass pins with function 0xFF */
  140. if (func == 0xff) {
  141. debug("Warning: pin %d value is not modified ", pin);
  142. debug("(kept as default)\n");
  143. continue;
  144. } else if (func > priv->max_func) {
  145. debug("Illegal function %d for pin %d\n", func, pin);
  146. return -EINVAL;
  147. }
  148. /* Calculate register address and bit in register */
  149. reg_offset = priv->reg_direction * 4 *
  150. (pin >> (PIN_REG_SHIFT));
  151. field_offset = (BITS_PER_PIN) * (pin & PIN_FIELD_MASK);
  152. clrsetbits_le32(priv->base_reg + reg_offset,
  153. PIN_FUNC_MASK << field_offset,
  154. (func & PIN_FUNC_MASK) << field_offset);
  155. }
  156. return 0;
  157. }
  158. int mvebu_pinctl_probe(struct udevice *dev)
  159. {
  160. const void *blob = gd->fdt_blob;
  161. int node = dev_of_offset(dev);
  162. struct mvebu_pinctrl_priv *priv;
  163. priv = dev_get_priv(dev);
  164. if (!priv) {
  165. debug("%s: Failed to get private\n", __func__);
  166. return -EINVAL;
  167. }
  168. priv->base_reg = dev_read_addr_ptr(dev);
  169. if (!priv->base_reg) {
  170. debug("%s: Failed to get base address\n", __func__);
  171. return -EINVAL;
  172. }
  173. priv->pin_cnt = fdtdec_get_int(blob, node, "pin-count",
  174. MVEBU_MAX_PINS_PER_BANK);
  175. priv->max_func = fdtdec_get_int(blob, node, "max-func",
  176. MVEBU_MAX_FUNC);
  177. priv->bank_name = fdt_getprop(blob, node, "bank-name", NULL);
  178. priv->reg_direction = 1;
  179. if (fdtdec_get_bool(blob, node, "reverse-reg"))
  180. priv->reg_direction = -1;
  181. return mvebu_pinctrl_set_state_all(dev, dev);
  182. }
  183. static struct pinctrl_ops mvebu_pinctrl_ops = {
  184. .set_state = mvebu_pinctrl_set_state
  185. };
  186. static const struct udevice_id mvebu_pinctrl_ids[] = {
  187. { .compatible = "marvell,mvebu-pinctrl" },
  188. { .compatible = "marvell,ap806-pinctrl" },
  189. { .compatible = "marvell,armada-7k-pinctrl" },
  190. { .compatible = "marvell,armada-8k-cpm-pinctrl" },
  191. { .compatible = "marvell,armada-8k-cps-pinctrl" },
  192. { }
  193. };
  194. U_BOOT_DRIVER(pinctrl_mvebu) = {
  195. .name = "mvebu_pinctrl",
  196. .id = UCLASS_PINCTRL,
  197. .of_match = mvebu_pinctrl_ids,
  198. .priv_auto_alloc_size = sizeof(struct mvebu_pinctrl_priv),
  199. .ops = &mvebu_pinctrl_ops,
  200. .probe = mvebu_pinctl_probe
  201. };