clk_ast2500.c 14 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532
  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * (C) Copyright 2016 Google, Inc
  4. */
  5. #include <common.h>
  6. #include <clk-uclass.h>
  7. #include <dm.h>
  8. #include <log.h>
  9. #include <asm/io.h>
  10. #include <asm/arch/scu_ast2500.h>
  11. #include <dm/lists.h>
  12. #include <dt-bindings/clock/ast2500-scu.h>
  13. #include <linux/delay.h>
  14. #include <linux/err.h>
  15. /*
  16. * MAC Clock Delay settings, taken from Aspeed SDK
  17. */
  18. #define RGMII_TXCLK_ODLY 8
  19. #define RMII_RXCLK_IDLY 2
  20. /*
  21. * TGMII Clock Duty constants, taken from Aspeed SDK
  22. */
  23. #define RGMII2_TXCK_DUTY 0x66
  24. #define RGMII1_TXCK_DUTY 0x64
  25. #define D2PLL_DEFAULT_RATE (250 * 1000 * 1000)
  26. DECLARE_GLOBAL_DATA_PTR;
  27. /*
  28. * Clock divider/multiplier configuration struct.
  29. * For H-PLL and M-PLL the formula is
  30. * (Output Frequency) = CLKIN * ((M + 1) / (N + 1)) / (P + 1)
  31. * M - Numerator
  32. * N - Denumerator
  33. * P - Post Divider
  34. * They have the same layout in their control register.
  35. *
  36. * D-PLL and D2-PLL have extra divider (OD + 1), which is not
  37. * yet needed and ignored by clock configurations.
  38. */
  39. struct ast2500_div_config {
  40. unsigned int num;
  41. unsigned int denum;
  42. unsigned int post_div;
  43. };
  44. /*
  45. * Get the rate of the M-PLL clock from input clock frequency and
  46. * the value of the M-PLL Parameter Register.
  47. */
  48. static ulong ast2500_get_mpll_rate(ulong clkin, u32 mpll_reg)
  49. {
  50. const ulong num = (mpll_reg & SCU_MPLL_NUM_MASK) >> SCU_MPLL_NUM_SHIFT;
  51. const ulong denum = (mpll_reg & SCU_MPLL_DENUM_MASK)
  52. >> SCU_MPLL_DENUM_SHIFT;
  53. const ulong post_div = (mpll_reg & SCU_MPLL_POST_MASK)
  54. >> SCU_MPLL_POST_SHIFT;
  55. return (clkin * ((num + 1) / (denum + 1))) / (post_div + 1);
  56. }
  57. /*
  58. * Get the rate of the H-PLL clock from input clock frequency and
  59. * the value of the H-PLL Parameter Register.
  60. */
  61. static ulong ast2500_get_hpll_rate(ulong clkin, u32 hpll_reg)
  62. {
  63. const ulong num = (hpll_reg & SCU_HPLL_NUM_MASK) >> SCU_HPLL_NUM_SHIFT;
  64. const ulong denum = (hpll_reg & SCU_HPLL_DENUM_MASK)
  65. >> SCU_HPLL_DENUM_SHIFT;
  66. const ulong post_div = (hpll_reg & SCU_HPLL_POST_MASK)
  67. >> SCU_HPLL_POST_SHIFT;
  68. return (clkin * ((num + 1) / (denum + 1))) / (post_div + 1);
  69. }
  70. static ulong ast2500_get_clkin(struct ast2500_scu *scu)
  71. {
  72. return readl(&scu->hwstrap) & SCU_HWSTRAP_CLKIN_25MHZ
  73. ? 25 * 1000 * 1000 : 24 * 1000 * 1000;
  74. }
  75. /**
  76. * Get current rate or uart clock
  77. *
  78. * @scu SCU registers
  79. * @uart_index UART index, 1-5
  80. *
  81. * @return current setting for uart clock rate
  82. */
  83. static ulong ast2500_get_uart_clk_rate(struct ast2500_scu *scu, int uart_index)
  84. {
  85. /*
  86. * ast2500 datasheet is very confusing when it comes to UART clocks,
  87. * especially when CLKIN = 25 MHz. The settings are in
  88. * different registers and it is unclear how they interact.
  89. *
  90. * This has only been tested with default settings and CLKIN = 24 MHz.
  91. */
  92. ulong uart_clkin;
  93. if (readl(&scu->misc_ctrl2) &
  94. (1 << (uart_index - 1 + SCU_MISC2_UARTCLK_SHIFT)))
  95. uart_clkin = 192 * 1000 * 1000;
  96. else
  97. uart_clkin = 24 * 1000 * 1000;
  98. if (readl(&scu->misc_ctrl1) & SCU_MISC_UARTCLK_DIV13)
  99. uart_clkin /= 13;
  100. return uart_clkin;
  101. }
  102. static ulong ast2500_clk_get_rate(struct clk *clk)
  103. {
  104. struct ast2500_clk_priv *priv = dev_get_priv(clk->dev);
  105. ulong clkin = ast2500_get_clkin(priv->scu);
  106. ulong rate;
  107. switch (clk->id) {
  108. case PLL_HPLL:
  109. case ARMCLK:
  110. /*
  111. * This ignores dynamic/static slowdown of ARMCLK and may
  112. * be inaccurate.
  113. */
  114. rate = ast2500_get_hpll_rate(clkin,
  115. readl(&priv->scu->h_pll_param));
  116. break;
  117. case MCLK_DDR:
  118. rate = ast2500_get_mpll_rate(clkin,
  119. readl(&priv->scu->m_pll_param));
  120. break;
  121. case BCLK_PCLK:
  122. {
  123. ulong apb_div = 4 + 4 * ((readl(&priv->scu->clk_sel1)
  124. & SCU_PCLK_DIV_MASK)
  125. >> SCU_PCLK_DIV_SHIFT);
  126. rate = ast2500_get_hpll_rate(clkin,
  127. readl(&priv->
  128. scu->h_pll_param));
  129. rate = rate / apb_div;
  130. }
  131. break;
  132. case BCLK_SDCLK:
  133. {
  134. ulong apb_div = 4 + 4 * ((readl(&priv->scu->clk_sel1)
  135. & SCU_SDCLK_DIV_MASK)
  136. >> SCU_SDCLK_DIV_SHIFT);
  137. rate = ast2500_get_hpll_rate(clkin,
  138. readl(&priv->
  139. scu->h_pll_param));
  140. rate = rate / apb_div;
  141. }
  142. break;
  143. case PCLK_UART1:
  144. rate = ast2500_get_uart_clk_rate(priv->scu, 1);
  145. break;
  146. case PCLK_UART2:
  147. rate = ast2500_get_uart_clk_rate(priv->scu, 2);
  148. break;
  149. case PCLK_UART3:
  150. rate = ast2500_get_uart_clk_rate(priv->scu, 3);
  151. break;
  152. case PCLK_UART4:
  153. rate = ast2500_get_uart_clk_rate(priv->scu, 4);
  154. break;
  155. case PCLK_UART5:
  156. rate = ast2500_get_uart_clk_rate(priv->scu, 5);
  157. break;
  158. default:
  159. return -ENOENT;
  160. }
  161. return rate;
  162. }
  163. struct ast2500_clock_config {
  164. ulong input_rate;
  165. ulong rate;
  166. struct ast2500_div_config cfg;
  167. };
  168. static const struct ast2500_clock_config ast2500_clock_config_defaults[] = {
  169. { 24000000, 250000000, { .num = 124, .denum = 1, .post_div = 5 } },
  170. };
  171. static bool ast2500_get_clock_config_default(ulong input_rate,
  172. ulong requested_rate,
  173. struct ast2500_div_config *cfg)
  174. {
  175. int i;
  176. for (i = 0; i < ARRAY_SIZE(ast2500_clock_config_defaults); i++) {
  177. const struct ast2500_clock_config *default_cfg =
  178. &ast2500_clock_config_defaults[i];
  179. if (default_cfg->input_rate == input_rate &&
  180. default_cfg->rate == requested_rate) {
  181. *cfg = default_cfg->cfg;
  182. return true;
  183. }
  184. }
  185. return false;
  186. }
  187. /*
  188. * @input_rate - the rate of input clock in Hz
  189. * @requested_rate - desired output rate in Hz
  190. * @div - this is an IN/OUT parameter, at input all fields of the config
  191. * need to be set to their maximum allowed values.
  192. * The result (the best config we could find), would also be returned
  193. * in this structure.
  194. *
  195. * @return The clock rate, when the resulting div_config is used.
  196. */
  197. static ulong ast2500_calc_clock_config(ulong input_rate, ulong requested_rate,
  198. struct ast2500_div_config *cfg)
  199. {
  200. /*
  201. * The assumption is that kHz precision is good enough and
  202. * also enough to avoid overflow when multiplying.
  203. */
  204. const ulong input_rate_khz = input_rate / 1000;
  205. const ulong rate_khz = requested_rate / 1000;
  206. const struct ast2500_div_config max_vals = *cfg;
  207. struct ast2500_div_config it = { 0, 0, 0 };
  208. ulong delta = rate_khz;
  209. ulong new_rate_khz = 0;
  210. /*
  211. * Look for a well known frequency first.
  212. */
  213. if (ast2500_get_clock_config_default(input_rate, requested_rate, cfg))
  214. return requested_rate;
  215. for (; it.denum <= max_vals.denum; ++it.denum) {
  216. for (it.post_div = 0; it.post_div <= max_vals.post_div;
  217. ++it.post_div) {
  218. it.num = (rate_khz * (it.post_div + 1) / input_rate_khz)
  219. * (it.denum + 1);
  220. if (it.num > max_vals.num)
  221. continue;
  222. new_rate_khz = (input_rate_khz
  223. * ((it.num + 1) / (it.denum + 1)))
  224. / (it.post_div + 1);
  225. /* Keep the rate below requested one. */
  226. if (new_rate_khz > rate_khz)
  227. continue;
  228. if (new_rate_khz - rate_khz < delta) {
  229. delta = new_rate_khz - rate_khz;
  230. *cfg = it;
  231. if (delta == 0)
  232. return new_rate_khz * 1000;
  233. }
  234. }
  235. }
  236. return new_rate_khz * 1000;
  237. }
  238. static ulong ast2500_configure_ddr(struct ast2500_scu *scu, ulong rate)
  239. {
  240. ulong clkin = ast2500_get_clkin(scu);
  241. u32 mpll_reg;
  242. struct ast2500_div_config div_cfg = {
  243. .num = (SCU_MPLL_NUM_MASK >> SCU_MPLL_NUM_SHIFT),
  244. .denum = (SCU_MPLL_DENUM_MASK >> SCU_MPLL_DENUM_SHIFT),
  245. .post_div = (SCU_MPLL_POST_MASK >> SCU_MPLL_POST_SHIFT),
  246. };
  247. ast2500_calc_clock_config(clkin, rate, &div_cfg);
  248. mpll_reg = readl(&scu->m_pll_param);
  249. mpll_reg &= ~(SCU_MPLL_POST_MASK | SCU_MPLL_NUM_MASK
  250. | SCU_MPLL_DENUM_MASK);
  251. mpll_reg |= (div_cfg.post_div << SCU_MPLL_POST_SHIFT)
  252. | (div_cfg.num << SCU_MPLL_NUM_SHIFT)
  253. | (div_cfg.denum << SCU_MPLL_DENUM_SHIFT);
  254. ast_scu_unlock(scu);
  255. writel(mpll_reg, &scu->m_pll_param);
  256. ast_scu_lock(scu);
  257. return ast2500_get_mpll_rate(clkin, mpll_reg);
  258. }
  259. static ulong ast2500_configure_mac(struct ast2500_scu *scu, int index)
  260. {
  261. ulong clkin = ast2500_get_clkin(scu);
  262. ulong hpll_rate = ast2500_get_hpll_rate(clkin,
  263. readl(&scu->h_pll_param));
  264. ulong required_rate;
  265. u32 hwstrap;
  266. u32 divisor;
  267. u32 reset_bit;
  268. u32 clkstop_bit;
  269. /*
  270. * According to data sheet, for 10/100 mode the MAC clock frequency
  271. * should be at least 25MHz and for 1000 mode at least 100MHz
  272. */
  273. hwstrap = readl(&scu->hwstrap);
  274. if (hwstrap & (SCU_HWSTRAP_MAC1_RGMII | SCU_HWSTRAP_MAC2_RGMII))
  275. required_rate = 100 * 1000 * 1000;
  276. else
  277. required_rate = 25 * 1000 * 1000;
  278. divisor = hpll_rate / required_rate;
  279. if (divisor < 4) {
  280. /* Clock can't run fast enough, but let's try anyway */
  281. debug("MAC clock too slow\n");
  282. divisor = 4;
  283. } else if (divisor > 16) {
  284. /* Can't slow down the clock enough, but let's try anyway */
  285. debug("MAC clock too fast\n");
  286. divisor = 16;
  287. }
  288. switch (index) {
  289. case 1:
  290. reset_bit = SCU_SYSRESET_MAC1;
  291. clkstop_bit = SCU_CLKSTOP_MAC1;
  292. break;
  293. case 2:
  294. reset_bit = SCU_SYSRESET_MAC2;
  295. clkstop_bit = SCU_CLKSTOP_MAC2;
  296. break;
  297. default:
  298. return -EINVAL;
  299. }
  300. ast_scu_unlock(scu);
  301. clrsetbits_le32(&scu->clk_sel1, SCU_MACCLK_MASK,
  302. ((divisor - 2) / 2) << SCU_MACCLK_SHIFT);
  303. /*
  304. * Disable MAC, start its clock and re-enable it.
  305. * The procedure and the delays (100us & 10ms) are
  306. * specified in the datasheet.
  307. */
  308. setbits_le32(&scu->sysreset_ctrl1, reset_bit);
  309. udelay(100);
  310. clrbits_le32(&scu->clk_stop_ctrl1, clkstop_bit);
  311. mdelay(10);
  312. clrbits_le32(&scu->sysreset_ctrl1, reset_bit);
  313. writel((RGMII2_TXCK_DUTY << SCU_CLKDUTY_RGMII2TXCK_SHIFT)
  314. | (RGMII1_TXCK_DUTY << SCU_CLKDUTY_RGMII1TXCK_SHIFT),
  315. &scu->clk_duty_sel);
  316. ast_scu_lock(scu);
  317. return required_rate;
  318. }
  319. static ulong ast2500_configure_d2pll(struct ast2500_scu *scu, ulong rate)
  320. {
  321. /*
  322. * The values and the meaning of the next three
  323. * parameters are undocumented. Taken from Aspeed SDK.
  324. *
  325. * TODO(clg@kaod.org): the SIP and SIC values depend on the
  326. * Numerator value
  327. */
  328. const u32 d2_pll_ext_param = 0x2c;
  329. const u32 d2_pll_sip = 0x11;
  330. const u32 d2_pll_sic = 0x18;
  331. u32 clk_delay_settings =
  332. (RMII_RXCLK_IDLY << SCU_MICDS_MAC1RMII_RDLY_SHIFT)
  333. | (RMII_RXCLK_IDLY << SCU_MICDS_MAC2RMII_RDLY_SHIFT)
  334. | (RGMII_TXCLK_ODLY << SCU_MICDS_MAC1RGMII_TXDLY_SHIFT)
  335. | (RGMII_TXCLK_ODLY << SCU_MICDS_MAC2RGMII_TXDLY_SHIFT);
  336. struct ast2500_div_config div_cfg = {
  337. .num = SCU_D2PLL_NUM_MASK >> SCU_D2PLL_NUM_SHIFT,
  338. .denum = SCU_D2PLL_DENUM_MASK >> SCU_D2PLL_DENUM_SHIFT,
  339. .post_div = SCU_D2PLL_POST_MASK >> SCU_D2PLL_POST_SHIFT,
  340. };
  341. ulong clkin = ast2500_get_clkin(scu);
  342. ulong new_rate;
  343. ast_scu_unlock(scu);
  344. writel((d2_pll_ext_param << SCU_D2PLL_EXT1_PARAM_SHIFT)
  345. | SCU_D2PLL_EXT1_OFF
  346. | SCU_D2PLL_EXT1_RESET, &scu->d2_pll_ext_param[0]);
  347. /*
  348. * Select USB2.0 port1 PHY clock as a clock source for GCRT.
  349. * This would disconnect it from D2-PLL.
  350. */
  351. clrsetbits_le32(&scu->misc_ctrl1, SCU_MISC_D2PLL_OFF,
  352. SCU_MISC_GCRT_USB20CLK);
  353. new_rate = ast2500_calc_clock_config(clkin, rate, &div_cfg);
  354. writel((d2_pll_sip << SCU_D2PLL_SIP_SHIFT)
  355. | (d2_pll_sic << SCU_D2PLL_SIC_SHIFT)
  356. | (div_cfg.num << SCU_D2PLL_NUM_SHIFT)
  357. | (div_cfg.denum << SCU_D2PLL_DENUM_SHIFT)
  358. | (div_cfg.post_div << SCU_D2PLL_POST_SHIFT),
  359. &scu->d2_pll_param);
  360. clrbits_le32(&scu->d2_pll_ext_param[0],
  361. SCU_D2PLL_EXT1_OFF | SCU_D2PLL_EXT1_RESET);
  362. clrsetbits_le32(&scu->misc_ctrl2,
  363. SCU_MISC2_RGMII_HPLL | SCU_MISC2_RMII_MPLL
  364. | SCU_MISC2_RGMII_CLKDIV_MASK |
  365. SCU_MISC2_RMII_CLKDIV_MASK,
  366. (4 << SCU_MISC2_RMII_CLKDIV_SHIFT));
  367. writel(clk_delay_settings | SCU_MICDS_RGMIIPLL, &scu->mac_clk_delay);
  368. writel(clk_delay_settings, &scu->mac_clk_delay_100M);
  369. writel(clk_delay_settings, &scu->mac_clk_delay_10M);
  370. ast_scu_lock(scu);
  371. return new_rate;
  372. }
  373. static ulong ast2500_clk_set_rate(struct clk *clk, ulong rate)
  374. {
  375. struct ast2500_clk_priv *priv = dev_get_priv(clk->dev);
  376. ulong new_rate;
  377. switch (clk->id) {
  378. case PLL_MPLL:
  379. case MCLK_DDR:
  380. new_rate = ast2500_configure_ddr(priv->scu, rate);
  381. break;
  382. case PLL_D2PLL:
  383. new_rate = ast2500_configure_d2pll(priv->scu, rate);
  384. break;
  385. default:
  386. return -ENOENT;
  387. }
  388. return new_rate;
  389. }
  390. static int ast2500_clk_enable(struct clk *clk)
  391. {
  392. struct ast2500_clk_priv *priv = dev_get_priv(clk->dev);
  393. switch (clk->id) {
  394. case BCLK_SDCLK:
  395. if (readl(&priv->scu->clk_stop_ctrl1) & SCU_CLKSTOP_SDCLK) {
  396. ast_scu_unlock(priv->scu);
  397. setbits_le32(&priv->scu->sysreset_ctrl1,
  398. SCU_SYSRESET_SDIO);
  399. udelay(100);
  400. clrbits_le32(&priv->scu->clk_stop_ctrl1,
  401. SCU_CLKSTOP_SDCLK);
  402. mdelay(10);
  403. clrbits_le32(&priv->scu->sysreset_ctrl1,
  404. SCU_SYSRESET_SDIO);
  405. ast_scu_lock(priv->scu);
  406. }
  407. break;
  408. /*
  409. * For MAC clocks the clock rate is
  410. * configured based on whether RGMII or RMII mode has been selected
  411. * through hardware strapping.
  412. */
  413. case PCLK_MAC1:
  414. ast2500_configure_mac(priv->scu, 1);
  415. break;
  416. case PCLK_MAC2:
  417. ast2500_configure_mac(priv->scu, 2);
  418. break;
  419. case PLL_D2PLL:
  420. ast2500_configure_d2pll(priv->scu, D2PLL_DEFAULT_RATE);
  421. break;
  422. default:
  423. return -ENOENT;
  424. }
  425. return 0;
  426. }
  427. struct clk_ops ast2500_clk_ops = {
  428. .get_rate = ast2500_clk_get_rate,
  429. .set_rate = ast2500_clk_set_rate,
  430. .enable = ast2500_clk_enable,
  431. };
  432. static int ast2500_clk_ofdata_to_platdata(struct udevice *dev)
  433. {
  434. struct ast2500_clk_priv *priv = dev_get_priv(dev);
  435. priv->scu = dev_read_addr_ptr(dev);
  436. if (!priv->scu)
  437. return -EINVAL;
  438. return 0;
  439. }
  440. static int ast2500_clk_bind(struct udevice *dev)
  441. {
  442. int ret;
  443. /* The reset driver does not have a device node, so bind it here */
  444. ret = device_bind_driver(gd->dm_root, "ast_sysreset", "reset", &dev);
  445. if (ret)
  446. debug("Warning: No reset driver: ret=%d\n", ret);
  447. return 0;
  448. }
  449. static const struct udevice_id ast2500_clk_ids[] = {
  450. { .compatible = "aspeed,ast2500-scu" },
  451. { }
  452. };
  453. U_BOOT_DRIVER(aspeed_ast2500_scu) = {
  454. .name = "aspeed_ast2500_scu",
  455. .id = UCLASS_CLK,
  456. .of_match = ast2500_clk_ids,
  457. .priv_auto_alloc_size = sizeof(struct ast2500_clk_priv),
  458. .ops = &ast2500_clk_ops,
  459. .bind = ast2500_clk_bind,
  460. .ofdata_to_platdata = ast2500_clk_ofdata_to_platdata,
  461. };