tap_delays.c 6.7 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Xilinx ZynqMP SoC Tap Delay Programming
  4. *
  5. * Copyright (C) 2018 Xilinx, Inc.
  6. */
  7. #include <common.h>
  8. #include <asm/arch/sys_proto.h>
  9. #define SD_DLL_CTRL 0xFF180358
  10. #define SD_ITAP_DLY 0xFF180314
  11. #define SD_OTAP_DLY 0xFF180318
  12. #define SD0_DLL_RST_MASK 0x00000004
  13. #define SD0_DLL_RST 0x00000004
  14. #define SD1_DLL_RST_MASK 0x00040000
  15. #define SD1_DLL_RST 0x00040000
  16. #define SD0_ITAPCHGWIN_MASK 0x00000200
  17. #define SD0_ITAPCHGWIN 0x00000200
  18. #define SD1_ITAPCHGWIN_MASK 0x02000000
  19. #define SD1_ITAPCHGWIN 0x02000000
  20. #define SD0_ITAPDLYENA_MASK 0x00000100
  21. #define SD0_ITAPDLYENA 0x00000100
  22. #define SD1_ITAPDLYENA_MASK 0x01000000
  23. #define SD1_ITAPDLYENA 0x01000000
  24. #define SD0_ITAPDLYSEL_MASK 0x000000FF
  25. #define SD0_ITAPDLYSEL_HSD 0x00000015
  26. #define SD0_ITAPDLYSEL_SD_DDR50 0x0000003D
  27. #define SD0_ITAPDLYSEL_MMC_DDR50 0x00000012
  28. #define SD1_ITAPDLYSEL_MASK 0x00FF0000
  29. #define SD1_ITAPDLYSEL_HSD 0x00150000
  30. #define SD1_ITAPDLYSEL_SD_DDR50 0x003D0000
  31. #define SD1_ITAPDLYSEL_MMC_DDR50 0x00120000
  32. #define SD0_OTAPDLYSEL_MASK 0x0000003F
  33. #define SD0_OTAPDLYSEL_MMC_HSD 0x00000006
  34. #define SD0_OTAPDLYSEL_SD_HSD 0x00000005
  35. #define SD0_OTAPDLYSEL_SDR50 0x00000003
  36. #define SD0_OTAPDLYSEL_SDR104_B0 0x00000003
  37. #define SD0_OTAPDLYSEL_SDR104_B2 0x00000002
  38. #define SD0_OTAPDLYSEL_SD_DDR50 0x00000004
  39. #define SD0_OTAPDLYSEL_MMC_DDR50 0x00000006
  40. #define SD1_OTAPDLYSEL_MASK 0x003F0000
  41. #define SD1_OTAPDLYSEL_MMC_HSD 0x00060000
  42. #define SD1_OTAPDLYSEL_SD_HSD 0x00050000
  43. #define SD1_OTAPDLYSEL_SDR50 0x00030000
  44. #define SD1_OTAPDLYSEL_SDR104_B0 0x00030000
  45. #define SD1_OTAPDLYSEL_SDR104_B2 0x00020000
  46. #define SD1_OTAPDLYSEL_SD_DDR50 0x00040000
  47. #define SD1_OTAPDLYSEL_MMC_DDR50 0x00060000
  48. #define MMC_BANK2 0x2
  49. #define MMC_TIMING_UHS_SDR25 1
  50. #define MMC_TIMING_UHS_SDR50 2
  51. #define MMC_TIMING_UHS_SDR104 3
  52. #define MMC_TIMING_UHS_DDR50 4
  53. #define MMC_TIMING_MMC_HS200 5
  54. #define MMC_TIMING_SD_HS 6
  55. #define MMC_TIMING_MMC_DDR52 7
  56. #define MMC_TIMING_MMC_HS 8
  57. void zynqmp_dll_reset(u8 deviceid)
  58. {
  59. /* Issue DLL Reset */
  60. if (deviceid == 0)
  61. zynqmp_mmio_write(SD_DLL_CTRL, SD0_DLL_RST_MASK,
  62. SD0_DLL_RST);
  63. else
  64. zynqmp_mmio_write(SD_DLL_CTRL, SD1_DLL_RST_MASK,
  65. SD1_DLL_RST);
  66. mdelay(1);
  67. /* Release DLL Reset */
  68. if (deviceid == 0)
  69. zynqmp_mmio_write(SD_DLL_CTRL, SD0_DLL_RST_MASK, 0x0);
  70. else
  71. zynqmp_mmio_write(SD_DLL_CTRL, SD1_DLL_RST_MASK, 0x0);
  72. }
  73. static void arasan_zynqmp_tap_sdr104(u8 deviceid, u8 timing, u8 bank)
  74. {
  75. if (deviceid == 0) {
  76. /* Program OTAP */
  77. if (bank == MMC_BANK2)
  78. zynqmp_mmio_write(SD_OTAP_DLY, SD0_OTAPDLYSEL_MASK,
  79. SD0_OTAPDLYSEL_SDR104_B2);
  80. else
  81. zynqmp_mmio_write(SD_OTAP_DLY, SD0_OTAPDLYSEL_MASK,
  82. SD0_OTAPDLYSEL_SDR104_B0);
  83. } else {
  84. /* Program OTAP */
  85. if (bank == MMC_BANK2)
  86. zynqmp_mmio_write(SD_OTAP_DLY, SD1_OTAPDLYSEL_MASK,
  87. SD1_OTAPDLYSEL_SDR104_B2);
  88. else
  89. zynqmp_mmio_write(SD_OTAP_DLY, SD1_OTAPDLYSEL_MASK,
  90. SD1_OTAPDLYSEL_SDR104_B0);
  91. }
  92. }
  93. static void arasan_zynqmp_tap_hs(u8 deviceid, u8 timing, u8 bank)
  94. {
  95. if (deviceid == 0) {
  96. /* Program ITAP */
  97. zynqmp_mmio_write(SD_ITAP_DLY, SD0_ITAPCHGWIN_MASK,
  98. SD0_ITAPCHGWIN);
  99. zynqmp_mmio_write(SD_ITAP_DLY, SD0_ITAPDLYENA_MASK,
  100. SD0_ITAPDLYENA);
  101. zynqmp_mmio_write(SD_ITAP_DLY, SD0_ITAPDLYSEL_MASK,
  102. SD0_ITAPDLYSEL_HSD);
  103. zynqmp_mmio_write(SD_ITAP_DLY, SD0_ITAPCHGWIN_MASK, 0x0);
  104. /* Program OTAP */
  105. if (timing == MMC_TIMING_MMC_HS)
  106. zynqmp_mmio_write(SD_OTAP_DLY, SD0_OTAPDLYSEL_MASK,
  107. SD0_OTAPDLYSEL_MMC_HSD);
  108. else
  109. zynqmp_mmio_write(SD_OTAP_DLY, SD0_OTAPDLYSEL_MASK,
  110. SD0_OTAPDLYSEL_SD_HSD);
  111. } else {
  112. /* Program ITAP */
  113. zynqmp_mmio_write(SD_ITAP_DLY, SD1_ITAPCHGWIN_MASK,
  114. SD1_ITAPCHGWIN);
  115. zynqmp_mmio_write(SD_ITAP_DLY, SD1_ITAPDLYENA_MASK,
  116. SD1_ITAPDLYENA);
  117. zynqmp_mmio_write(SD_ITAP_DLY, SD1_ITAPDLYSEL_MASK,
  118. SD1_ITAPDLYSEL_HSD);
  119. zynqmp_mmio_write(SD_ITAP_DLY, SD1_ITAPCHGWIN_MASK, 0x0);
  120. /* Program OTAP */
  121. if (timing == MMC_TIMING_MMC_HS)
  122. zynqmp_mmio_write(SD_OTAP_DLY, SD1_OTAPDLYSEL_MASK,
  123. SD1_OTAPDLYSEL_MMC_HSD);
  124. else
  125. zynqmp_mmio_write(SD_OTAP_DLY, SD1_OTAPDLYSEL_MASK,
  126. SD1_OTAPDLYSEL_SD_HSD);
  127. }
  128. }
  129. static void arasan_zynqmp_tap_ddr50(u8 deviceid, u8 timing, u8 bank)
  130. {
  131. if (deviceid == 0) {
  132. /* Program ITAP */
  133. zynqmp_mmio_write(SD_ITAP_DLY, SD0_ITAPCHGWIN_MASK,
  134. SD0_ITAPCHGWIN);
  135. zynqmp_mmio_write(SD_ITAP_DLY, SD0_ITAPDLYENA_MASK,
  136. SD0_ITAPDLYENA);
  137. if (timing == MMC_TIMING_UHS_DDR50)
  138. zynqmp_mmio_write(SD_ITAP_DLY, SD0_ITAPDLYSEL_MASK,
  139. SD0_ITAPDLYSEL_SD_DDR50);
  140. else
  141. zynqmp_mmio_write(SD_ITAP_DLY, SD0_ITAPDLYSEL_MASK,
  142. SD0_ITAPDLYSEL_MMC_DDR50);
  143. zynqmp_mmio_write(SD_ITAP_DLY, SD0_ITAPCHGWIN_MASK, 0x0);
  144. /* Program OTAP */
  145. if (timing == MMC_TIMING_UHS_DDR50)
  146. zynqmp_mmio_write(SD_OTAP_DLY, SD0_OTAPDLYSEL_MASK,
  147. SD0_OTAPDLYSEL_SD_DDR50);
  148. else
  149. zynqmp_mmio_write(SD_OTAP_DLY, SD0_OTAPDLYSEL_MASK,
  150. SD0_OTAPDLYSEL_MMC_DDR50);
  151. } else {
  152. /* Program ITAP */
  153. zynqmp_mmio_write(SD_ITAP_DLY, SD1_ITAPCHGWIN_MASK,
  154. SD1_ITAPCHGWIN);
  155. zynqmp_mmio_write(SD_ITAP_DLY, SD1_ITAPDLYENA_MASK,
  156. SD1_ITAPDLYENA);
  157. if (timing == MMC_TIMING_UHS_DDR50)
  158. zynqmp_mmio_write(SD_ITAP_DLY, SD1_ITAPDLYSEL_MASK,
  159. SD1_ITAPDLYSEL_SD_DDR50);
  160. else
  161. zynqmp_mmio_write(SD_ITAP_DLY, SD1_ITAPDLYSEL_MASK,
  162. SD1_ITAPDLYSEL_MMC_DDR50);
  163. zynqmp_mmio_write(SD_ITAP_DLY, SD1_ITAPCHGWIN_MASK, 0x0);
  164. /* Program OTAP */
  165. if (timing == MMC_TIMING_UHS_DDR50)
  166. zynqmp_mmio_write(SD_OTAP_DLY, SD1_OTAPDLYSEL_MASK,
  167. SD1_OTAPDLYSEL_SD_DDR50);
  168. else
  169. zynqmp_mmio_write(SD_OTAP_DLY, SD1_OTAPDLYSEL_MASK,
  170. SD1_OTAPDLYSEL_MMC_DDR50);
  171. }
  172. }
  173. static void arasan_zynqmp_tap_sdr50(u8 deviceid, u8 timing, u8 bank)
  174. {
  175. if (deviceid == 0) {
  176. /* Program OTAP */
  177. zynqmp_mmio_write(SD_OTAP_DLY, SD0_OTAPDLYSEL_MASK,
  178. SD0_OTAPDLYSEL_SDR50);
  179. } else {
  180. /* Program OTAP */
  181. zynqmp_mmio_write(SD_OTAP_DLY, SD1_OTAPDLYSEL_MASK,
  182. SD1_OTAPDLYSEL_SDR50);
  183. }
  184. }
  185. void arasan_zynqmp_set_tapdelay(u8 deviceid, u8 timing, u8 bank)
  186. {
  187. if (deviceid == 0)
  188. zynqmp_mmio_write(SD_DLL_CTRL, SD0_DLL_RST_MASK,
  189. SD0_DLL_RST);
  190. else
  191. zynqmp_mmio_write(SD_DLL_CTRL, SD1_DLL_RST_MASK,
  192. SD1_DLL_RST);
  193. switch (timing) {
  194. case MMC_TIMING_UHS_SDR25:
  195. arasan_zynqmp_tap_hs(deviceid, timing, bank);
  196. break;
  197. case MMC_TIMING_UHS_SDR50:
  198. arasan_zynqmp_tap_sdr50(deviceid, timing, bank);
  199. break;
  200. case MMC_TIMING_UHS_SDR104:
  201. case MMC_TIMING_MMC_HS200:
  202. arasan_zynqmp_tap_sdr104(deviceid, timing, bank);
  203. break;
  204. case MMC_TIMING_UHS_DDR50:
  205. arasan_zynqmp_tap_ddr50(deviceid, timing, bank);
  206. break;
  207. }
  208. if (deviceid == 0)
  209. zynqmp_mmio_write(SD_DLL_CTRL, SD0_DLL_RST_MASK, 0x0);
  210. else
  211. zynqmp_mmio_write(SD_DLL_CTRL, SD1_DLL_RST_MASK, 0x0);
  212. }