stm32mp1.c 21 KB

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  1. // SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
  2. /*
  3. * Copyright (C) 2018, STMicroelectronics - All Rights Reserved
  4. */
  5. #include <common.h>
  6. #include <adc.h>
  7. #include <bootm.h>
  8. #include <clk.h>
  9. #include <config.h>
  10. #include <dm.h>
  11. #include <env.h>
  12. #include <env_internal.h>
  13. #include <fdt_support.h>
  14. #include <g_dnl.h>
  15. #include <generic-phy.h>
  16. #include <hang.h>
  17. #include <i2c.h>
  18. #include <init.h>
  19. #include <led.h>
  20. #include <log.h>
  21. #include <malloc.h>
  22. #include <misc.h>
  23. #include <mtd_node.h>
  24. #include <net.h>
  25. #include <netdev.h>
  26. #include <phy.h>
  27. #include <remoteproc.h>
  28. #include <reset.h>
  29. #include <syscon.h>
  30. #include <usb.h>
  31. #include <watchdog.h>
  32. #include <asm/io.h>
  33. #include <asm/gpio.h>
  34. #include <asm/arch/stm32.h>
  35. #include <asm/arch/sys_proto.h>
  36. #include <jffs2/load_kernel.h>
  37. #include <linux/bitops.h>
  38. #include <linux/delay.h>
  39. #include <linux/err.h>
  40. #include <linux/iopoll.h>
  41. #include <power/regulator.h>
  42. #include <usb/dwc2_udc.h>
  43. #include "../../st/common/stusb160x.h"
  44. /* SYSCFG registers */
  45. #define SYSCFG_BOOTR 0x00
  46. #define SYSCFG_PMCSETR 0x04
  47. #define SYSCFG_IOCTRLSETR 0x18
  48. #define SYSCFG_ICNR 0x1C
  49. #define SYSCFG_CMPCR 0x20
  50. #define SYSCFG_CMPENSETR 0x24
  51. #define SYSCFG_PMCCLRR 0x44
  52. #define SYSCFG_BOOTR_BOOT_MASK GENMASK(2, 0)
  53. #define SYSCFG_BOOTR_BOOTPD_SHIFT 4
  54. #define SYSCFG_IOCTRLSETR_HSLVEN_TRACE BIT(0)
  55. #define SYSCFG_IOCTRLSETR_HSLVEN_QUADSPI BIT(1)
  56. #define SYSCFG_IOCTRLSETR_HSLVEN_ETH BIT(2)
  57. #define SYSCFG_IOCTRLSETR_HSLVEN_SDMMC BIT(3)
  58. #define SYSCFG_IOCTRLSETR_HSLVEN_SPI BIT(4)
  59. #define SYSCFG_CMPCR_SW_CTRL BIT(1)
  60. #define SYSCFG_CMPCR_READY BIT(8)
  61. #define SYSCFG_CMPENSETR_MPU_EN BIT(0)
  62. #define SYSCFG_PMCSETR_ETH_CLK_SEL BIT(16)
  63. #define SYSCFG_PMCSETR_ETH_REF_CLK_SEL BIT(17)
  64. #define SYSCFG_PMCSETR_ETH_SELMII BIT(20)
  65. #define SYSCFG_PMCSETR_ETH_SEL_MASK GENMASK(23, 21)
  66. #define SYSCFG_PMCSETR_ETH_SEL_GMII_MII 0
  67. #define SYSCFG_PMCSETR_ETH_SEL_RGMII BIT(21)
  68. #define SYSCFG_PMCSETR_ETH_SEL_RMII BIT(23)
  69. /*
  70. * Get a global data pointer
  71. */
  72. DECLARE_GLOBAL_DATA_PTR;
  73. #define USB_LOW_THRESHOLD_UV 200000
  74. #define USB_WARNING_LOW_THRESHOLD_UV 660000
  75. #define USB_START_LOW_THRESHOLD_UV 1230000
  76. #define USB_START_HIGH_THRESHOLD_UV 2150000
  77. int board_early_init_f(void)
  78. {
  79. /* nothing to do, only used in SPL */
  80. return 0;
  81. }
  82. int checkboard(void)
  83. {
  84. int ret;
  85. char *mode;
  86. u32 otp;
  87. struct udevice *dev;
  88. const char *fdt_compat;
  89. int fdt_compat_len;
  90. if (IS_ENABLED(CONFIG_TFABOOT))
  91. mode = "trusted";
  92. else
  93. mode = "basic";
  94. printf("Board: stm32mp1 in %s mode", mode);
  95. fdt_compat = fdt_getprop(gd->fdt_blob, 0, "compatible",
  96. &fdt_compat_len);
  97. if (fdt_compat && fdt_compat_len)
  98. printf(" (%s)", fdt_compat);
  99. puts("\n");
  100. /* display the STMicroelectronics board identification */
  101. if (CONFIG_IS_ENABLED(CMD_STBOARD)) {
  102. ret = uclass_get_device_by_driver(UCLASS_MISC,
  103. DM_GET_DRIVER(stm32mp_bsec),
  104. &dev);
  105. if (!ret)
  106. ret = misc_read(dev, STM32_BSEC_SHADOW(BSEC_OTP_BOARD),
  107. &otp, sizeof(otp));
  108. if (ret > 0 && otp)
  109. printf("Board: MB%04x Var%d.%d Rev.%c-%02d\n",
  110. otp >> 16,
  111. (otp >> 12) & 0xF,
  112. (otp >> 4) & 0xF,
  113. ((otp >> 8) & 0xF) - 1 + 'A',
  114. otp & 0xF);
  115. }
  116. return 0;
  117. }
  118. static void board_key_check(void)
  119. {
  120. ofnode node;
  121. struct gpio_desc gpio;
  122. enum forced_boot_mode boot_mode = BOOT_NORMAL;
  123. if (!IS_ENABLED(CONFIG_FASTBOOT) && !IS_ENABLED(CONFIG_CMD_STM32PROG))
  124. return;
  125. node = ofnode_path("/config");
  126. if (!ofnode_valid(node)) {
  127. debug("%s: no /config node?\n", __func__);
  128. return;
  129. }
  130. if (IS_ENABLED(CONFIG_FASTBOOT)) {
  131. if (gpio_request_by_name_nodev(node, "st,fastboot-gpios", 0,
  132. &gpio, GPIOD_IS_IN)) {
  133. debug("%s: could not find a /config/st,fastboot-gpios\n",
  134. __func__);
  135. } else {
  136. if (dm_gpio_get_value(&gpio)) {
  137. puts("Fastboot key pressed, ");
  138. boot_mode = BOOT_FASTBOOT;
  139. }
  140. dm_gpio_free(NULL, &gpio);
  141. }
  142. }
  143. if (IS_ENABLED(CONFIG_CMD_STM32PROG)) {
  144. if (gpio_request_by_name_nodev(node, "st,stm32prog-gpios", 0,
  145. &gpio, GPIOD_IS_IN)) {
  146. debug("%s: could not find a /config/st,stm32prog-gpios\n",
  147. __func__);
  148. } else {
  149. if (dm_gpio_get_value(&gpio)) {
  150. puts("STM32Programmer key pressed, ");
  151. boot_mode = BOOT_STM32PROG;
  152. }
  153. dm_gpio_free(NULL, &gpio);
  154. }
  155. }
  156. if (boot_mode != BOOT_NORMAL) {
  157. puts("entering download mode...\n");
  158. clrsetbits_le32(TAMP_BOOT_CONTEXT,
  159. TAMP_BOOT_FORCED_MASK,
  160. boot_mode);
  161. }
  162. }
  163. int g_dnl_board_usb_cable_connected(void)
  164. {
  165. struct udevice *dwc2_udc_otg;
  166. int ret;
  167. if (!IS_ENABLED(CONFIG_USB_GADGET_DWC2_OTG))
  168. return -ENODEV;
  169. /* if typec stusb160x is present, means DK1 or DK2 board */
  170. ret = stusb160x_cable_connected();
  171. if (ret >= 0)
  172. return ret;
  173. ret = uclass_get_device_by_driver(UCLASS_USB_GADGET_GENERIC,
  174. DM_GET_DRIVER(dwc2_udc_otg),
  175. &dwc2_udc_otg);
  176. if (!ret)
  177. debug("dwc2_udc_otg init failed\n");
  178. return dwc2_udc_B_session_valid(dwc2_udc_otg);
  179. }
  180. #ifdef CONFIG_USB_GADGET_DOWNLOAD
  181. #define STM32MP1_G_DNL_DFU_PRODUCT_NUM 0xdf11
  182. #define STM32MP1_G_DNL_FASTBOOT_PRODUCT_NUM 0x0afb
  183. int g_dnl_bind_fixup(struct usb_device_descriptor *dev, const char *name)
  184. {
  185. if (IS_ENABLED(CONFIG_DFU_OVER_USB) &&
  186. !strcmp(name, "usb_dnl_dfu"))
  187. put_unaligned(STM32MP1_G_DNL_DFU_PRODUCT_NUM, &dev->idProduct);
  188. else if (IS_ENABLED(CONFIG_FASTBOOT) &&
  189. !strcmp(name, "usb_dnl_fastboot"))
  190. put_unaligned(STM32MP1_G_DNL_FASTBOOT_PRODUCT_NUM,
  191. &dev->idProduct);
  192. else
  193. put_unaligned(CONFIG_USB_GADGET_PRODUCT_NUM, &dev->idProduct);
  194. return 0;
  195. }
  196. #endif /* CONFIG_USB_GADGET_DOWNLOAD */
  197. static int get_led(struct udevice **dev, char *led_string)
  198. {
  199. char *led_name;
  200. int ret;
  201. led_name = fdtdec_get_config_string(gd->fdt_blob, led_string);
  202. if (!led_name) {
  203. pr_debug("%s: could not find %s config string\n",
  204. __func__, led_string);
  205. return -ENOENT;
  206. }
  207. ret = led_get_by_label(led_name, dev);
  208. if (ret) {
  209. debug("%s: get=%d\n", __func__, ret);
  210. return ret;
  211. }
  212. return 0;
  213. }
  214. static int setup_led(enum led_state_t cmd)
  215. {
  216. struct udevice *dev;
  217. int ret;
  218. if (!CONFIG_IS_ENABLED(LED))
  219. return 0;
  220. ret = get_led(&dev, "u-boot,boot-led");
  221. if (ret)
  222. return ret;
  223. ret = led_set_state(dev, cmd);
  224. return ret;
  225. }
  226. static void __maybe_unused led_error_blink(u32 nb_blink)
  227. {
  228. int ret;
  229. struct udevice *led;
  230. u32 i;
  231. if (!nb_blink)
  232. return;
  233. if (CONFIG_IS_ENABLED(LED)) {
  234. ret = get_led(&led, "u-boot,error-led");
  235. if (!ret) {
  236. /* make u-boot,error-led blinking */
  237. /* if U32_MAX and 125ms interval, for 17.02 years */
  238. for (i = 0; i < 2 * nb_blink; i++) {
  239. led_set_state(led, LEDST_TOGGLE);
  240. mdelay(125);
  241. WATCHDOG_RESET();
  242. }
  243. led_set_state(led, LEDST_ON);
  244. }
  245. }
  246. /* infinite: the boot process must be stopped */
  247. if (nb_blink == U32_MAX)
  248. hang();
  249. }
  250. static int board_check_usb_power(void)
  251. {
  252. struct ofnode_phandle_args adc_args;
  253. struct udevice *adc;
  254. ofnode node;
  255. unsigned int raw;
  256. int max_uV = 0;
  257. int min_uV = USB_START_HIGH_THRESHOLD_UV;
  258. int ret, uV, adc_count;
  259. u32 nb_blink;
  260. u8 i;
  261. if (!IS_ENABLED(CONFIG_ADC))
  262. return -ENODEV;
  263. node = ofnode_path("/config");
  264. if (!ofnode_valid(node)) {
  265. debug("%s: no /config node?\n", __func__);
  266. return -ENOENT;
  267. }
  268. /*
  269. * Retrieve the ADC channels devices and get measurement
  270. * for each of them
  271. */
  272. adc_count = ofnode_count_phandle_with_args(node, "st,adc_usb_pd",
  273. "#io-channel-cells");
  274. if (adc_count < 0) {
  275. if (adc_count == -ENOENT)
  276. return 0;
  277. pr_err("%s: can't find adc channel (%d)\n", __func__,
  278. adc_count);
  279. return adc_count;
  280. }
  281. for (i = 0; i < adc_count; i++) {
  282. if (ofnode_parse_phandle_with_args(node, "st,adc_usb_pd",
  283. "#io-channel-cells", 0, i,
  284. &adc_args)) {
  285. pr_debug("%s: can't find /config/st,adc_usb_pd\n",
  286. __func__);
  287. return 0;
  288. }
  289. ret = uclass_get_device_by_ofnode(UCLASS_ADC, adc_args.node,
  290. &adc);
  291. if (ret) {
  292. pr_err("%s: Can't get adc device(%d)\n", __func__,
  293. ret);
  294. return ret;
  295. }
  296. ret = adc_channel_single_shot(adc->name, adc_args.args[0],
  297. &raw);
  298. if (ret) {
  299. pr_err("%s: single shot failed for %s[%d]!\n",
  300. __func__, adc->name, adc_args.args[0]);
  301. return ret;
  302. }
  303. /* Convert to uV */
  304. if (!adc_raw_to_uV(adc, raw, &uV)) {
  305. if (uV > max_uV)
  306. max_uV = uV;
  307. if (uV < min_uV)
  308. min_uV = uV;
  309. pr_debug("%s: %s[%02d] = %u, %d uV\n", __func__,
  310. adc->name, adc_args.args[0], raw, uV);
  311. } else {
  312. pr_err("%s: Can't get uV value for %s[%d]\n",
  313. __func__, adc->name, adc_args.args[0]);
  314. }
  315. }
  316. /*
  317. * If highest value is inside 1.23 Volts and 2.10 Volts, that means
  318. * board is plugged on an USB-C 3A power supply and boot process can
  319. * continue.
  320. */
  321. if (max_uV > USB_START_LOW_THRESHOLD_UV &&
  322. max_uV <= USB_START_HIGH_THRESHOLD_UV &&
  323. min_uV <= USB_LOW_THRESHOLD_UV)
  324. return 0;
  325. pr_err("****************************************************\n");
  326. /*
  327. * If highest and lowest value are either both below
  328. * USB_LOW_THRESHOLD_UV or both above USB_LOW_THRESHOLD_UV, that
  329. * means USB TYPE-C is in unattached mode, this is an issue, make
  330. * u-boot,error-led blinking and stop boot process.
  331. */
  332. if ((max_uV > USB_LOW_THRESHOLD_UV &&
  333. min_uV > USB_LOW_THRESHOLD_UV) ||
  334. (max_uV <= USB_LOW_THRESHOLD_UV &&
  335. min_uV <= USB_LOW_THRESHOLD_UV)) {
  336. pr_err("* ERROR USB TYPE-C connection in unattached mode *\n");
  337. pr_err("* Check that USB TYPE-C cable is correctly plugged *\n");
  338. /* with 125ms interval, led will blink for 17.02 years ....*/
  339. nb_blink = U32_MAX;
  340. }
  341. if (max_uV > USB_LOW_THRESHOLD_UV &&
  342. max_uV <= USB_WARNING_LOW_THRESHOLD_UV &&
  343. min_uV <= USB_LOW_THRESHOLD_UV) {
  344. pr_err("* WARNING 500mA power supply detected *\n");
  345. nb_blink = 2;
  346. }
  347. if (max_uV > USB_WARNING_LOW_THRESHOLD_UV &&
  348. max_uV <= USB_START_LOW_THRESHOLD_UV &&
  349. min_uV <= USB_LOW_THRESHOLD_UV) {
  350. pr_err("* WARNING 1.5A power supply detected *\n");
  351. nb_blink = 3;
  352. }
  353. /*
  354. * If highest value is above 2.15 Volts that means that the USB TypeC
  355. * supplies more than 3 Amp, this is not compliant with TypeC specification
  356. */
  357. if (max_uV > USB_START_HIGH_THRESHOLD_UV) {
  358. pr_err("* USB TYPE-C charger not compliant with *\n");
  359. pr_err("* specification *\n");
  360. pr_err("****************************************************\n\n");
  361. /* with 125ms interval, led will blink for 17.02 years ....*/
  362. nb_blink = U32_MAX;
  363. } else {
  364. pr_err("* Current too low, use a 3A power supply! *\n");
  365. pr_err("****************************************************\n\n");
  366. }
  367. led_error_blink(nb_blink);
  368. return 0;
  369. }
  370. static void sysconf_init(void)
  371. {
  372. u8 *syscfg;
  373. struct udevice *pwr_dev;
  374. struct udevice *pwr_reg;
  375. struct udevice *dev;
  376. u32 otp = 0;
  377. int ret;
  378. u32 bootr, val;
  379. syscfg = (u8 *)syscon_get_first_range(STM32MP_SYSCON_SYSCFG);
  380. /* interconnect update : select master using the port 1 */
  381. /* LTDC = AXI_M9 */
  382. /* GPU = AXI_M8 */
  383. /* today information is hardcoded in U-Boot */
  384. writel(BIT(9), syscfg + SYSCFG_ICNR);
  385. /* disable Pull-Down for boot pin connected to VDD */
  386. bootr = readl(syscfg + SYSCFG_BOOTR);
  387. bootr &= ~(SYSCFG_BOOTR_BOOT_MASK << SYSCFG_BOOTR_BOOTPD_SHIFT);
  388. bootr |= (bootr & SYSCFG_BOOTR_BOOT_MASK) << SYSCFG_BOOTR_BOOTPD_SHIFT;
  389. writel(bootr, syscfg + SYSCFG_BOOTR);
  390. /* High Speed Low Voltage Pad mode Enable for SPI, SDMMC, ETH, QSPI
  391. * and TRACE. Needed above ~50MHz and conditioned by AFMUX selection.
  392. * The customer will have to disable this for low frequencies
  393. * or if AFMUX is selected but the function not used, typically for
  394. * TRACE. Otherwise, impact on power consumption.
  395. *
  396. * WARNING:
  397. * enabling High Speed mode while VDD>2.7V
  398. * with the OTP product_below_2v5 (OTP 18, BIT 13)
  399. * erroneously set to 1 can damage the IC!
  400. * => U-Boot set the register only if VDD < 2.7V (in DT)
  401. * but this value need to be consistent with board design
  402. */
  403. ret = uclass_get_device_by_driver(UCLASS_PMIC,
  404. DM_GET_DRIVER(stm32mp_pwr_pmic),
  405. &pwr_dev);
  406. if (!ret && IS_ENABLED(CONFIG_DM_REGULATOR)) {
  407. ret = uclass_get_device_by_driver(UCLASS_MISC,
  408. DM_GET_DRIVER(stm32mp_bsec),
  409. &dev);
  410. if (ret) {
  411. pr_err("Can't find stm32mp_bsec driver\n");
  412. return;
  413. }
  414. ret = misc_read(dev, STM32_BSEC_SHADOW(18), &otp, 4);
  415. if (ret > 0)
  416. otp = otp & BIT(13);
  417. /* get VDD = vdd-supply */
  418. ret = device_get_supply_regulator(pwr_dev, "vdd-supply",
  419. &pwr_reg);
  420. /* check if VDD is Low Voltage */
  421. if (!ret) {
  422. if (regulator_get_value(pwr_reg) < 2700000) {
  423. writel(SYSCFG_IOCTRLSETR_HSLVEN_TRACE |
  424. SYSCFG_IOCTRLSETR_HSLVEN_QUADSPI |
  425. SYSCFG_IOCTRLSETR_HSLVEN_ETH |
  426. SYSCFG_IOCTRLSETR_HSLVEN_SDMMC |
  427. SYSCFG_IOCTRLSETR_HSLVEN_SPI,
  428. syscfg + SYSCFG_IOCTRLSETR);
  429. if (!otp)
  430. pr_err("product_below_2v5=0: HSLVEN protected by HW\n");
  431. } else {
  432. if (otp)
  433. pr_err("product_below_2v5=1: HSLVEN update is destructive, no update as VDD>2.7V\n");
  434. }
  435. } else {
  436. debug("VDD unknown");
  437. }
  438. }
  439. /* activate automatic I/O compensation
  440. * warning: need to ensure CSI enabled and ready in clock driver
  441. */
  442. writel(SYSCFG_CMPENSETR_MPU_EN, syscfg + SYSCFG_CMPENSETR);
  443. /* poll until ready (1s timeout) */
  444. ret = readl_poll_timeout(syscfg + SYSCFG_CMPCR, val,
  445. val & SYSCFG_CMPCR_READY,
  446. 1000000);
  447. if (ret) {
  448. pr_err("SYSCFG: I/O compensation failed, timeout.\n");
  449. led_error_blink(10);
  450. }
  451. clrbits_le32(syscfg + SYSCFG_CMPCR, SYSCFG_CMPCR_SW_CTRL);
  452. }
  453. /* Fix to make I2C1 usable on DK2 for touchscreen usage in kernel */
  454. static int dk2_i2c1_fix(void)
  455. {
  456. ofnode node;
  457. struct gpio_desc hdmi, audio;
  458. int ret = 0;
  459. if (!IS_ENABLED(CONFIG_DM_REGULATOR))
  460. return -ENODEV;
  461. node = ofnode_path("/soc/i2c@40012000/hdmi-transmitter@39");
  462. if (!ofnode_valid(node)) {
  463. pr_debug("%s: no hdmi-transmitter@39 ?\n", __func__);
  464. return -ENOENT;
  465. }
  466. if (gpio_request_by_name_nodev(node, "reset-gpios", 0,
  467. &hdmi, GPIOD_IS_OUT)) {
  468. pr_debug("%s: could not find reset-gpios\n",
  469. __func__);
  470. return -ENOENT;
  471. }
  472. node = ofnode_path("/soc/i2c@40012000/cs42l51@4a");
  473. if (!ofnode_valid(node)) {
  474. pr_debug("%s: no cs42l51@4a ?\n", __func__);
  475. return -ENOENT;
  476. }
  477. if (gpio_request_by_name_nodev(node, "reset-gpios", 0,
  478. &audio, GPIOD_IS_OUT)) {
  479. pr_debug("%s: could not find reset-gpios\n",
  480. __func__);
  481. return -ENOENT;
  482. }
  483. /* before power up, insure that HDMI and AUDIO IC is under reset */
  484. ret = dm_gpio_set_value(&hdmi, 1);
  485. if (ret) {
  486. pr_err("%s: can't set_value for hdmi_nrst gpio", __func__);
  487. goto error;
  488. }
  489. ret = dm_gpio_set_value(&audio, 1);
  490. if (ret) {
  491. pr_err("%s: can't set_value for audio_nrst gpio", __func__);
  492. goto error;
  493. }
  494. /* power-up audio IC */
  495. regulator_autoset_by_name("v1v8_audio", NULL);
  496. /* power-up HDMI IC */
  497. regulator_autoset_by_name("v1v2_hdmi", NULL);
  498. regulator_autoset_by_name("v3v3_hdmi", NULL);
  499. error:
  500. return ret;
  501. }
  502. static bool board_is_dk2(void)
  503. {
  504. if (CONFIG_IS_ENABLED(TARGET_ST_STM32MP15x) &&
  505. of_machine_is_compatible("st,stm32mp157c-dk2"))
  506. return true;
  507. return false;
  508. }
  509. static bool board_is_ev1(void)
  510. {
  511. if (CONFIG_IS_ENABLED(TARGET_ST_STM32MP15x) &&
  512. (of_machine_is_compatible("st,stm32mp157a-ev1") ||
  513. of_machine_is_compatible("st,stm32mp157c-ev1") ||
  514. of_machine_is_compatible("st,stm32mp157d-ev1") ||
  515. of_machine_is_compatible("st,stm32mp157f-ev1")))
  516. return true;
  517. return false;
  518. }
  519. /* touchscreen driver: only used for pincontrol configuration */
  520. static const struct udevice_id goodix_ids[] = {
  521. { .compatible = "goodix,gt9147", },
  522. { }
  523. };
  524. U_BOOT_DRIVER(goodix) = {
  525. .name = "goodix",
  526. .id = UCLASS_NOP,
  527. .of_match = goodix_ids,
  528. };
  529. static void board_ev1_init(void)
  530. {
  531. struct udevice *dev;
  532. /* configure IRQ line on EV1 for touchscreen before LCD reset */
  533. uclass_get_device_by_driver(UCLASS_NOP, DM_GET_DRIVER(goodix), &dev);
  534. }
  535. /* board dependent setup after realloc */
  536. int board_init(void)
  537. {
  538. /* address of boot parameters */
  539. gd->bd->bi_boot_params = STM32_DDR_BASE + 0x100;
  540. if (CONFIG_IS_ENABLED(DM_GPIO_HOG))
  541. gpio_hog_probe_all();
  542. board_key_check();
  543. if (board_is_ev1())
  544. board_ev1_init();
  545. if (board_is_dk2())
  546. dk2_i2c1_fix();
  547. if (IS_ENABLED(CONFIG_DM_REGULATOR))
  548. regulators_enable_boot_on(_DEBUG);
  549. if (!IS_ENABLED(CONFIG_TFABOOT))
  550. sysconf_init();
  551. if (CONFIG_IS_ENABLED(LED))
  552. led_default_state();
  553. setup_led(LEDST_ON);
  554. return 0;
  555. }
  556. int board_late_init(void)
  557. {
  558. const void *fdt_compat;
  559. int fdt_compat_len;
  560. int ret;
  561. u32 otp;
  562. struct udevice *dev;
  563. char buf[10];
  564. char dtb_name[256];
  565. int buf_len;
  566. if (IS_ENABLED(CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG)) {
  567. fdt_compat = fdt_getprop(gd->fdt_blob, 0, "compatible",
  568. &fdt_compat_len);
  569. if (fdt_compat && fdt_compat_len) {
  570. if (strncmp(fdt_compat, "st,", 3) != 0) {
  571. env_set("board_name", fdt_compat);
  572. } else {
  573. env_set("board_name", fdt_compat + 3);
  574. buf_len = sizeof(dtb_name);
  575. strncpy(dtb_name, fdt_compat + 3, buf_len);
  576. buf_len -= strlen(fdt_compat + 3);
  577. strncat(dtb_name, ".dtb", buf_len);
  578. env_set("fdtfile", dtb_name);
  579. }
  580. }
  581. ret = uclass_get_device_by_driver(UCLASS_MISC,
  582. DM_GET_DRIVER(stm32mp_bsec),
  583. &dev);
  584. if (!ret)
  585. ret = misc_read(dev, STM32_BSEC_SHADOW(BSEC_OTP_BOARD),
  586. &otp, sizeof(otp));
  587. if (ret > 0 && otp) {
  588. snprintf(buf, sizeof(buf), "0x%04x", otp >> 16);
  589. env_set("board_id", buf);
  590. snprintf(buf, sizeof(buf), "0x%04x",
  591. ((otp >> 8) & 0xF) - 1 + 0xA);
  592. env_set("board_rev", buf);
  593. }
  594. }
  595. /* for DK1/DK2 boards */
  596. board_check_usb_power();
  597. return 0;
  598. }
  599. void board_quiesce_devices(void)
  600. {
  601. setup_led(LEDST_OFF);
  602. }
  603. /* eth init function : weak called in eqos driver */
  604. int board_interface_eth_init(struct udevice *dev,
  605. phy_interface_t interface_type)
  606. {
  607. u8 *syscfg;
  608. u32 value;
  609. bool eth_clk_sel_reg = false;
  610. bool eth_ref_clk_sel_reg = false;
  611. /* Gigabit Ethernet 125MHz clock selection. */
  612. eth_clk_sel_reg = dev_read_bool(dev, "st,eth_clk_sel");
  613. /* Ethernet 50Mhz RMII clock selection */
  614. eth_ref_clk_sel_reg =
  615. dev_read_bool(dev, "st,eth_ref_clk_sel");
  616. syscfg = (u8 *)syscon_get_first_range(STM32MP_SYSCON_SYSCFG);
  617. if (!syscfg)
  618. return -ENODEV;
  619. switch (interface_type) {
  620. case PHY_INTERFACE_MODE_MII:
  621. value = SYSCFG_PMCSETR_ETH_SEL_GMII_MII |
  622. SYSCFG_PMCSETR_ETH_REF_CLK_SEL;
  623. debug("%s: PHY_INTERFACE_MODE_MII\n", __func__);
  624. break;
  625. case PHY_INTERFACE_MODE_GMII:
  626. if (eth_clk_sel_reg)
  627. value = SYSCFG_PMCSETR_ETH_SEL_GMII_MII |
  628. SYSCFG_PMCSETR_ETH_CLK_SEL;
  629. else
  630. value = SYSCFG_PMCSETR_ETH_SEL_GMII_MII;
  631. debug("%s: PHY_INTERFACE_MODE_GMII\n", __func__);
  632. break;
  633. case PHY_INTERFACE_MODE_RMII:
  634. if (eth_ref_clk_sel_reg)
  635. value = SYSCFG_PMCSETR_ETH_SEL_RMII |
  636. SYSCFG_PMCSETR_ETH_REF_CLK_SEL;
  637. else
  638. value = SYSCFG_PMCSETR_ETH_SEL_RMII;
  639. debug("%s: PHY_INTERFACE_MODE_RMII\n", __func__);
  640. break;
  641. case PHY_INTERFACE_MODE_RGMII:
  642. case PHY_INTERFACE_MODE_RGMII_ID:
  643. case PHY_INTERFACE_MODE_RGMII_RXID:
  644. case PHY_INTERFACE_MODE_RGMII_TXID:
  645. if (eth_clk_sel_reg)
  646. value = SYSCFG_PMCSETR_ETH_SEL_RGMII |
  647. SYSCFG_PMCSETR_ETH_CLK_SEL;
  648. else
  649. value = SYSCFG_PMCSETR_ETH_SEL_RGMII;
  650. debug("%s: PHY_INTERFACE_MODE_RGMII\n", __func__);
  651. break;
  652. default:
  653. debug("%s: Do not manage %d interface\n",
  654. __func__, interface_type);
  655. /* Do not manage others interfaces */
  656. return -EINVAL;
  657. }
  658. /* clear and set ETH configuration bits */
  659. writel(SYSCFG_PMCSETR_ETH_SEL_MASK | SYSCFG_PMCSETR_ETH_SELMII |
  660. SYSCFG_PMCSETR_ETH_REF_CLK_SEL | SYSCFG_PMCSETR_ETH_CLK_SEL,
  661. syscfg + SYSCFG_PMCCLRR);
  662. writel(value, syscfg + SYSCFG_PMCSETR);
  663. return 0;
  664. }
  665. enum env_location env_get_location(enum env_operation op, int prio)
  666. {
  667. u32 bootmode = get_bootmode();
  668. if (prio)
  669. return ENVL_UNKNOWN;
  670. switch (bootmode & TAMP_BOOT_DEVICE_MASK) {
  671. case BOOT_FLASH_SD:
  672. case BOOT_FLASH_EMMC:
  673. if (CONFIG_IS_ENABLED(ENV_IS_IN_MMC))
  674. return ENVL_MMC;
  675. else if (CONFIG_IS_ENABLED(ENV_IS_IN_EXT4))
  676. return ENVL_EXT4;
  677. else
  678. return ENVL_NOWHERE;
  679. case BOOT_FLASH_NAND:
  680. case BOOT_FLASH_SPINAND:
  681. if (CONFIG_IS_ENABLED(ENV_IS_IN_UBI))
  682. return ENVL_UBI;
  683. else
  684. return ENVL_NOWHERE;
  685. case BOOT_FLASH_NOR:
  686. if (CONFIG_IS_ENABLED(ENV_IS_IN_SPI_FLASH))
  687. return ENVL_SPI_FLASH;
  688. else
  689. return ENVL_NOWHERE;
  690. default:
  691. return ENVL_NOWHERE;
  692. }
  693. }
  694. const char *env_ext4_get_intf(void)
  695. {
  696. u32 bootmode = get_bootmode();
  697. switch (bootmode & TAMP_BOOT_DEVICE_MASK) {
  698. case BOOT_FLASH_SD:
  699. case BOOT_FLASH_EMMC:
  700. return "mmc";
  701. default:
  702. return "";
  703. }
  704. }
  705. const char *env_ext4_get_dev_part(void)
  706. {
  707. static char *const dev_part[] = {"0:auto", "1:auto", "2:auto"};
  708. u32 bootmode = get_bootmode();
  709. return dev_part[(bootmode & TAMP_BOOT_INSTANCE_MASK) - 1];
  710. }
  711. int mmc_get_env_dev(void)
  712. {
  713. u32 bootmode = get_bootmode();
  714. return (bootmode & TAMP_BOOT_INSTANCE_MASK) - 1;
  715. }
  716. #if defined(CONFIG_OF_BOARD_SETUP)
  717. int ft_board_setup(void *blob, struct bd_info *bd)
  718. {
  719. static const struct node_info nodes[] = {
  720. { "st,stm32f469-qspi", MTD_DEV_TYPE_NOR, },
  721. { "st,stm32f469-qspi", MTD_DEV_TYPE_SPINAND},
  722. { "st,stm32mp15-fmc2", MTD_DEV_TYPE_NAND, },
  723. { "st,stm32mp1-fmc2-nfc", MTD_DEV_TYPE_NAND, },
  724. };
  725. if (IS_ENABLED(CONFIG_FDT_FIXUP_PARTITIONS))
  726. fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
  727. return 0;
  728. }
  729. #endif
  730. static void board_copro_image_process(ulong fw_image, size_t fw_size)
  731. {
  732. int ret, id = 0; /* Copro id fixed to 0 as only one coproc on mp1 */
  733. if (!rproc_is_initialized())
  734. if (rproc_init()) {
  735. printf("Remote Processor %d initialization failed\n",
  736. id);
  737. return;
  738. }
  739. ret = rproc_load(id, fw_image, fw_size);
  740. printf("Load Remote Processor %d with data@addr=0x%08lx %u bytes:%s\n",
  741. id, fw_image, fw_size, ret ? " Failed!" : " Success!");
  742. if (!ret)
  743. rproc_start(id);
  744. }
  745. U_BOOT_FIT_LOADABLE_HANDLER(IH_TYPE_COPRO, board_copro_image_process);