Kconfig 8.7 KB

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  1. #
  2. # Multifunction miscellaneous devices
  3. #
  4. menu "Multifunction device drivers"
  5. config MISC
  6. bool "Enable Driver Model for Misc drivers"
  7. depends on DM
  8. help
  9. Enable driver model for miscellaneous devices. This class is
  10. used only for those do not fit other more general classes. A
  11. set of generic read, write and ioctl methods may be used to
  12. access the device.
  13. config ALTERA_SYSID
  14. bool "Altera Sysid support"
  15. depends on MISC
  16. help
  17. Select this to enable a sysid for Altera devices. Please find
  18. details on the "Embedded Peripherals IP User Guide" of Altera.
  19. config ATSHA204A
  20. bool "Support for Atmel ATSHA204A module"
  21. depends on MISC
  22. help
  23. Enable support for I2C connected Atmel's ATSHA204A
  24. CryptoAuthentication module found for example on the Turris Omnia
  25. board.
  26. config ROCKCHIP_EFUSE
  27. bool "Rockchip e-fuse support"
  28. depends on MISC
  29. help
  30. Enable (read-only) access for the e-fuse block found in Rockchip
  31. SoCs: accesses can either be made using byte addressing and a length
  32. or through child-nodes that are generated based on the e-fuse map
  33. retrieved from the DTS.
  34. This driver currently supports the RK3399 only, but can easily be
  35. extended (by porting the read function from the Linux kernel sources)
  36. to support other recent Rockchip devices.
  37. config CMD_CROS_EC
  38. bool "Enable crosec command"
  39. depends on CROS_EC
  40. help
  41. Enable command-line access to the Chrome OS EC (Embedded
  42. Controller). This provides the 'crosec' command which has
  43. a number of sub-commands for performing EC tasks such as
  44. updating its flash, accessing a small saved context area
  45. and talking to the I2C bus behind the EC (if there is one).
  46. config CROS_EC
  47. bool "Enable Chrome OS EC"
  48. help
  49. Enable access to the Chrome OS EC. This is a separate
  50. microcontroller typically available on a SPI bus on Chromebooks. It
  51. provides access to the keyboard, some internal storage and may
  52. control access to the battery and main PMIC depending on the
  53. device. You can use the 'crosec' command to access it.
  54. config CROS_EC_I2C
  55. bool "Enable Chrome OS EC I2C driver"
  56. depends on CROS_EC
  57. help
  58. Enable I2C access to the Chrome OS EC. This is used on older
  59. ARM Chromebooks such as snow and spring before the standard bus
  60. changed to SPI. The EC will accept commands across the I2C using
  61. a special message protocol, and provide responses.
  62. config CROS_EC_LPC
  63. bool "Enable Chrome OS EC LPC driver"
  64. depends on CROS_EC
  65. help
  66. Enable I2C access to the Chrome OS EC. This is used on x86
  67. Chromebooks such as link and falco. The keyboard is provided
  68. through a legacy port interface, so on x86 machines the main
  69. function of the EC is power and thermal management.
  70. config CROS_EC_SANDBOX
  71. bool "Enable Chrome OS EC sandbox driver"
  72. depends on CROS_EC && SANDBOX
  73. help
  74. Enable a sandbox emulation of the Chrome OS EC. This supports
  75. keyboard (use the -l flag to enable the LCD), verified boot context,
  76. EC flash read/write/erase support and a few other things. It is
  77. enough to perform a Chrome OS verified boot on sandbox.
  78. config CROS_EC_SPI
  79. bool "Enable Chrome OS EC SPI driver"
  80. depends on CROS_EC
  81. help
  82. Enable SPI access to the Chrome OS EC. This is used on newer
  83. ARM Chromebooks such as pit, pi and nyan-big. The SPI interface
  84. provides a faster and more robust interface than I2C but the bugs
  85. are less interesting.
  86. config DS4510
  87. bool "Enable support for DS4510 CPU supervisor"
  88. help
  89. Enable support for the Maxim DS4510 CPU supervisor. It has an
  90. integrated 64-byte EEPROM, four programmable non-volatile I/O pins
  91. and a configurable timer for the supervisor function. The device is
  92. connected over I2C.
  93. config FSL_SEC_MON
  94. bool "Enable FSL SEC_MON Driver"
  95. help
  96. Freescale Security Monitor block is responsible for monitoring
  97. system states.
  98. Security Monitor can be transitioned on any security failures,
  99. like software violations or hardware security violations.
  100. config MXC_OCOTP
  101. bool "Enable MXC OCOTP Driver"
  102. help
  103. If you say Y here, you will get support for the One Time
  104. Programmable memory pages that are stored on the some
  105. Freescale i.MX processors.
  106. config NUVOTON_NCT6102D
  107. bool "Enable Nuvoton NCT6102D Super I/O driver"
  108. help
  109. If you say Y here, you will get support for the Nuvoton
  110. NCT6102D Super I/O driver. This can be used to enable or
  111. disable the legacy UART, the watchdog or other devices
  112. in the Nuvoton Super IO chips on X86 platforms.
  113. config PWRSEQ
  114. bool "Enable power-sequencing drivers"
  115. depends on DM
  116. help
  117. Power-sequencing drivers provide support for controlling power for
  118. devices. They are typically referenced by a phandle from another
  119. device. When the device is started up, its power sequence can be
  120. initiated.
  121. config SPL_PWRSEQ
  122. bool "Enable power-sequencing drivers for SPL"
  123. depends on PWRSEQ
  124. help
  125. Power-sequencing drivers provide support for controlling power for
  126. devices. They are typically referenced by a phandle from another
  127. device. When the device is started up, its power sequence can be
  128. initiated.
  129. config PCA9551_LED
  130. bool "Enable PCA9551 LED driver"
  131. help
  132. Enable driver for PCA9551 LED controller. This controller
  133. is connected via I2C. So I2C needs to be enabled.
  134. config PCA9551_I2C_ADDR
  135. hex "I2C address of PCA9551 LED controller"
  136. depends on PCA9551_LED
  137. default 0x60
  138. help
  139. The I2C address of the PCA9551 LED controller.
  140. config STM32MP_FUSE
  141. bool "Enable STM32MP fuse wrapper providing the fuse API"
  142. depends on ARCH_STM32MP && MISC
  143. default y if CMD_FUSE
  144. help
  145. If you say Y here, you will get support for the fuse API (OTP)
  146. for STM32MP architecture.
  147. This API is needed for CMD_FUSE.
  148. config STM32_RCC
  149. bool "Enable RCC driver for the STM32 SoC's family"
  150. depends on (STM32 || ARCH_STM32MP) && MISC
  151. help
  152. Enable the STM32 RCC driver. The RCC block (Reset and Clock Control
  153. block) is responsible of the management of the clock and reset
  154. generation.
  155. This driver is similar to an MFD driver in the Linux kernel.
  156. config TEGRA_CAR
  157. bool "Enable support for the Tegra CAR driver"
  158. depends on TEGRA_NO_BPMP
  159. help
  160. The Tegra CAR (Clock and Reset Controller) is a HW module that
  161. controls almost all clocks and resets in a Tegra SoC.
  162. config TEGRA186_BPMP
  163. bool "Enable support for the Tegra186 BPMP driver"
  164. depends on TEGRA186
  165. help
  166. The Tegra BPMP (Boot and Power Management Processor) is a separate
  167. auxiliary CPU embedded into Tegra to perform power management work,
  168. and controls related features such as clocks, resets, power domains,
  169. PMIC I2C bus, etc. This driver provides the core low-level
  170. communication path by which feature-specific drivers (such as clock)
  171. can make requests to the BPMP. This driver is similar to an MFD
  172. driver in the Linux kernel.
  173. config WINBOND_W83627
  174. bool "Enable Winbond Super I/O driver"
  175. help
  176. If you say Y here, you will get support for the Winbond
  177. W83627 Super I/O driver. This can be used to enable the
  178. legacy UART or other devices in the Winbond Super IO chips
  179. on X86 platforms.
  180. config QFW
  181. bool
  182. help
  183. Hidden option to enable QEMU fw_cfg interface. This will be selected by
  184. either CONFIG_CMD_QFW or CONFIG_GENERATE_ACPI_TABLE.
  185. config I2C_EEPROM
  186. bool "Enable driver for generic I2C-attached EEPROMs"
  187. depends on MISC
  188. help
  189. Enable a generic driver for EEPROMs attached via I2C.
  190. config SPL_I2C_EEPROM
  191. bool "Enable driver for generic I2C-attached EEPROMs for SPL"
  192. depends on MISC && SPL && SPL_DM
  193. help
  194. This option is an SPL-variant of the I2C_EEPROM option.
  195. See the help of I2C_EEPROM for details.
  196. config ZYNQ_GEM_I2C_MAC_OFFSET
  197. hex "Set the I2C MAC offset"
  198. default 0x0
  199. help
  200. Set the MAC offset for i2C.
  201. if I2C_EEPROM
  202. config SYS_I2C_EEPROM_ADDR
  203. hex "Chip address of the EEPROM device"
  204. default 0
  205. config SYS_I2C_EEPROM_BUS
  206. int "I2C bus of the EEPROM device."
  207. default 0
  208. config SYS_EEPROM_SIZE
  209. int "Size in bytes of the EEPROM device"
  210. default 256
  211. config SYS_EEPROM_PAGE_WRITE_BITS
  212. int "Number of bits used to address bytes in a single page"
  213. default 0
  214. help
  215. The EEPROM page size is 2^SYS_EEPROM_PAGE_WRITE_BITS.
  216. A 64 byte page, for example would require six bits.
  217. config SYS_EEPROM_PAGE_WRITE_DELAY_MS
  218. int "Number of milliseconds to delay between page writes"
  219. default 0
  220. config SYS_I2C_EEPROM_ADDR_LEN
  221. int "Length in bytes of the EEPROM memory array address"
  222. default 1
  223. help
  224. Note: This is NOT the chip address length!
  225. config SYS_I2C_EEPROM_ADDR_OVERFLOW
  226. hex "EEPROM Address Overflow"
  227. default 0
  228. help
  229. EEPROM chips that implement "address overflow" are ones
  230. like Catalyst 24WC04/08/16 which has 9/10/11 bits of
  231. address and the extra bits end up in the "chip address" bit
  232. slots. This makes a 24WC08 (1Kbyte) chip look like four 256
  233. byte chips.
  234. endif
  235. config GDSYS_RXAUI_CTRL
  236. bool "Enable gdsys RXAUI control driver"
  237. depends on MISC
  238. help
  239. Support gdsys FPGA's RXAUI control.
  240. endmenu