clk_stm32mp1.c 45 KB

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  1. // SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
  2. /*
  3. * Copyright (C) 2018, STMicroelectronics - All Rights Reserved
  4. */
  5. #include <common.h>
  6. #include <clk-uclass.h>
  7. #include <div64.h>
  8. #include <dm.h>
  9. #include <regmap.h>
  10. #include <spl.h>
  11. #include <syscon.h>
  12. #include <linux/io.h>
  13. #include <linux/iopoll.h>
  14. #include <dt-bindings/clock/stm32mp1-clks.h>
  15. #include <dt-bindings/clock/stm32mp1-clksrc.h>
  16. #if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)
  17. /* activate clock tree initialization in the driver */
  18. #define STM32MP1_CLOCK_TREE_INIT
  19. #endif
  20. #define MAX_HSI_HZ 64000000
  21. /* TIMEOUT */
  22. #define TIMEOUT_200MS 200000
  23. #define TIMEOUT_1S 1000000
  24. /* STGEN registers */
  25. #define STGENC_CNTCR 0x00
  26. #define STGENC_CNTSR 0x04
  27. #define STGENC_CNTCVL 0x08
  28. #define STGENC_CNTCVU 0x0C
  29. #define STGENC_CNTFID0 0x20
  30. #define STGENC_CNTCR_EN BIT(0)
  31. /* RCC registers */
  32. #define RCC_OCENSETR 0x0C
  33. #define RCC_OCENCLRR 0x10
  34. #define RCC_HSICFGR 0x18
  35. #define RCC_MPCKSELR 0x20
  36. #define RCC_ASSCKSELR 0x24
  37. #define RCC_RCK12SELR 0x28
  38. #define RCC_MPCKDIVR 0x2C
  39. #define RCC_AXIDIVR 0x30
  40. #define RCC_APB4DIVR 0x3C
  41. #define RCC_APB5DIVR 0x40
  42. #define RCC_RTCDIVR 0x44
  43. #define RCC_MSSCKSELR 0x48
  44. #define RCC_PLL1CR 0x80
  45. #define RCC_PLL1CFGR1 0x84
  46. #define RCC_PLL1CFGR2 0x88
  47. #define RCC_PLL1FRACR 0x8C
  48. #define RCC_PLL1CSGR 0x90
  49. #define RCC_PLL2CR 0x94
  50. #define RCC_PLL2CFGR1 0x98
  51. #define RCC_PLL2CFGR2 0x9C
  52. #define RCC_PLL2FRACR 0xA0
  53. #define RCC_PLL2CSGR 0xA4
  54. #define RCC_I2C46CKSELR 0xC0
  55. #define RCC_CPERCKSELR 0xD0
  56. #define RCC_STGENCKSELR 0xD4
  57. #define RCC_DDRITFCR 0xD8
  58. #define RCC_BDCR 0x140
  59. #define RCC_RDLSICR 0x144
  60. #define RCC_MP_APB4ENSETR 0x200
  61. #define RCC_MP_APB5ENSETR 0x208
  62. #define RCC_MP_AHB5ENSETR 0x210
  63. #define RCC_MP_AHB6ENSETR 0x218
  64. #define RCC_OCRDYR 0x808
  65. #define RCC_DBGCFGR 0x80C
  66. #define RCC_RCK3SELR 0x820
  67. #define RCC_RCK4SELR 0x824
  68. #define RCC_MCUDIVR 0x830
  69. #define RCC_APB1DIVR 0x834
  70. #define RCC_APB2DIVR 0x838
  71. #define RCC_APB3DIVR 0x83C
  72. #define RCC_PLL3CR 0x880
  73. #define RCC_PLL3CFGR1 0x884
  74. #define RCC_PLL3CFGR2 0x888
  75. #define RCC_PLL3FRACR 0x88C
  76. #define RCC_PLL3CSGR 0x890
  77. #define RCC_PLL4CR 0x894
  78. #define RCC_PLL4CFGR1 0x898
  79. #define RCC_PLL4CFGR2 0x89C
  80. #define RCC_PLL4FRACR 0x8A0
  81. #define RCC_PLL4CSGR 0x8A4
  82. #define RCC_I2C12CKSELR 0x8C0
  83. #define RCC_I2C35CKSELR 0x8C4
  84. #define RCC_UART6CKSELR 0x8E4
  85. #define RCC_UART24CKSELR 0x8E8
  86. #define RCC_UART35CKSELR 0x8EC
  87. #define RCC_UART78CKSELR 0x8F0
  88. #define RCC_SDMMC12CKSELR 0x8F4
  89. #define RCC_SDMMC3CKSELR 0x8F8
  90. #define RCC_ETHCKSELR 0x8FC
  91. #define RCC_QSPICKSELR 0x900
  92. #define RCC_FMCCKSELR 0x904
  93. #define RCC_USBCKSELR 0x91C
  94. #define RCC_MP_APB1ENSETR 0xA00
  95. #define RCC_MP_APB2ENSETR 0XA08
  96. #define RCC_MP_APB3ENSETR 0xA10
  97. #define RCC_MP_AHB2ENSETR 0xA18
  98. #define RCC_MP_AHB4ENSETR 0xA28
  99. /* used for most of SELR register */
  100. #define RCC_SELR_SRC_MASK GENMASK(2, 0)
  101. #define RCC_SELR_SRCRDY BIT(31)
  102. /* Values of RCC_MPCKSELR register */
  103. #define RCC_MPCKSELR_HSI 0
  104. #define RCC_MPCKSELR_HSE 1
  105. #define RCC_MPCKSELR_PLL 2
  106. #define RCC_MPCKSELR_PLL_MPUDIV 3
  107. /* Values of RCC_ASSCKSELR register */
  108. #define RCC_ASSCKSELR_HSI 0
  109. #define RCC_ASSCKSELR_HSE 1
  110. #define RCC_ASSCKSELR_PLL 2
  111. /* Values of RCC_MSSCKSELR register */
  112. #define RCC_MSSCKSELR_HSI 0
  113. #define RCC_MSSCKSELR_HSE 1
  114. #define RCC_MSSCKSELR_CSI 2
  115. #define RCC_MSSCKSELR_PLL 3
  116. /* Values of RCC_CPERCKSELR register */
  117. #define RCC_CPERCKSELR_HSI 0
  118. #define RCC_CPERCKSELR_CSI 1
  119. #define RCC_CPERCKSELR_HSE 2
  120. /* used for most of DIVR register : max div for RTC */
  121. #define RCC_DIVR_DIV_MASK GENMASK(5, 0)
  122. #define RCC_DIVR_DIVRDY BIT(31)
  123. /* Masks for specific DIVR registers */
  124. #define RCC_APBXDIV_MASK GENMASK(2, 0)
  125. #define RCC_MPUDIV_MASK GENMASK(2, 0)
  126. #define RCC_AXIDIV_MASK GENMASK(2, 0)
  127. #define RCC_MCUDIV_MASK GENMASK(3, 0)
  128. /* offset between RCC_MP_xxxENSETR and RCC_MP_xxxENCLRR registers */
  129. #define RCC_MP_ENCLRR_OFFSET 4
  130. /* Fields of RCC_BDCR register */
  131. #define RCC_BDCR_LSEON BIT(0)
  132. #define RCC_BDCR_LSEBYP BIT(1)
  133. #define RCC_BDCR_LSERDY BIT(2)
  134. #define RCC_BDCR_LSEDRV_MASK GENMASK(5, 4)
  135. #define RCC_BDCR_LSEDRV_SHIFT 4
  136. #define RCC_BDCR_LSECSSON BIT(8)
  137. #define RCC_BDCR_RTCCKEN BIT(20)
  138. #define RCC_BDCR_RTCSRC_MASK GENMASK(17, 16)
  139. #define RCC_BDCR_RTCSRC_SHIFT 16
  140. /* Fields of RCC_RDLSICR register */
  141. #define RCC_RDLSICR_LSION BIT(0)
  142. #define RCC_RDLSICR_LSIRDY BIT(1)
  143. /* used for ALL PLLNCR registers */
  144. #define RCC_PLLNCR_PLLON BIT(0)
  145. #define RCC_PLLNCR_PLLRDY BIT(1)
  146. #define RCC_PLLNCR_DIVPEN BIT(4)
  147. #define RCC_PLLNCR_DIVQEN BIT(5)
  148. #define RCC_PLLNCR_DIVREN BIT(6)
  149. #define RCC_PLLNCR_DIVEN_SHIFT 4
  150. /* used for ALL PLLNCFGR1 registers */
  151. #define RCC_PLLNCFGR1_DIVM_SHIFT 16
  152. #define RCC_PLLNCFGR1_DIVM_MASK GENMASK(21, 16)
  153. #define RCC_PLLNCFGR1_DIVN_SHIFT 0
  154. #define RCC_PLLNCFGR1_DIVN_MASK GENMASK(8, 0)
  155. /* only for PLL3 and PLL4 */
  156. #define RCC_PLLNCFGR1_IFRGE_SHIFT 24
  157. #define RCC_PLLNCFGR1_IFRGE_MASK GENMASK(25, 24)
  158. /* used for ALL PLLNCFGR2 registers */
  159. #define RCC_PLLNCFGR2_DIVX_MASK GENMASK(6, 0)
  160. #define RCC_PLLNCFGR2_DIVP_SHIFT 0
  161. #define RCC_PLLNCFGR2_DIVP_MASK GENMASK(6, 0)
  162. #define RCC_PLLNCFGR2_DIVQ_SHIFT 8
  163. #define RCC_PLLNCFGR2_DIVQ_MASK GENMASK(14, 8)
  164. #define RCC_PLLNCFGR2_DIVR_SHIFT 16
  165. #define RCC_PLLNCFGR2_DIVR_MASK GENMASK(22, 16)
  166. /* used for ALL PLLNFRACR registers */
  167. #define RCC_PLLNFRACR_FRACV_SHIFT 3
  168. #define RCC_PLLNFRACR_FRACV_MASK GENMASK(15, 3)
  169. #define RCC_PLLNFRACR_FRACLE BIT(16)
  170. /* used for ALL PLLNCSGR registers */
  171. #define RCC_PLLNCSGR_INC_STEP_SHIFT 16
  172. #define RCC_PLLNCSGR_INC_STEP_MASK GENMASK(30, 16)
  173. #define RCC_PLLNCSGR_MOD_PER_SHIFT 0
  174. #define RCC_PLLNCSGR_MOD_PER_MASK GENMASK(12, 0)
  175. #define RCC_PLLNCSGR_SSCG_MODE_SHIFT 15
  176. #define RCC_PLLNCSGR_SSCG_MODE_MASK BIT(15)
  177. /* used for RCC_OCENSETR and RCC_OCENCLRR registers */
  178. #define RCC_OCENR_HSION BIT(0)
  179. #define RCC_OCENR_CSION BIT(4)
  180. #define RCC_OCENR_HSEON BIT(8)
  181. #define RCC_OCENR_HSEBYP BIT(10)
  182. #define RCC_OCENR_HSECSSON BIT(11)
  183. /* Fields of RCC_OCRDYR register */
  184. #define RCC_OCRDYR_HSIRDY BIT(0)
  185. #define RCC_OCRDYR_HSIDIVRDY BIT(2)
  186. #define RCC_OCRDYR_CSIRDY BIT(4)
  187. #define RCC_OCRDYR_HSERDY BIT(8)
  188. /* Fields of DDRITFCR register */
  189. #define RCC_DDRITFCR_DDRCKMOD_MASK GENMASK(22, 20)
  190. #define RCC_DDRITFCR_DDRCKMOD_SHIFT 20
  191. #define RCC_DDRITFCR_DDRCKMOD_SSR 0
  192. /* Fields of RCC_HSICFGR register */
  193. #define RCC_HSICFGR_HSIDIV_MASK GENMASK(1, 0)
  194. /* used for MCO related operations */
  195. #define RCC_MCOCFG_MCOON BIT(12)
  196. #define RCC_MCOCFG_MCODIV_MASK GENMASK(7, 4)
  197. #define RCC_MCOCFG_MCODIV_SHIFT 4
  198. #define RCC_MCOCFG_MCOSRC_MASK GENMASK(2, 0)
  199. enum stm32mp1_parent_id {
  200. /*
  201. * _HSI, _HSE, _CSI, _LSI, _LSE should not be moved
  202. * they are used as index in osc[] as entry point
  203. */
  204. _HSI,
  205. _HSE,
  206. _CSI,
  207. _LSI,
  208. _LSE,
  209. _I2S_CKIN,
  210. _USB_PHY_48,
  211. NB_OSC,
  212. /* other parent source */
  213. _HSI_KER = NB_OSC,
  214. _HSE_KER,
  215. _HSE_KER_DIV2,
  216. _CSI_KER,
  217. _PLL1_P,
  218. _PLL1_Q,
  219. _PLL1_R,
  220. _PLL2_P,
  221. _PLL2_Q,
  222. _PLL2_R,
  223. _PLL3_P,
  224. _PLL3_Q,
  225. _PLL3_R,
  226. _PLL4_P,
  227. _PLL4_Q,
  228. _PLL4_R,
  229. _ACLK,
  230. _PCLK1,
  231. _PCLK2,
  232. _PCLK3,
  233. _PCLK4,
  234. _PCLK5,
  235. _HCLK6,
  236. _HCLK2,
  237. _CK_PER,
  238. _CK_MPU,
  239. _CK_MCU,
  240. _PARENT_NB,
  241. _UNKNOWN_ID = 0xff,
  242. };
  243. enum stm32mp1_parent_sel {
  244. _I2C12_SEL,
  245. _I2C35_SEL,
  246. _I2C46_SEL,
  247. _UART6_SEL,
  248. _UART24_SEL,
  249. _UART35_SEL,
  250. _UART78_SEL,
  251. _SDMMC12_SEL,
  252. _SDMMC3_SEL,
  253. _ETH_SEL,
  254. _QSPI_SEL,
  255. _FMC_SEL,
  256. _USBPHY_SEL,
  257. _USBO_SEL,
  258. _STGEN_SEL,
  259. _PARENT_SEL_NB,
  260. _UNKNOWN_SEL = 0xff,
  261. };
  262. enum stm32mp1_pll_id {
  263. _PLL1,
  264. _PLL2,
  265. _PLL3,
  266. _PLL4,
  267. _PLL_NB
  268. };
  269. enum stm32mp1_div_id {
  270. _DIV_P,
  271. _DIV_Q,
  272. _DIV_R,
  273. _DIV_NB,
  274. };
  275. enum stm32mp1_clksrc_id {
  276. CLKSRC_MPU,
  277. CLKSRC_AXI,
  278. CLKSRC_MCU,
  279. CLKSRC_PLL12,
  280. CLKSRC_PLL3,
  281. CLKSRC_PLL4,
  282. CLKSRC_RTC,
  283. CLKSRC_MCO1,
  284. CLKSRC_MCO2,
  285. CLKSRC_NB
  286. };
  287. enum stm32mp1_clkdiv_id {
  288. CLKDIV_MPU,
  289. CLKDIV_AXI,
  290. CLKDIV_MCU,
  291. CLKDIV_APB1,
  292. CLKDIV_APB2,
  293. CLKDIV_APB3,
  294. CLKDIV_APB4,
  295. CLKDIV_APB5,
  296. CLKDIV_RTC,
  297. CLKDIV_MCO1,
  298. CLKDIV_MCO2,
  299. CLKDIV_NB
  300. };
  301. enum stm32mp1_pllcfg {
  302. PLLCFG_M,
  303. PLLCFG_N,
  304. PLLCFG_P,
  305. PLLCFG_Q,
  306. PLLCFG_R,
  307. PLLCFG_O,
  308. PLLCFG_NB
  309. };
  310. enum stm32mp1_pllcsg {
  311. PLLCSG_MOD_PER,
  312. PLLCSG_INC_STEP,
  313. PLLCSG_SSCG_MODE,
  314. PLLCSG_NB
  315. };
  316. enum stm32mp1_plltype {
  317. PLL_800,
  318. PLL_1600,
  319. PLL_TYPE_NB
  320. };
  321. struct stm32mp1_pll {
  322. u8 refclk_min;
  323. u8 refclk_max;
  324. u8 divn_max;
  325. };
  326. struct stm32mp1_clk_gate {
  327. u16 offset;
  328. u8 bit;
  329. u8 index;
  330. u8 set_clr;
  331. u8 sel;
  332. u8 fixed;
  333. };
  334. struct stm32mp1_clk_sel {
  335. u16 offset;
  336. u8 src;
  337. u8 msk;
  338. u8 nb_parent;
  339. const u8 *parent;
  340. };
  341. #define REFCLK_SIZE 4
  342. struct stm32mp1_clk_pll {
  343. enum stm32mp1_plltype plltype;
  344. u16 rckxselr;
  345. u16 pllxcfgr1;
  346. u16 pllxcfgr2;
  347. u16 pllxfracr;
  348. u16 pllxcr;
  349. u16 pllxcsgr;
  350. u8 refclk[REFCLK_SIZE];
  351. };
  352. struct stm32mp1_clk_data {
  353. const struct stm32mp1_clk_gate *gate;
  354. const struct stm32mp1_clk_sel *sel;
  355. const struct stm32mp1_clk_pll *pll;
  356. const int nb_gate;
  357. };
  358. struct stm32mp1_clk_priv {
  359. fdt_addr_t base;
  360. const struct stm32mp1_clk_data *data;
  361. ulong osc[NB_OSC];
  362. struct udevice *osc_dev[NB_OSC];
  363. };
  364. #define STM32MP1_CLK(off, b, idx, s) \
  365. { \
  366. .offset = (off), \
  367. .bit = (b), \
  368. .index = (idx), \
  369. .set_clr = 0, \
  370. .sel = (s), \
  371. .fixed = _UNKNOWN_ID, \
  372. }
  373. #define STM32MP1_CLK_F(off, b, idx, f) \
  374. { \
  375. .offset = (off), \
  376. .bit = (b), \
  377. .index = (idx), \
  378. .set_clr = 0, \
  379. .sel = _UNKNOWN_SEL, \
  380. .fixed = (f), \
  381. }
  382. #define STM32MP1_CLK_SET_CLR(off, b, idx, s) \
  383. { \
  384. .offset = (off), \
  385. .bit = (b), \
  386. .index = (idx), \
  387. .set_clr = 1, \
  388. .sel = (s), \
  389. .fixed = _UNKNOWN_ID, \
  390. }
  391. #define STM32MP1_CLK_SET_CLR_F(off, b, idx, f) \
  392. { \
  393. .offset = (off), \
  394. .bit = (b), \
  395. .index = (idx), \
  396. .set_clr = 1, \
  397. .sel = _UNKNOWN_SEL, \
  398. .fixed = (f), \
  399. }
  400. #define STM32MP1_CLK_PARENT(idx, off, s, m, p) \
  401. [(idx)] = { \
  402. .offset = (off), \
  403. .src = (s), \
  404. .msk = (m), \
  405. .parent = (p), \
  406. .nb_parent = ARRAY_SIZE((p)) \
  407. }
  408. #define STM32MP1_CLK_PLL(idx, type, off1, off2, off3, off4, off5, off6,\
  409. p1, p2, p3, p4) \
  410. [(idx)] = { \
  411. .plltype = (type), \
  412. .rckxselr = (off1), \
  413. .pllxcfgr1 = (off2), \
  414. .pllxcfgr2 = (off3), \
  415. .pllxfracr = (off4), \
  416. .pllxcr = (off5), \
  417. .pllxcsgr = (off6), \
  418. .refclk[0] = (p1), \
  419. .refclk[1] = (p2), \
  420. .refclk[2] = (p3), \
  421. .refclk[3] = (p4), \
  422. }
  423. static const u8 stm32mp1_clks[][2] = {
  424. {CK_PER, _CK_PER},
  425. {CK_MPU, _CK_MPU},
  426. {CK_AXI, _ACLK},
  427. {CK_MCU, _CK_MCU},
  428. {CK_HSE, _HSE},
  429. {CK_CSI, _CSI},
  430. {CK_LSI, _LSI},
  431. {CK_LSE, _LSE},
  432. {CK_HSI, _HSI},
  433. {CK_HSE_DIV2, _HSE_KER_DIV2},
  434. };
  435. static const struct stm32mp1_clk_gate stm32mp1_clk_gate[] = {
  436. STM32MP1_CLK(RCC_DDRITFCR, 0, DDRC1, _UNKNOWN_SEL),
  437. STM32MP1_CLK(RCC_DDRITFCR, 1, DDRC1LP, _UNKNOWN_SEL),
  438. STM32MP1_CLK(RCC_DDRITFCR, 2, DDRC2, _UNKNOWN_SEL),
  439. STM32MP1_CLK(RCC_DDRITFCR, 3, DDRC2LP, _UNKNOWN_SEL),
  440. STM32MP1_CLK_F(RCC_DDRITFCR, 4, DDRPHYC, _PLL2_R),
  441. STM32MP1_CLK(RCC_DDRITFCR, 5, DDRPHYCLP, _UNKNOWN_SEL),
  442. STM32MP1_CLK(RCC_DDRITFCR, 6, DDRCAPB, _UNKNOWN_SEL),
  443. STM32MP1_CLK(RCC_DDRITFCR, 7, DDRCAPBLP, _UNKNOWN_SEL),
  444. STM32MP1_CLK(RCC_DDRITFCR, 8, AXIDCG, _UNKNOWN_SEL),
  445. STM32MP1_CLK(RCC_DDRITFCR, 9, DDRPHYCAPB, _UNKNOWN_SEL),
  446. STM32MP1_CLK(RCC_DDRITFCR, 10, DDRPHYCAPBLP, _UNKNOWN_SEL),
  447. STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 14, USART2_K, _UART24_SEL),
  448. STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 15, USART3_K, _UART35_SEL),
  449. STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 16, UART4_K, _UART24_SEL),
  450. STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 17, UART5_K, _UART35_SEL),
  451. STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 18, UART7_K, _UART78_SEL),
  452. STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 19, UART8_K, _UART78_SEL),
  453. STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 21, I2C1_K, _I2C12_SEL),
  454. STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 22, I2C2_K, _I2C12_SEL),
  455. STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 23, I2C3_K, _I2C35_SEL),
  456. STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 24, I2C5_K, _I2C35_SEL),
  457. STM32MP1_CLK_SET_CLR(RCC_MP_APB2ENSETR, 13, USART6_K, _UART6_SEL),
  458. STM32MP1_CLK_SET_CLR_F(RCC_MP_APB3ENSETR, 13, VREF, _PCLK3),
  459. STM32MP1_CLK_SET_CLR(RCC_MP_APB4ENSETR, 8, DDRPERFM, _UNKNOWN_SEL),
  460. STM32MP1_CLK_SET_CLR(RCC_MP_APB4ENSETR, 15, IWDG2, _UNKNOWN_SEL),
  461. STM32MP1_CLK_SET_CLR(RCC_MP_APB4ENSETR, 16, USBPHY_K, _USBPHY_SEL),
  462. STM32MP1_CLK_SET_CLR(RCC_MP_APB5ENSETR, 2, I2C4_K, _I2C46_SEL),
  463. STM32MP1_CLK_SET_CLR(RCC_MP_APB5ENSETR, 20, STGEN_K, _STGEN_SEL),
  464. STM32MP1_CLK_SET_CLR(RCC_MP_AHB2ENSETR, 8, USBO_K, _USBO_SEL),
  465. STM32MP1_CLK_SET_CLR(RCC_MP_AHB2ENSETR, 16, SDMMC3_K, _SDMMC3_SEL),
  466. STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 0, GPIOA, _UNKNOWN_SEL),
  467. STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 1, GPIOB, _UNKNOWN_SEL),
  468. STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 2, GPIOC, _UNKNOWN_SEL),
  469. STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 3, GPIOD, _UNKNOWN_SEL),
  470. STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 4, GPIOE, _UNKNOWN_SEL),
  471. STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 5, GPIOF, _UNKNOWN_SEL),
  472. STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 6, GPIOG, _UNKNOWN_SEL),
  473. STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 7, GPIOH, _UNKNOWN_SEL),
  474. STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 8, GPIOI, _UNKNOWN_SEL),
  475. STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 9, GPIOJ, _UNKNOWN_SEL),
  476. STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 10, GPIOK, _UNKNOWN_SEL),
  477. STM32MP1_CLK_SET_CLR(RCC_MP_AHB5ENSETR, 0, GPIOZ, _UNKNOWN_SEL),
  478. STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 7, ETHCK, _UNKNOWN_SEL),
  479. STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 8, ETHTX, _UNKNOWN_SEL),
  480. STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 9, ETHRX, _UNKNOWN_SEL),
  481. STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 10, ETHMAC_K, _ETH_SEL),
  482. STM32MP1_CLK_SET_CLR_F(RCC_MP_AHB6ENSETR, 10, ETHMAC, _ACLK),
  483. STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 12, FMC_K, _FMC_SEL),
  484. STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 14, QSPI_K, _QSPI_SEL),
  485. STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 16, SDMMC1_K, _SDMMC12_SEL),
  486. STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 17, SDMMC2_K, _SDMMC12_SEL),
  487. STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 24, USBH, _UNKNOWN_SEL),
  488. STM32MP1_CLK(RCC_DBGCFGR, 8, CK_DBG, _UNKNOWN_SEL),
  489. };
  490. static const u8 i2c12_parents[] = {_PCLK1, _PLL4_R, _HSI_KER, _CSI_KER};
  491. static const u8 i2c35_parents[] = {_PCLK1, _PLL4_R, _HSI_KER, _CSI_KER};
  492. static const u8 i2c46_parents[] = {_PCLK5, _PLL3_Q, _HSI_KER, _CSI_KER};
  493. static const u8 uart6_parents[] = {_PCLK2, _PLL4_Q, _HSI_KER, _CSI_KER,
  494. _HSE_KER};
  495. static const u8 uart24_parents[] = {_PCLK1, _PLL4_Q, _HSI_KER, _CSI_KER,
  496. _HSE_KER};
  497. static const u8 uart35_parents[] = {_PCLK1, _PLL4_Q, _HSI_KER, _CSI_KER,
  498. _HSE_KER};
  499. static const u8 uart78_parents[] = {_PCLK1, _PLL4_Q, _HSI_KER, _CSI_KER,
  500. _HSE_KER};
  501. static const u8 sdmmc12_parents[] = {_HCLK6, _PLL3_R, _PLL4_P, _HSI_KER};
  502. static const u8 sdmmc3_parents[] = {_HCLK2, _PLL3_R, _PLL4_P, _HSI_KER};
  503. static const u8 eth_parents[] = {_PLL4_P, _PLL3_Q};
  504. static const u8 qspi_parents[] = {_ACLK, _PLL3_R, _PLL4_P, _CK_PER};
  505. static const u8 fmc_parents[] = {_ACLK, _PLL3_R, _PLL4_P, _CK_PER};
  506. static const u8 usbphy_parents[] = {_HSE_KER, _PLL4_R, _HSE_KER_DIV2};
  507. static const u8 usbo_parents[] = {_PLL4_R, _USB_PHY_48};
  508. static const u8 stgen_parents[] = {_HSI_KER, _HSE_KER};
  509. static const struct stm32mp1_clk_sel stm32mp1_clk_sel[_PARENT_SEL_NB] = {
  510. STM32MP1_CLK_PARENT(_I2C12_SEL, RCC_I2C12CKSELR, 0, 0x7, i2c12_parents),
  511. STM32MP1_CLK_PARENT(_I2C35_SEL, RCC_I2C35CKSELR, 0, 0x7, i2c35_parents),
  512. STM32MP1_CLK_PARENT(_I2C46_SEL, RCC_I2C46CKSELR, 0, 0x7, i2c46_parents),
  513. STM32MP1_CLK_PARENT(_UART6_SEL, RCC_UART6CKSELR, 0, 0x7, uart6_parents),
  514. STM32MP1_CLK_PARENT(_UART24_SEL, RCC_UART24CKSELR, 0, 0x7,
  515. uart24_parents),
  516. STM32MP1_CLK_PARENT(_UART35_SEL, RCC_UART35CKSELR, 0, 0x7,
  517. uart35_parents),
  518. STM32MP1_CLK_PARENT(_UART78_SEL, RCC_UART78CKSELR, 0, 0x7,
  519. uart78_parents),
  520. STM32MP1_CLK_PARENT(_SDMMC12_SEL, RCC_SDMMC12CKSELR, 0, 0x7,
  521. sdmmc12_parents),
  522. STM32MP1_CLK_PARENT(_SDMMC3_SEL, RCC_SDMMC3CKSELR, 0, 0x7,
  523. sdmmc3_parents),
  524. STM32MP1_CLK_PARENT(_ETH_SEL, RCC_ETHCKSELR, 0, 0x3, eth_parents),
  525. STM32MP1_CLK_PARENT(_QSPI_SEL, RCC_QSPICKSELR, 0, 0xf, qspi_parents),
  526. STM32MP1_CLK_PARENT(_FMC_SEL, RCC_FMCCKSELR, 0, 0xf, fmc_parents),
  527. STM32MP1_CLK_PARENT(_USBPHY_SEL, RCC_USBCKSELR, 0, 0x3, usbphy_parents),
  528. STM32MP1_CLK_PARENT(_USBO_SEL, RCC_USBCKSELR, 4, 0x1, usbo_parents),
  529. STM32MP1_CLK_PARENT(_STGEN_SEL, RCC_STGENCKSELR, 0, 0x3, stgen_parents),
  530. };
  531. #ifdef STM32MP1_CLOCK_TREE_INIT
  532. /* define characteristic of PLL according type */
  533. #define DIVN_MIN 24
  534. static const struct stm32mp1_pll stm32mp1_pll[PLL_TYPE_NB] = {
  535. [PLL_800] = {
  536. .refclk_min = 4,
  537. .refclk_max = 16,
  538. .divn_max = 99,
  539. },
  540. [PLL_1600] = {
  541. .refclk_min = 8,
  542. .refclk_max = 16,
  543. .divn_max = 199,
  544. },
  545. };
  546. #endif /* STM32MP1_CLOCK_TREE_INIT */
  547. static const struct stm32mp1_clk_pll stm32mp1_clk_pll[_PLL_NB] = {
  548. STM32MP1_CLK_PLL(_PLL1, PLL_1600,
  549. RCC_RCK12SELR, RCC_PLL1CFGR1, RCC_PLL1CFGR2,
  550. RCC_PLL1FRACR, RCC_PLL1CR, RCC_PLL1CSGR,
  551. _HSI, _HSE, _UNKNOWN_ID, _UNKNOWN_ID),
  552. STM32MP1_CLK_PLL(_PLL2, PLL_1600,
  553. RCC_RCK12SELR, RCC_PLL2CFGR1, RCC_PLL2CFGR2,
  554. RCC_PLL2FRACR, RCC_PLL2CR, RCC_PLL2CSGR,
  555. _HSI, _HSE, _UNKNOWN_ID, _UNKNOWN_ID),
  556. STM32MP1_CLK_PLL(_PLL3, PLL_800,
  557. RCC_RCK3SELR, RCC_PLL3CFGR1, RCC_PLL3CFGR2,
  558. RCC_PLL3FRACR, RCC_PLL3CR, RCC_PLL3CSGR,
  559. _HSI, _HSE, _CSI, _UNKNOWN_ID),
  560. STM32MP1_CLK_PLL(_PLL4, PLL_800,
  561. RCC_RCK4SELR, RCC_PLL4CFGR1, RCC_PLL4CFGR2,
  562. RCC_PLL4FRACR, RCC_PLL4CR, RCC_PLL4CSGR,
  563. _HSI, _HSE, _CSI, _I2S_CKIN),
  564. };
  565. /* Prescaler table lookups for clock computation */
  566. /* div = /1 /2 /4 /8 / 16 /64 /128 /512 */
  567. static const u8 stm32mp1_mcu_div[16] = {
  568. 0, 1, 2, 3, 4, 6, 7, 8, 9, 9, 9, 9, 9, 9, 9, 9
  569. };
  570. /* div = /1 /2 /4 /8 /16 : same divider for pmu and apbx*/
  571. #define stm32mp1_mpu_div stm32mp1_mpu_apbx_div
  572. #define stm32mp1_apbx_div stm32mp1_mpu_apbx_div
  573. static const u8 stm32mp1_mpu_apbx_div[8] = {
  574. 0, 1, 2, 3, 4, 4, 4, 4
  575. };
  576. /* div = /1 /2 /3 /4 */
  577. static const u8 stm32mp1_axi_div[8] = {
  578. 1, 2, 3, 4, 4, 4, 4, 4
  579. };
  580. #ifdef DEBUG
  581. static const char * const stm32mp1_clk_parent_name[_PARENT_NB] = {
  582. [_HSI] = "HSI",
  583. [_HSE] = "HSE",
  584. [_CSI] = "CSI",
  585. [_LSI] = "LSI",
  586. [_LSE] = "LSE",
  587. [_I2S_CKIN] = "I2S_CKIN",
  588. [_HSI_KER] = "HSI_KER",
  589. [_HSE_KER] = "HSE_KER",
  590. [_HSE_KER_DIV2] = "HSE_KER_DIV2",
  591. [_CSI_KER] = "CSI_KER",
  592. [_PLL1_P] = "PLL1_P",
  593. [_PLL1_Q] = "PLL1_Q",
  594. [_PLL1_R] = "PLL1_R",
  595. [_PLL2_P] = "PLL2_P",
  596. [_PLL2_Q] = "PLL2_Q",
  597. [_PLL2_R] = "PLL2_R",
  598. [_PLL3_P] = "PLL3_P",
  599. [_PLL3_Q] = "PLL3_Q",
  600. [_PLL3_R] = "PLL3_R",
  601. [_PLL4_P] = "PLL4_P",
  602. [_PLL4_Q] = "PLL4_Q",
  603. [_PLL4_R] = "PLL4_R",
  604. [_ACLK] = "ACLK",
  605. [_PCLK1] = "PCLK1",
  606. [_PCLK2] = "PCLK2",
  607. [_PCLK3] = "PCLK3",
  608. [_PCLK4] = "PCLK4",
  609. [_PCLK5] = "PCLK5",
  610. [_HCLK6] = "KCLK6",
  611. [_HCLK2] = "HCLK2",
  612. [_CK_PER] = "CK_PER",
  613. [_CK_MPU] = "CK_MPU",
  614. [_CK_MCU] = "CK_MCU",
  615. [_USB_PHY_48] = "USB_PHY_48"
  616. };
  617. static const char * const stm32mp1_clk_parent_sel_name[_PARENT_SEL_NB] = {
  618. [_I2C12_SEL] = "I2C12",
  619. [_I2C35_SEL] = "I2C35",
  620. [_I2C46_SEL] = "I2C46",
  621. [_UART6_SEL] = "UART6",
  622. [_UART24_SEL] = "UART24",
  623. [_UART35_SEL] = "UART35",
  624. [_UART78_SEL] = "UART78",
  625. [_SDMMC12_SEL] = "SDMMC12",
  626. [_SDMMC3_SEL] = "SDMMC3",
  627. [_ETH_SEL] = "ETH",
  628. [_QSPI_SEL] = "QSPI",
  629. [_FMC_SEL] = "FMC",
  630. [_USBPHY_SEL] = "USBPHY",
  631. [_USBO_SEL] = "USBO",
  632. [_STGEN_SEL] = "STGEN"
  633. };
  634. #endif
  635. static const struct stm32mp1_clk_data stm32mp1_data = {
  636. .gate = stm32mp1_clk_gate,
  637. .sel = stm32mp1_clk_sel,
  638. .pll = stm32mp1_clk_pll,
  639. .nb_gate = ARRAY_SIZE(stm32mp1_clk_gate),
  640. };
  641. static ulong stm32mp1_clk_get_fixed(struct stm32mp1_clk_priv *priv, int idx)
  642. {
  643. if (idx >= NB_OSC) {
  644. debug("%s: clk id %d not found\n", __func__, idx);
  645. return 0;
  646. }
  647. debug("%s: clk id %d = %x : %ld kHz\n", __func__, idx,
  648. (u32)priv->osc[idx], priv->osc[idx] / 1000);
  649. return priv->osc[idx];
  650. }
  651. static int stm32mp1_clk_get_id(struct stm32mp1_clk_priv *priv, unsigned long id)
  652. {
  653. const struct stm32mp1_clk_gate *gate = priv->data->gate;
  654. int i, nb_clks = priv->data->nb_gate;
  655. for (i = 0; i < nb_clks; i++) {
  656. if (gate[i].index == id)
  657. break;
  658. }
  659. if (i == nb_clks) {
  660. printf("%s: clk id %d not found\n", __func__, (u32)id);
  661. return -EINVAL;
  662. }
  663. return i;
  664. }
  665. static int stm32mp1_clk_get_sel(struct stm32mp1_clk_priv *priv,
  666. int i)
  667. {
  668. const struct stm32mp1_clk_gate *gate = priv->data->gate;
  669. if (gate[i].sel > _PARENT_SEL_NB) {
  670. printf("%s: parents for clk id %d not found\n",
  671. __func__, i);
  672. return -EINVAL;
  673. }
  674. return gate[i].sel;
  675. }
  676. static int stm32mp1_clk_get_fixed_parent(struct stm32mp1_clk_priv *priv,
  677. int i)
  678. {
  679. const struct stm32mp1_clk_gate *gate = priv->data->gate;
  680. if (gate[i].fixed == _UNKNOWN_ID)
  681. return -ENOENT;
  682. return gate[i].fixed;
  683. }
  684. static int stm32mp1_clk_get_parent(struct stm32mp1_clk_priv *priv,
  685. unsigned long id)
  686. {
  687. const struct stm32mp1_clk_sel *sel = priv->data->sel;
  688. int i;
  689. int s, p;
  690. for (i = 0; i < ARRAY_SIZE(stm32mp1_clks); i++)
  691. if (stm32mp1_clks[i][0] == id)
  692. return stm32mp1_clks[i][1];
  693. i = stm32mp1_clk_get_id(priv, id);
  694. if (i < 0)
  695. return i;
  696. p = stm32mp1_clk_get_fixed_parent(priv, i);
  697. if (p >= 0 && p < _PARENT_NB)
  698. return p;
  699. s = stm32mp1_clk_get_sel(priv, i);
  700. if (s < 0)
  701. return s;
  702. p = (readl(priv->base + sel[s].offset) >> sel[s].src) & sel[s].msk;
  703. if (p < sel[s].nb_parent) {
  704. #ifdef DEBUG
  705. debug("%s: %s clock is the parent %s of clk id %d\n", __func__,
  706. stm32mp1_clk_parent_name[sel[s].parent[p]],
  707. stm32mp1_clk_parent_sel_name[s],
  708. (u32)id);
  709. #endif
  710. return sel[s].parent[p];
  711. }
  712. pr_err("%s: no parents defined for clk id %d\n",
  713. __func__, (u32)id);
  714. return -EINVAL;
  715. }
  716. static ulong stm32mp1_read_pll_freq(struct stm32mp1_clk_priv *priv,
  717. int pll_id, int div_id)
  718. {
  719. const struct stm32mp1_clk_pll *pll = priv->data->pll;
  720. int divm, divn, divy, src;
  721. ulong refclk, dfout;
  722. u32 selr, cfgr1, cfgr2, fracr;
  723. const u8 shift[_DIV_NB] = {
  724. [_DIV_P] = RCC_PLLNCFGR2_DIVP_SHIFT,
  725. [_DIV_Q] = RCC_PLLNCFGR2_DIVQ_SHIFT,
  726. [_DIV_R] = RCC_PLLNCFGR2_DIVR_SHIFT };
  727. debug("%s(%d, %d)\n", __func__, pll_id, div_id);
  728. if (div_id > _DIV_NB)
  729. return 0;
  730. selr = readl(priv->base + pll[pll_id].rckxselr);
  731. cfgr1 = readl(priv->base + pll[pll_id].pllxcfgr1);
  732. cfgr2 = readl(priv->base + pll[pll_id].pllxcfgr2);
  733. fracr = readl(priv->base + pll[pll_id].pllxfracr);
  734. debug("PLL%d : selr=%x cfgr1=%x cfgr2=%x fracr=%x\n",
  735. pll_id, selr, cfgr1, cfgr2, fracr);
  736. divm = (cfgr1 & (RCC_PLLNCFGR1_DIVM_MASK)) >> RCC_PLLNCFGR1_DIVM_SHIFT;
  737. divn = cfgr1 & RCC_PLLNCFGR1_DIVN_MASK;
  738. divy = (cfgr2 >> shift[div_id]) & RCC_PLLNCFGR2_DIVX_MASK;
  739. debug(" DIVN=%d DIVM=%d DIVY=%d\n", divn, divm, divy);
  740. src = selr & RCC_SELR_SRC_MASK;
  741. refclk = stm32mp1_clk_get_fixed(priv, pll[pll_id].refclk[src]);
  742. debug(" refclk = %d kHz\n", (u32)(refclk / 1000));
  743. /*
  744. * For: PLL1 & PLL2 => VCO is * 2 but ck_pll_y is also / 2
  745. * So same final result than PLL2 et 4
  746. * with FRACV :
  747. * Fck_pll_y = Fck_ref * ((DIVN + 1) + FRACV / 2^13)
  748. * / (DIVM + 1) * (DIVy + 1)
  749. * without FRACV
  750. * Fck_pll_y = Fck_ref * ((DIVN + 1) / (DIVM + 1) *(DIVy + 1)
  751. */
  752. if (fracr & RCC_PLLNFRACR_FRACLE) {
  753. u32 fracv = (fracr & RCC_PLLNFRACR_FRACV_MASK)
  754. >> RCC_PLLNFRACR_FRACV_SHIFT;
  755. dfout = (ulong)lldiv((unsigned long long)refclk *
  756. (((divn + 1) << 13) + fracv),
  757. ((unsigned long long)(divm + 1) *
  758. (divy + 1)) << 13);
  759. } else {
  760. dfout = (ulong)(refclk * (divn + 1) / (divm + 1) * (divy + 1));
  761. }
  762. debug(" => dfout = %d kHz\n", (u32)(dfout / 1000));
  763. return dfout;
  764. }
  765. static ulong stm32mp1_clk_get(struct stm32mp1_clk_priv *priv, int p)
  766. {
  767. u32 reg;
  768. ulong clock = 0;
  769. switch (p) {
  770. case _CK_MPU:
  771. /* MPU sub system */
  772. reg = readl(priv->base + RCC_MPCKSELR);
  773. switch (reg & RCC_SELR_SRC_MASK) {
  774. case RCC_MPCKSELR_HSI:
  775. clock = stm32mp1_clk_get_fixed(priv, _HSI);
  776. break;
  777. case RCC_MPCKSELR_HSE:
  778. clock = stm32mp1_clk_get_fixed(priv, _HSE);
  779. break;
  780. case RCC_MPCKSELR_PLL:
  781. case RCC_MPCKSELR_PLL_MPUDIV:
  782. clock = stm32mp1_read_pll_freq(priv, _PLL1, _DIV_P);
  783. if (p == RCC_MPCKSELR_PLL_MPUDIV) {
  784. reg = readl(priv->base + RCC_MPCKDIVR);
  785. clock /= stm32mp1_mpu_div[reg &
  786. RCC_MPUDIV_MASK];
  787. }
  788. break;
  789. }
  790. break;
  791. /* AXI sub system */
  792. case _ACLK:
  793. case _HCLK2:
  794. case _HCLK6:
  795. case _PCLK4:
  796. case _PCLK5:
  797. reg = readl(priv->base + RCC_ASSCKSELR);
  798. switch (reg & RCC_SELR_SRC_MASK) {
  799. case RCC_ASSCKSELR_HSI:
  800. clock = stm32mp1_clk_get_fixed(priv, _HSI);
  801. break;
  802. case RCC_ASSCKSELR_HSE:
  803. clock = stm32mp1_clk_get_fixed(priv, _HSE);
  804. break;
  805. case RCC_ASSCKSELR_PLL:
  806. clock = stm32mp1_read_pll_freq(priv, _PLL2, _DIV_P);
  807. break;
  808. }
  809. /* System clock divider */
  810. reg = readl(priv->base + RCC_AXIDIVR);
  811. clock /= stm32mp1_axi_div[reg & RCC_AXIDIV_MASK];
  812. switch (p) {
  813. case _PCLK4:
  814. reg = readl(priv->base + RCC_APB4DIVR);
  815. clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK];
  816. break;
  817. case _PCLK5:
  818. reg = readl(priv->base + RCC_APB5DIVR);
  819. clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK];
  820. break;
  821. default:
  822. break;
  823. }
  824. break;
  825. /* MCU sub system */
  826. case _CK_MCU:
  827. case _PCLK1:
  828. case _PCLK2:
  829. case _PCLK3:
  830. reg = readl(priv->base + RCC_MSSCKSELR);
  831. switch (reg & RCC_SELR_SRC_MASK) {
  832. case RCC_MSSCKSELR_HSI:
  833. clock = stm32mp1_clk_get_fixed(priv, _HSI);
  834. break;
  835. case RCC_MSSCKSELR_HSE:
  836. clock = stm32mp1_clk_get_fixed(priv, _HSE);
  837. break;
  838. case RCC_MSSCKSELR_CSI:
  839. clock = stm32mp1_clk_get_fixed(priv, _CSI);
  840. break;
  841. case RCC_MSSCKSELR_PLL:
  842. clock = stm32mp1_read_pll_freq(priv, _PLL3, _DIV_P);
  843. break;
  844. }
  845. /* MCU clock divider */
  846. reg = readl(priv->base + RCC_MCUDIVR);
  847. clock >>= stm32mp1_mcu_div[reg & RCC_MCUDIV_MASK];
  848. switch (p) {
  849. case _PCLK1:
  850. reg = readl(priv->base + RCC_APB1DIVR);
  851. clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK];
  852. break;
  853. case _PCLK2:
  854. reg = readl(priv->base + RCC_APB2DIVR);
  855. clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK];
  856. break;
  857. case _PCLK3:
  858. reg = readl(priv->base + RCC_APB3DIVR);
  859. clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK];
  860. break;
  861. case _CK_MCU:
  862. default:
  863. break;
  864. }
  865. break;
  866. case _CK_PER:
  867. reg = readl(priv->base + RCC_CPERCKSELR);
  868. switch (reg & RCC_SELR_SRC_MASK) {
  869. case RCC_CPERCKSELR_HSI:
  870. clock = stm32mp1_clk_get_fixed(priv, _HSI);
  871. break;
  872. case RCC_CPERCKSELR_HSE:
  873. clock = stm32mp1_clk_get_fixed(priv, _HSE);
  874. break;
  875. case RCC_CPERCKSELR_CSI:
  876. clock = stm32mp1_clk_get_fixed(priv, _CSI);
  877. break;
  878. }
  879. break;
  880. case _HSI:
  881. case _HSI_KER:
  882. clock = stm32mp1_clk_get_fixed(priv, _HSI);
  883. break;
  884. case _CSI:
  885. case _CSI_KER:
  886. clock = stm32mp1_clk_get_fixed(priv, _CSI);
  887. break;
  888. case _HSE:
  889. case _HSE_KER:
  890. case _HSE_KER_DIV2:
  891. clock = stm32mp1_clk_get_fixed(priv, _HSE);
  892. if (p == _HSE_KER_DIV2)
  893. clock >>= 1;
  894. break;
  895. case _LSI:
  896. clock = stm32mp1_clk_get_fixed(priv, _LSI);
  897. break;
  898. case _LSE:
  899. clock = stm32mp1_clk_get_fixed(priv, _LSE);
  900. break;
  901. /* PLL */
  902. case _PLL1_P:
  903. case _PLL1_Q:
  904. case _PLL1_R:
  905. clock = stm32mp1_read_pll_freq(priv, _PLL1, p - _PLL1_P);
  906. break;
  907. case _PLL2_P:
  908. case _PLL2_Q:
  909. case _PLL2_R:
  910. clock = stm32mp1_read_pll_freq(priv, _PLL2, p - _PLL2_P);
  911. break;
  912. case _PLL3_P:
  913. case _PLL3_Q:
  914. case _PLL3_R:
  915. clock = stm32mp1_read_pll_freq(priv, _PLL3, p - _PLL3_P);
  916. break;
  917. case _PLL4_P:
  918. case _PLL4_Q:
  919. case _PLL4_R:
  920. clock = stm32mp1_read_pll_freq(priv, _PLL4, p - _PLL4_P);
  921. break;
  922. /* other */
  923. case _USB_PHY_48:
  924. clock = stm32mp1_clk_get_fixed(priv, _USB_PHY_48);
  925. break;
  926. default:
  927. break;
  928. }
  929. debug("%s(%d) clock = %lx : %ld kHz\n",
  930. __func__, p, clock, clock / 1000);
  931. return clock;
  932. }
  933. static int stm32mp1_clk_enable(struct clk *clk)
  934. {
  935. struct stm32mp1_clk_priv *priv = dev_get_priv(clk->dev);
  936. const struct stm32mp1_clk_gate *gate = priv->data->gate;
  937. int i = stm32mp1_clk_get_id(priv, clk->id);
  938. if (i < 0)
  939. return i;
  940. if (gate[i].set_clr)
  941. writel(BIT(gate[i].bit), priv->base + gate[i].offset);
  942. else
  943. setbits_le32(priv->base + gate[i].offset, BIT(gate[i].bit));
  944. debug("%s: id clock %d has been enabled\n", __func__, (u32)clk->id);
  945. return 0;
  946. }
  947. static int stm32mp1_clk_disable(struct clk *clk)
  948. {
  949. struct stm32mp1_clk_priv *priv = dev_get_priv(clk->dev);
  950. const struct stm32mp1_clk_gate *gate = priv->data->gate;
  951. int i = stm32mp1_clk_get_id(priv, clk->id);
  952. if (i < 0)
  953. return i;
  954. if (gate[i].set_clr)
  955. writel(BIT(gate[i].bit),
  956. priv->base + gate[i].offset
  957. + RCC_MP_ENCLRR_OFFSET);
  958. else
  959. clrbits_le32(priv->base + gate[i].offset, BIT(gate[i].bit));
  960. debug("%s: id clock %d has been disabled\n", __func__, (u32)clk->id);
  961. return 0;
  962. }
  963. static ulong stm32mp1_clk_get_rate(struct clk *clk)
  964. {
  965. struct stm32mp1_clk_priv *priv = dev_get_priv(clk->dev);
  966. int p = stm32mp1_clk_get_parent(priv, clk->id);
  967. ulong rate;
  968. if (p < 0)
  969. return 0;
  970. rate = stm32mp1_clk_get(priv, p);
  971. #ifdef DEBUG
  972. debug("%s: computed rate for id clock %d is %d (parent is %s)\n",
  973. __func__, (u32)clk->id, (u32)rate, stm32mp1_clk_parent_name[p]);
  974. #endif
  975. return rate;
  976. }
  977. #ifdef STM32MP1_CLOCK_TREE_INIT
  978. static void stm32mp1_ls_osc_set(int enable, fdt_addr_t rcc, u32 offset,
  979. u32 mask_on)
  980. {
  981. u32 address = rcc + offset;
  982. if (enable)
  983. setbits_le32(address, mask_on);
  984. else
  985. clrbits_le32(address, mask_on);
  986. }
  987. static void stm32mp1_hs_ocs_set(int enable, fdt_addr_t rcc, u32 mask_on)
  988. {
  989. if (enable)
  990. setbits_le32(rcc + RCC_OCENSETR, mask_on);
  991. else
  992. setbits_le32(rcc + RCC_OCENCLRR, mask_on);
  993. }
  994. static int stm32mp1_osc_wait(int enable, fdt_addr_t rcc, u32 offset,
  995. u32 mask_rdy)
  996. {
  997. u32 mask_test = 0;
  998. u32 address = rcc + offset;
  999. u32 val;
  1000. int ret;
  1001. if (enable)
  1002. mask_test = mask_rdy;
  1003. ret = readl_poll_timeout(address, val,
  1004. (val & mask_rdy) == mask_test,
  1005. TIMEOUT_1S);
  1006. if (ret)
  1007. pr_err("OSC %x @ %x timeout for enable=%d : 0x%x\n",
  1008. mask_rdy, address, enable, readl(address));
  1009. return ret;
  1010. }
  1011. static void stm32mp1_lse_enable(fdt_addr_t rcc, int bypass, int lsedrv)
  1012. {
  1013. u32 value;
  1014. if (bypass)
  1015. setbits_le32(rcc + RCC_BDCR, RCC_BDCR_LSEBYP);
  1016. /*
  1017. * warning: not recommended to switch directly from "high drive"
  1018. * to "medium low drive", and vice-versa.
  1019. */
  1020. value = (readl(rcc + RCC_BDCR) & RCC_BDCR_LSEDRV_MASK)
  1021. >> RCC_BDCR_LSEDRV_SHIFT;
  1022. while (value != lsedrv) {
  1023. if (value > lsedrv)
  1024. value--;
  1025. else
  1026. value++;
  1027. clrsetbits_le32(rcc + RCC_BDCR,
  1028. RCC_BDCR_LSEDRV_MASK,
  1029. value << RCC_BDCR_LSEDRV_SHIFT);
  1030. }
  1031. stm32mp1_ls_osc_set(1, rcc, RCC_BDCR, RCC_BDCR_LSEON);
  1032. }
  1033. static void stm32mp1_lse_wait(fdt_addr_t rcc)
  1034. {
  1035. stm32mp1_osc_wait(1, rcc, RCC_BDCR, RCC_BDCR_LSERDY);
  1036. }
  1037. static void stm32mp1_lsi_set(fdt_addr_t rcc, int enable)
  1038. {
  1039. stm32mp1_ls_osc_set(enable, rcc, RCC_RDLSICR, RCC_RDLSICR_LSION);
  1040. stm32mp1_osc_wait(enable, rcc, RCC_RDLSICR, RCC_RDLSICR_LSIRDY);
  1041. }
  1042. static void stm32mp1_hse_enable(fdt_addr_t rcc, int bypass, int css)
  1043. {
  1044. if (bypass)
  1045. setbits_le32(rcc + RCC_OCENSETR, RCC_OCENR_HSEBYP);
  1046. stm32mp1_hs_ocs_set(1, rcc, RCC_OCENR_HSEON);
  1047. stm32mp1_osc_wait(1, rcc, RCC_OCRDYR, RCC_OCRDYR_HSERDY);
  1048. if (css)
  1049. setbits_le32(rcc + RCC_OCENSETR, RCC_OCENR_HSECSSON);
  1050. }
  1051. static void stm32mp1_csi_set(fdt_addr_t rcc, int enable)
  1052. {
  1053. stm32mp1_ls_osc_set(enable, rcc, RCC_OCENSETR, RCC_OCENR_CSION);
  1054. stm32mp1_osc_wait(enable, rcc, RCC_OCRDYR, RCC_OCRDYR_CSIRDY);
  1055. }
  1056. static void stm32mp1_hsi_set(fdt_addr_t rcc, int enable)
  1057. {
  1058. stm32mp1_hs_ocs_set(enable, rcc, RCC_OCENR_HSION);
  1059. stm32mp1_osc_wait(enable, rcc, RCC_OCRDYR, RCC_OCRDYR_HSIRDY);
  1060. }
  1061. static int stm32mp1_set_hsidiv(fdt_addr_t rcc, u8 hsidiv)
  1062. {
  1063. u32 address = rcc + RCC_OCRDYR;
  1064. u32 val;
  1065. int ret;
  1066. clrsetbits_le32(rcc + RCC_HSICFGR,
  1067. RCC_HSICFGR_HSIDIV_MASK,
  1068. RCC_HSICFGR_HSIDIV_MASK & hsidiv);
  1069. ret = readl_poll_timeout(address, val,
  1070. val & RCC_OCRDYR_HSIDIVRDY,
  1071. TIMEOUT_200MS);
  1072. if (ret)
  1073. pr_err("HSIDIV failed @ 0x%x: 0x%x\n",
  1074. address, readl(address));
  1075. return ret;
  1076. }
  1077. static int stm32mp1_hsidiv(fdt_addr_t rcc, ulong hsifreq)
  1078. {
  1079. u8 hsidiv;
  1080. u32 hsidivfreq = MAX_HSI_HZ;
  1081. for (hsidiv = 0; hsidiv < 4; hsidiv++,
  1082. hsidivfreq = hsidivfreq / 2)
  1083. if (hsidivfreq == hsifreq)
  1084. break;
  1085. if (hsidiv == 4) {
  1086. pr_err("clk-hsi frequency invalid");
  1087. return -1;
  1088. }
  1089. if (hsidiv > 0)
  1090. return stm32mp1_set_hsidiv(rcc, hsidiv);
  1091. return 0;
  1092. }
  1093. static void pll_start(struct stm32mp1_clk_priv *priv, int pll_id)
  1094. {
  1095. const struct stm32mp1_clk_pll *pll = priv->data->pll;
  1096. writel(RCC_PLLNCR_PLLON, priv->base + pll[pll_id].pllxcr);
  1097. }
  1098. static int pll_output(struct stm32mp1_clk_priv *priv, int pll_id, int output)
  1099. {
  1100. const struct stm32mp1_clk_pll *pll = priv->data->pll;
  1101. u32 pllxcr = priv->base + pll[pll_id].pllxcr;
  1102. u32 val;
  1103. int ret;
  1104. ret = readl_poll_timeout(pllxcr, val, val & RCC_PLLNCR_PLLRDY,
  1105. TIMEOUT_200MS);
  1106. if (ret) {
  1107. pr_err("PLL%d start failed @ 0x%x: 0x%x\n",
  1108. pll_id, pllxcr, readl(pllxcr));
  1109. return ret;
  1110. }
  1111. /* start the requested output */
  1112. setbits_le32(pllxcr, output << RCC_PLLNCR_DIVEN_SHIFT);
  1113. return 0;
  1114. }
  1115. static int pll_stop(struct stm32mp1_clk_priv *priv, int pll_id)
  1116. {
  1117. const struct stm32mp1_clk_pll *pll = priv->data->pll;
  1118. u32 pllxcr = priv->base + pll[pll_id].pllxcr;
  1119. u32 val;
  1120. /* stop all output */
  1121. clrbits_le32(pllxcr,
  1122. RCC_PLLNCR_DIVPEN | RCC_PLLNCR_DIVQEN | RCC_PLLNCR_DIVREN);
  1123. /* stop PLL */
  1124. clrbits_le32(pllxcr, RCC_PLLNCR_PLLON);
  1125. /* wait PLL stopped */
  1126. return readl_poll_timeout(pllxcr, val, (val & RCC_PLLNCR_PLLRDY) == 0,
  1127. TIMEOUT_200MS);
  1128. }
  1129. static void pll_config_output(struct stm32mp1_clk_priv *priv,
  1130. int pll_id, u32 *pllcfg)
  1131. {
  1132. const struct stm32mp1_clk_pll *pll = priv->data->pll;
  1133. fdt_addr_t rcc = priv->base;
  1134. u32 value;
  1135. value = (pllcfg[PLLCFG_P] << RCC_PLLNCFGR2_DIVP_SHIFT)
  1136. & RCC_PLLNCFGR2_DIVP_MASK;
  1137. value |= (pllcfg[PLLCFG_Q] << RCC_PLLNCFGR2_DIVQ_SHIFT)
  1138. & RCC_PLLNCFGR2_DIVQ_MASK;
  1139. value |= (pllcfg[PLLCFG_R] << RCC_PLLNCFGR2_DIVR_SHIFT)
  1140. & RCC_PLLNCFGR2_DIVR_MASK;
  1141. writel(value, rcc + pll[pll_id].pllxcfgr2);
  1142. }
  1143. static int pll_config(struct stm32mp1_clk_priv *priv, int pll_id,
  1144. u32 *pllcfg, u32 fracv)
  1145. {
  1146. const struct stm32mp1_clk_pll *pll = priv->data->pll;
  1147. fdt_addr_t rcc = priv->base;
  1148. enum stm32mp1_plltype type = pll[pll_id].plltype;
  1149. int src;
  1150. ulong refclk;
  1151. u8 ifrge = 0;
  1152. u32 value;
  1153. src = readl(priv->base + pll[pll_id].rckxselr) & RCC_SELR_SRC_MASK;
  1154. refclk = stm32mp1_clk_get_fixed(priv, pll[pll_id].refclk[src]) /
  1155. (pllcfg[PLLCFG_M] + 1);
  1156. if (refclk < (stm32mp1_pll[type].refclk_min * 1000000) ||
  1157. refclk > (stm32mp1_pll[type].refclk_max * 1000000)) {
  1158. debug("invalid refclk = %x\n", (u32)refclk);
  1159. return -EINVAL;
  1160. }
  1161. if (type == PLL_800 && refclk >= 8000000)
  1162. ifrge = 1;
  1163. value = (pllcfg[PLLCFG_N] << RCC_PLLNCFGR1_DIVN_SHIFT)
  1164. & RCC_PLLNCFGR1_DIVN_MASK;
  1165. value |= (pllcfg[PLLCFG_M] << RCC_PLLNCFGR1_DIVM_SHIFT)
  1166. & RCC_PLLNCFGR1_DIVM_MASK;
  1167. value |= (ifrge << RCC_PLLNCFGR1_IFRGE_SHIFT)
  1168. & RCC_PLLNCFGR1_IFRGE_MASK;
  1169. writel(value, rcc + pll[pll_id].pllxcfgr1);
  1170. /* fractional configuration: load sigma-delta modulator (SDM) */
  1171. /* Write into FRACV the new fractional value , and FRACLE to 0 */
  1172. writel(fracv << RCC_PLLNFRACR_FRACV_SHIFT,
  1173. rcc + pll[pll_id].pllxfracr);
  1174. /* Write FRACLE to 1 : FRACV value is loaded into the SDM */
  1175. setbits_le32(rcc + pll[pll_id].pllxfracr,
  1176. RCC_PLLNFRACR_FRACLE);
  1177. pll_config_output(priv, pll_id, pllcfg);
  1178. return 0;
  1179. }
  1180. static void pll_csg(struct stm32mp1_clk_priv *priv, int pll_id, u32 *csg)
  1181. {
  1182. const struct stm32mp1_clk_pll *pll = priv->data->pll;
  1183. u32 pllxcsg;
  1184. pllxcsg = ((csg[PLLCSG_MOD_PER] << RCC_PLLNCSGR_MOD_PER_SHIFT) &
  1185. RCC_PLLNCSGR_MOD_PER_MASK) |
  1186. ((csg[PLLCSG_INC_STEP] << RCC_PLLNCSGR_INC_STEP_SHIFT) &
  1187. RCC_PLLNCSGR_INC_STEP_MASK) |
  1188. ((csg[PLLCSG_SSCG_MODE] << RCC_PLLNCSGR_SSCG_MODE_SHIFT) &
  1189. RCC_PLLNCSGR_SSCG_MODE_MASK);
  1190. writel(pllxcsg, priv->base + pll[pll_id].pllxcsgr);
  1191. }
  1192. static int set_clksrc(struct stm32mp1_clk_priv *priv, unsigned int clksrc)
  1193. {
  1194. u32 address = priv->base + (clksrc >> 4);
  1195. u32 val;
  1196. int ret;
  1197. clrsetbits_le32(address, RCC_SELR_SRC_MASK, clksrc & RCC_SELR_SRC_MASK);
  1198. ret = readl_poll_timeout(address, val, val & RCC_SELR_SRCRDY,
  1199. TIMEOUT_200MS);
  1200. if (ret)
  1201. pr_err("CLKSRC %x start failed @ 0x%x: 0x%x\n",
  1202. clksrc, address, readl(address));
  1203. return ret;
  1204. }
  1205. static void stgen_config(struct stm32mp1_clk_priv *priv)
  1206. {
  1207. int p;
  1208. u32 stgenc, cntfid0;
  1209. ulong rate;
  1210. stgenc = (u32)syscon_get_first_range(STM32MP_SYSCON_STGEN);
  1211. cntfid0 = readl(stgenc + STGENC_CNTFID0);
  1212. p = stm32mp1_clk_get_parent(priv, STGEN_K);
  1213. rate = stm32mp1_clk_get(priv, p);
  1214. if (cntfid0 != rate) {
  1215. pr_debug("System Generic Counter (STGEN) update\n");
  1216. clrbits_le32(stgenc + STGENC_CNTCR, STGENC_CNTCR_EN);
  1217. writel(0x0, stgenc + STGENC_CNTCVL);
  1218. writel(0x0, stgenc + STGENC_CNTCVU);
  1219. writel(rate, stgenc + STGENC_CNTFID0);
  1220. setbits_le32(stgenc + STGENC_CNTCR, STGENC_CNTCR_EN);
  1221. __asm__ volatile("mcr p15, 0, %0, c14, c0, 0" : : "r" (rate));
  1222. /* need to update gd->arch.timer_rate_hz with new frequency */
  1223. timer_init();
  1224. pr_debug("gd->arch.timer_rate_hz = %x\n",
  1225. (u32)gd->arch.timer_rate_hz);
  1226. pr_debug("Tick = %x\n", (u32)(get_ticks()));
  1227. }
  1228. }
  1229. static int set_clkdiv(unsigned int clkdiv, u32 address)
  1230. {
  1231. u32 val;
  1232. int ret;
  1233. clrsetbits_le32(address, RCC_DIVR_DIV_MASK, clkdiv & RCC_DIVR_DIV_MASK);
  1234. ret = readl_poll_timeout(address, val, val & RCC_DIVR_DIVRDY,
  1235. TIMEOUT_200MS);
  1236. if (ret)
  1237. pr_err("CLKDIV %x start failed @ 0x%x: 0x%x\n",
  1238. clkdiv, address, readl(address));
  1239. return ret;
  1240. }
  1241. static void stm32mp1_mco_csg(struct stm32mp1_clk_priv *priv,
  1242. u32 clksrc, u32 clkdiv)
  1243. {
  1244. u32 address = priv->base + (clksrc >> 4);
  1245. /*
  1246. * binding clksrc : bit15-4 offset
  1247. * bit3: disable
  1248. * bit2-0: MCOSEL[2:0]
  1249. */
  1250. if (clksrc & 0x8) {
  1251. clrbits_le32(address, RCC_MCOCFG_MCOON);
  1252. } else {
  1253. clrsetbits_le32(address,
  1254. RCC_MCOCFG_MCOSRC_MASK,
  1255. clksrc & RCC_MCOCFG_MCOSRC_MASK);
  1256. clrsetbits_le32(address,
  1257. RCC_MCOCFG_MCODIV_MASK,
  1258. clkdiv << RCC_MCOCFG_MCODIV_SHIFT);
  1259. setbits_le32(address, RCC_MCOCFG_MCOON);
  1260. }
  1261. }
  1262. static void set_rtcsrc(struct stm32mp1_clk_priv *priv,
  1263. unsigned int clksrc,
  1264. int lse_css)
  1265. {
  1266. u32 address = priv->base + RCC_BDCR;
  1267. if (readl(address) & RCC_BDCR_RTCCKEN)
  1268. goto skip_rtc;
  1269. if (clksrc == CLK_RTC_DISABLED)
  1270. goto skip_rtc;
  1271. clrsetbits_le32(address,
  1272. RCC_BDCR_RTCSRC_MASK,
  1273. clksrc << RCC_BDCR_RTCSRC_SHIFT);
  1274. setbits_le32(address, RCC_BDCR_RTCCKEN);
  1275. skip_rtc:
  1276. if (lse_css)
  1277. setbits_le32(address, RCC_BDCR_LSECSSON);
  1278. }
  1279. static void pkcs_config(struct stm32mp1_clk_priv *priv, u32 pkcs)
  1280. {
  1281. u32 address = priv->base + ((pkcs >> 4) & 0xFFF);
  1282. u32 value = pkcs & 0xF;
  1283. u32 mask = 0xF;
  1284. if (pkcs & BIT(31)) {
  1285. mask <<= 4;
  1286. value <<= 4;
  1287. }
  1288. clrsetbits_le32(address, mask, value);
  1289. }
  1290. static int stm32mp1_clktree(struct udevice *dev)
  1291. {
  1292. struct stm32mp1_clk_priv *priv = dev_get_priv(dev);
  1293. fdt_addr_t rcc = priv->base;
  1294. unsigned int clksrc[CLKSRC_NB];
  1295. unsigned int clkdiv[CLKDIV_NB];
  1296. unsigned int pllcfg[_PLL_NB][PLLCFG_NB];
  1297. ofnode plloff[_PLL_NB];
  1298. int ret;
  1299. int i, len;
  1300. int lse_css = 0;
  1301. const u32 *pkcs_cell;
  1302. /* check mandatory field */
  1303. ret = dev_read_u32_array(dev, "st,clksrc", clksrc, CLKSRC_NB);
  1304. if (ret < 0) {
  1305. debug("field st,clksrc invalid: error %d\n", ret);
  1306. return -FDT_ERR_NOTFOUND;
  1307. }
  1308. ret = dev_read_u32_array(dev, "st,clkdiv", clkdiv, CLKDIV_NB);
  1309. if (ret < 0) {
  1310. debug("field st,clkdiv invalid: error %d\n", ret);
  1311. return -FDT_ERR_NOTFOUND;
  1312. }
  1313. /* check mandatory field in each pll */
  1314. for (i = 0; i < _PLL_NB; i++) {
  1315. char name[12];
  1316. sprintf(name, "st,pll@%d", i);
  1317. plloff[i] = dev_read_subnode(dev, name);
  1318. if (!ofnode_valid(plloff[i]))
  1319. continue;
  1320. ret = ofnode_read_u32_array(plloff[i], "cfg",
  1321. pllcfg[i], PLLCFG_NB);
  1322. if (ret < 0) {
  1323. debug("field cfg invalid: error %d\n", ret);
  1324. return -FDT_ERR_NOTFOUND;
  1325. }
  1326. }
  1327. debug("configuration MCO\n");
  1328. stm32mp1_mco_csg(priv, clksrc[CLKSRC_MCO1], clkdiv[CLKDIV_MCO1]);
  1329. stm32mp1_mco_csg(priv, clksrc[CLKSRC_MCO2], clkdiv[CLKDIV_MCO2]);
  1330. debug("switch ON osillator\n");
  1331. /*
  1332. * switch ON oscillator found in device-tree,
  1333. * HSI already ON after bootrom
  1334. */
  1335. if (priv->osc[_LSI])
  1336. stm32mp1_lsi_set(rcc, 1);
  1337. if (priv->osc[_LSE]) {
  1338. int bypass;
  1339. int lsedrv;
  1340. struct udevice *dev = priv->osc_dev[_LSE];
  1341. bypass = dev_read_bool(dev, "st,bypass");
  1342. lse_css = dev_read_bool(dev, "st,css");
  1343. lsedrv = dev_read_u32_default(dev, "st,drive",
  1344. LSEDRV_MEDIUM_HIGH);
  1345. stm32mp1_lse_enable(rcc, bypass, lsedrv);
  1346. }
  1347. if (priv->osc[_HSE]) {
  1348. int bypass, css;
  1349. struct udevice *dev = priv->osc_dev[_HSE];
  1350. bypass = dev_read_bool(dev, "st,bypass");
  1351. css = dev_read_bool(dev, "st,css");
  1352. stm32mp1_hse_enable(rcc, bypass, css);
  1353. }
  1354. /* CSI is mandatory for automatic I/O compensation (SYSCFG_CMPCR)
  1355. * => switch on CSI even if node is not present in device tree
  1356. */
  1357. stm32mp1_csi_set(rcc, 1);
  1358. /* come back to HSI */
  1359. debug("come back to HSI\n");
  1360. set_clksrc(priv, CLK_MPU_HSI);
  1361. set_clksrc(priv, CLK_AXI_HSI);
  1362. set_clksrc(priv, CLK_MCU_HSI);
  1363. debug("pll stop\n");
  1364. for (i = 0; i < _PLL_NB; i++)
  1365. pll_stop(priv, i);
  1366. /* configure HSIDIV */
  1367. debug("configure HSIDIV\n");
  1368. if (priv->osc[_HSI]) {
  1369. stm32mp1_hsidiv(rcc, priv->osc[_HSI]);
  1370. stgen_config(priv);
  1371. }
  1372. /* select DIV */
  1373. debug("select DIV\n");
  1374. /* no ready bit when MPUSRC != CLK_MPU_PLL1P_DIV, MPUDIV is disabled */
  1375. writel(clkdiv[CLKDIV_MPU] & RCC_DIVR_DIV_MASK, rcc + RCC_MPCKDIVR);
  1376. set_clkdiv(clkdiv[CLKDIV_AXI], rcc + RCC_AXIDIVR);
  1377. set_clkdiv(clkdiv[CLKDIV_APB4], rcc + RCC_APB4DIVR);
  1378. set_clkdiv(clkdiv[CLKDIV_APB5], rcc + RCC_APB5DIVR);
  1379. set_clkdiv(clkdiv[CLKDIV_MCU], rcc + RCC_MCUDIVR);
  1380. set_clkdiv(clkdiv[CLKDIV_APB1], rcc + RCC_APB1DIVR);
  1381. set_clkdiv(clkdiv[CLKDIV_APB2], rcc + RCC_APB2DIVR);
  1382. set_clkdiv(clkdiv[CLKDIV_APB3], rcc + RCC_APB3DIVR);
  1383. /* no ready bit for RTC */
  1384. writel(clkdiv[CLKDIV_RTC] & RCC_DIVR_DIV_MASK, rcc + RCC_RTCDIVR);
  1385. /* configure PLLs source */
  1386. debug("configure PLLs source\n");
  1387. set_clksrc(priv, clksrc[CLKSRC_PLL12]);
  1388. set_clksrc(priv, clksrc[CLKSRC_PLL3]);
  1389. set_clksrc(priv, clksrc[CLKSRC_PLL4]);
  1390. /* configure and start PLLs */
  1391. debug("configure PLLs\n");
  1392. for (i = 0; i < _PLL_NB; i++) {
  1393. u32 fracv;
  1394. u32 csg[PLLCSG_NB];
  1395. debug("configure PLL %d @ %d\n", i,
  1396. ofnode_to_offset(plloff[i]));
  1397. if (!ofnode_valid(plloff[i]))
  1398. continue;
  1399. fracv = ofnode_read_u32_default(plloff[i], "frac", 0);
  1400. pll_config(priv, i, pllcfg[i], fracv);
  1401. ret = ofnode_read_u32_array(plloff[i], "csg", csg, PLLCSG_NB);
  1402. if (!ret) {
  1403. pll_csg(priv, i, csg);
  1404. } else if (ret != -FDT_ERR_NOTFOUND) {
  1405. debug("invalid csg node for pll@%d res=%d\n", i, ret);
  1406. return ret;
  1407. }
  1408. pll_start(priv, i);
  1409. }
  1410. /* wait and start PLLs ouptut when ready */
  1411. for (i = 0; i < _PLL_NB; i++) {
  1412. if (!ofnode_valid(plloff[i]))
  1413. continue;
  1414. debug("output PLL %d\n", i);
  1415. pll_output(priv, i, pllcfg[i][PLLCFG_O]);
  1416. }
  1417. /* wait LSE ready before to use it */
  1418. if (priv->osc[_LSE])
  1419. stm32mp1_lse_wait(rcc);
  1420. /* configure with expected clock source */
  1421. debug("CLKSRC\n");
  1422. set_clksrc(priv, clksrc[CLKSRC_MPU]);
  1423. set_clksrc(priv, clksrc[CLKSRC_AXI]);
  1424. set_clksrc(priv, clksrc[CLKSRC_MCU]);
  1425. set_rtcsrc(priv, clksrc[CLKSRC_RTC], lse_css);
  1426. /* configure PKCK */
  1427. debug("PKCK\n");
  1428. pkcs_cell = dev_read_prop(dev, "st,pkcs", &len);
  1429. if (pkcs_cell) {
  1430. bool ckper_disabled = false;
  1431. for (i = 0; i < len / sizeof(u32); i++) {
  1432. u32 pkcs = (u32)fdt32_to_cpu(pkcs_cell[i]);
  1433. if (pkcs == CLK_CKPER_DISABLED) {
  1434. ckper_disabled = true;
  1435. continue;
  1436. }
  1437. pkcs_config(priv, pkcs);
  1438. }
  1439. /* CKPER is source for some peripheral clock
  1440. * (FMC-NAND / QPSI-NOR) and switching source is allowed
  1441. * only if previous clock is still ON
  1442. * => deactivated CKPER only after switching clock
  1443. */
  1444. if (ckper_disabled)
  1445. pkcs_config(priv, CLK_CKPER_DISABLED);
  1446. }
  1447. /* STGEN clock source can change with CLK_STGEN_XXX */
  1448. stgen_config(priv);
  1449. debug("oscillator off\n");
  1450. /* switch OFF HSI if not found in device-tree */
  1451. if (!priv->osc[_HSI])
  1452. stm32mp1_hsi_set(rcc, 0);
  1453. /* Software Self-Refresh mode (SSR) during DDR initilialization */
  1454. clrsetbits_le32(priv->base + RCC_DDRITFCR,
  1455. RCC_DDRITFCR_DDRCKMOD_MASK,
  1456. RCC_DDRITFCR_DDRCKMOD_SSR <<
  1457. RCC_DDRITFCR_DDRCKMOD_SHIFT);
  1458. return 0;
  1459. }
  1460. #endif /* STM32MP1_CLOCK_TREE_INIT */
  1461. static void stm32mp1_osc_clk_init(const char *name,
  1462. struct stm32mp1_clk_priv *priv,
  1463. int index)
  1464. {
  1465. struct clk clk;
  1466. struct udevice *dev = NULL;
  1467. priv->osc[index] = 0;
  1468. clk.id = 0;
  1469. if (!uclass_get_device_by_name(UCLASS_CLK, name, &dev)) {
  1470. if (clk_request(dev, &clk))
  1471. pr_err("%s request", name);
  1472. else
  1473. priv->osc[index] = clk_get_rate(&clk);
  1474. }
  1475. priv->osc_dev[index] = dev;
  1476. }
  1477. static void stm32mp1_osc_init(struct udevice *dev)
  1478. {
  1479. struct stm32mp1_clk_priv *priv = dev_get_priv(dev);
  1480. int i;
  1481. const char *name[NB_OSC] = {
  1482. [_LSI] = "clk-lsi",
  1483. [_LSE] = "clk-lse",
  1484. [_HSI] = "clk-hsi",
  1485. [_HSE] = "clk-hse",
  1486. [_CSI] = "clk-csi",
  1487. [_I2S_CKIN] = "i2s_ckin",
  1488. [_USB_PHY_48] = "ck_usbo_48m"};
  1489. for (i = 0; i < NB_OSC; i++) {
  1490. stm32mp1_osc_clk_init(name[i], priv, i);
  1491. debug("%d: %s => %x\n", i, name[i], (u32)priv->osc[i]);
  1492. }
  1493. }
  1494. static int stm32mp1_clk_probe(struct udevice *dev)
  1495. {
  1496. int result = 0;
  1497. struct stm32mp1_clk_priv *priv = dev_get_priv(dev);
  1498. priv->base = dev_read_addr(dev->parent);
  1499. if (priv->base == FDT_ADDR_T_NONE)
  1500. return -EINVAL;
  1501. priv->data = (void *)&stm32mp1_data;
  1502. if (!priv->data->gate || !priv->data->sel ||
  1503. !priv->data->pll)
  1504. return -EINVAL;
  1505. stm32mp1_osc_init(dev);
  1506. #ifdef STM32MP1_CLOCK_TREE_INIT
  1507. /* clock tree init is done only one time, before relocation */
  1508. if (!(gd->flags & GD_FLG_RELOC))
  1509. result = stm32mp1_clktree(dev);
  1510. #endif
  1511. return result;
  1512. }
  1513. static const struct clk_ops stm32mp1_clk_ops = {
  1514. .enable = stm32mp1_clk_enable,
  1515. .disable = stm32mp1_clk_disable,
  1516. .get_rate = stm32mp1_clk_get_rate,
  1517. };
  1518. U_BOOT_DRIVER(stm32mp1_clock) = {
  1519. .name = "stm32mp1_clk",
  1520. .id = UCLASS_CLK,
  1521. .ops = &stm32mp1_clk_ops,
  1522. .priv_auto_alloc_size = sizeof(struct stm32mp1_clk_priv),
  1523. .probe = stm32mp1_clk_probe,
  1524. };