imx_lpi2c.c 12 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2016 Freescale Semiconductors, Inc.
  4. */
  5. #include <common.h>
  6. #include <errno.h>
  7. #include <asm/io.h>
  8. #include <asm/arch/clock.h>
  9. #include <asm/arch/imx-regs.h>
  10. #include <imx_lpi2c.h>
  11. #include <asm/arch/sys_proto.h>
  12. #include <dm.h>
  13. #include <fdtdec.h>
  14. #include <i2c.h>
  15. #define LPI2C_FIFO_SIZE 4
  16. #define LPI2C_NACK_TOUT_MS 1
  17. #define LPI2C_TIMEOUT_MS 100
  18. static int bus_i2c_init(struct udevice *bus, int speed);
  19. /* Weak linked function for overridden by some SoC power function */
  20. int __weak init_i2c_power(unsigned i2c_num)
  21. {
  22. return 0;
  23. }
  24. static int imx_lpci2c_check_busy_bus(const struct imx_lpi2c_reg *regs)
  25. {
  26. lpi2c_status_t result = LPI2C_SUCESS;
  27. u32 status;
  28. status = readl(&regs->msr);
  29. if ((status & LPI2C_MSR_BBF_MASK) && !(status & LPI2C_MSR_MBF_MASK))
  30. result = LPI2C_BUSY;
  31. return result;
  32. }
  33. static int imx_lpci2c_check_clear_error(struct imx_lpi2c_reg *regs)
  34. {
  35. lpi2c_status_t result = LPI2C_SUCESS;
  36. u32 val, status;
  37. status = readl(&regs->msr);
  38. /* errors to check for */
  39. status &= LPI2C_MSR_NDF_MASK | LPI2C_MSR_ALF_MASK |
  40. LPI2C_MSR_FEF_MASK | LPI2C_MSR_PLTF_MASK;
  41. if (status) {
  42. if (status & LPI2C_MSR_PLTF_MASK)
  43. result = LPI2C_PIN_LOW_TIMEOUT_ERR;
  44. else if (status & LPI2C_MSR_ALF_MASK)
  45. result = LPI2C_ARB_LOST_ERR;
  46. else if (status & LPI2C_MSR_NDF_MASK)
  47. result = LPI2C_NAK_ERR;
  48. else if (status & LPI2C_MSR_FEF_MASK)
  49. result = LPI2C_FIFO_ERR;
  50. /* clear status flags */
  51. writel(0x7f00, &regs->msr);
  52. /* reset fifos */
  53. val = readl(&regs->mcr);
  54. val |= LPI2C_MCR_RRF_MASK | LPI2C_MCR_RTF_MASK;
  55. writel(val, &regs->mcr);
  56. }
  57. return result;
  58. }
  59. static int bus_i2c_wait_for_tx_ready(struct imx_lpi2c_reg *regs)
  60. {
  61. lpi2c_status_t result = LPI2C_SUCESS;
  62. u32 txcount = 0;
  63. ulong start_time = get_timer(0);
  64. do {
  65. txcount = LPI2C_MFSR_TXCOUNT(readl(&regs->mfsr));
  66. txcount = LPI2C_FIFO_SIZE - txcount;
  67. result = imx_lpci2c_check_clear_error(regs);
  68. if (result) {
  69. debug("i2c: wait for tx ready: result 0x%x\n", result);
  70. return result;
  71. }
  72. if (get_timer(start_time) > LPI2C_TIMEOUT_MS) {
  73. debug("i2c: wait for tx ready: timeout\n");
  74. return -1;
  75. }
  76. } while (!txcount);
  77. return result;
  78. }
  79. static int bus_i2c_send(struct udevice *bus, u8 *txbuf, int len)
  80. {
  81. struct imx_lpi2c_reg *regs = (struct imx_lpi2c_reg *)devfdt_get_addr(bus);
  82. lpi2c_status_t result = LPI2C_SUCESS;
  83. /* empty tx */
  84. if (!len)
  85. return result;
  86. while (len--) {
  87. result = bus_i2c_wait_for_tx_ready(regs);
  88. if (result) {
  89. debug("i2c: send wait for tx ready: %d\n", result);
  90. return result;
  91. }
  92. writel(*txbuf++, &regs->mtdr);
  93. }
  94. return result;
  95. }
  96. static int bus_i2c_receive(struct udevice *bus, u8 *rxbuf, int len)
  97. {
  98. struct imx_lpi2c_reg *regs = (struct imx_lpi2c_reg *)devfdt_get_addr(bus);
  99. lpi2c_status_t result = LPI2C_SUCESS;
  100. u32 val;
  101. ulong start_time = get_timer(0);
  102. /* empty read */
  103. if (!len)
  104. return result;
  105. result = bus_i2c_wait_for_tx_ready(regs);
  106. if (result) {
  107. debug("i2c: receive wait fot tx ready: %d\n", result);
  108. return result;
  109. }
  110. /* clear all status flags */
  111. writel(0x7f00, &regs->msr);
  112. /* send receive command */
  113. val = LPI2C_MTDR_CMD(0x1) | LPI2C_MTDR_DATA(len - 1);
  114. writel(val, &regs->mtdr);
  115. while (len--) {
  116. do {
  117. result = imx_lpci2c_check_clear_error(regs);
  118. if (result) {
  119. debug("i2c: receive check clear error: %d\n",
  120. result);
  121. return result;
  122. }
  123. if (get_timer(start_time) > LPI2C_TIMEOUT_MS) {
  124. debug("i2c: receive mrdr: timeout\n");
  125. return -1;
  126. }
  127. val = readl(&regs->mrdr);
  128. } while (val & LPI2C_MRDR_RXEMPTY_MASK);
  129. *rxbuf++ = LPI2C_MRDR_DATA(val);
  130. }
  131. return result;
  132. }
  133. static int bus_i2c_start(struct udevice *bus, u8 addr, u8 dir)
  134. {
  135. lpi2c_status_t result;
  136. struct imx_lpi2c_reg *regs =
  137. (struct imx_lpi2c_reg *)devfdt_get_addr(bus);
  138. u32 val;
  139. result = imx_lpci2c_check_busy_bus(regs);
  140. if (result) {
  141. debug("i2c: start check busy bus: 0x%x\n", result);
  142. /* Try to init the lpi2c then check the bus busy again */
  143. bus_i2c_init(bus, 100000);
  144. result = imx_lpci2c_check_busy_bus(regs);
  145. if (result) {
  146. printf("i2c: Error check busy bus: 0x%x\n", result);
  147. return result;
  148. }
  149. }
  150. /* clear all status flags */
  151. writel(0x7f00, &regs->msr);
  152. /* turn off auto-stop condition */
  153. val = readl(&regs->mcfgr1) & ~LPI2C_MCFGR1_AUTOSTOP_MASK;
  154. writel(val, &regs->mcfgr1);
  155. /* wait tx fifo ready */
  156. result = bus_i2c_wait_for_tx_ready(regs);
  157. if (result) {
  158. debug("i2c: start wait for tx ready: 0x%x\n", result);
  159. return result;
  160. }
  161. /* issue start command */
  162. val = LPI2C_MTDR_CMD(0x4) | (addr << 0x1) | dir;
  163. writel(val, &regs->mtdr);
  164. return result;
  165. }
  166. static int bus_i2c_stop(struct udevice *bus)
  167. {
  168. lpi2c_status_t result;
  169. struct imx_lpi2c_reg *regs =
  170. (struct imx_lpi2c_reg *)devfdt_get_addr(bus);
  171. u32 status;
  172. ulong start_time;
  173. result = bus_i2c_wait_for_tx_ready(regs);
  174. if (result) {
  175. debug("i2c: stop wait for tx ready: 0x%x\n", result);
  176. return result;
  177. }
  178. /* send stop command */
  179. writel(LPI2C_MTDR_CMD(0x2), &regs->mtdr);
  180. start_time = get_timer(0);
  181. while (1) {
  182. status = readl(&regs->msr);
  183. result = imx_lpci2c_check_clear_error(regs);
  184. /* stop detect flag */
  185. if (status & LPI2C_MSR_SDF_MASK) {
  186. /* clear stop flag */
  187. status &= LPI2C_MSR_SDF_MASK;
  188. writel(status, &regs->msr);
  189. break;
  190. }
  191. if (get_timer(start_time) > LPI2C_NACK_TOUT_MS) {
  192. debug("stop timeout\n");
  193. return -ETIMEDOUT;
  194. }
  195. }
  196. return result;
  197. }
  198. static int bus_i2c_read(struct udevice *bus, u32 chip, u8 *buf, int len)
  199. {
  200. lpi2c_status_t result;
  201. result = bus_i2c_start(bus, chip, 1);
  202. if (result)
  203. return result;
  204. result = bus_i2c_receive(bus, buf, len);
  205. if (result)
  206. return result;
  207. return result;
  208. }
  209. static int bus_i2c_write(struct udevice *bus, u32 chip, u8 *buf, int len)
  210. {
  211. lpi2c_status_t result;
  212. result = bus_i2c_start(bus, chip, 0);
  213. if (result)
  214. return result;
  215. result = bus_i2c_send(bus, buf, len);
  216. if (result)
  217. return result;
  218. return result;
  219. }
  220. u32 __weak imx_get_i2cclk(u32 i2c_num)
  221. {
  222. return 0;
  223. }
  224. static int bus_i2c_set_bus_speed(struct udevice *bus, int speed)
  225. {
  226. struct imx_lpi2c_bus *i2c_bus = dev_get_priv(bus);
  227. struct imx_lpi2c_reg *regs;
  228. u32 val;
  229. u32 preescale = 0, best_pre = 0, clkhi = 0;
  230. u32 best_clkhi = 0, abs_error = 0, rate;
  231. u32 error = 0xffffffff;
  232. u32 clock_rate;
  233. bool mode;
  234. int i;
  235. regs = (struct imx_lpi2c_reg *)devfdt_get_addr(bus);
  236. if (IS_ENABLED(CONFIG_CLK)) {
  237. clock_rate = clk_get_rate(&i2c_bus->per_clk);
  238. if (clock_rate <= 0) {
  239. dev_err(bus, "Failed to get i2c clk: %d\n", clock_rate);
  240. return clock_rate;
  241. }
  242. } else {
  243. clock_rate = imx_get_i2cclk(bus->seq);
  244. if (!clock_rate)
  245. return -EPERM;
  246. }
  247. mode = (readl(&regs->mcr) & LPI2C_MCR_MEN_MASK) >> LPI2C_MCR_MEN_SHIFT;
  248. /* disable master mode */
  249. val = readl(&regs->mcr) & ~LPI2C_MCR_MEN_MASK;
  250. writel(val | LPI2C_MCR_MEN(0), &regs->mcr);
  251. for (preescale = 1; (preescale <= 128) &&
  252. (error != 0); preescale = 2 * preescale) {
  253. for (clkhi = 1; clkhi < 32; clkhi++) {
  254. if (clkhi == 1)
  255. rate = (clock_rate / preescale) / (1 + 3 + 2 + 2 / preescale);
  256. else
  257. rate = (clock_rate / preescale / (3 * clkhi + 2 + 2 / preescale));
  258. abs_error = speed > rate ? speed - rate : rate - speed;
  259. if (abs_error < error) {
  260. best_pre = preescale;
  261. best_clkhi = clkhi;
  262. error = abs_error;
  263. if (abs_error == 0)
  264. break;
  265. }
  266. }
  267. }
  268. /* Standard, fast, fast mode plus and ultra-fast transfers. */
  269. val = LPI2C_MCCR0_CLKHI(best_clkhi);
  270. if (best_clkhi < 2)
  271. val |= LPI2C_MCCR0_CLKLO(3) | LPI2C_MCCR0_SETHOLD(2) | LPI2C_MCCR0_DATAVD(1);
  272. else
  273. val |= LPI2C_MCCR0_CLKLO(2 * best_clkhi) | LPI2C_MCCR0_SETHOLD(best_clkhi) |
  274. LPI2C_MCCR0_DATAVD(best_clkhi / 2);
  275. writel(val, &regs->mccr0);
  276. for (i = 0; i < 8; i++) {
  277. if (best_pre == (1 << i)) {
  278. best_pre = i;
  279. break;
  280. }
  281. }
  282. val = readl(&regs->mcfgr1) & ~LPI2C_MCFGR1_PRESCALE_MASK;
  283. writel(val | LPI2C_MCFGR1_PRESCALE(best_pre), &regs->mcfgr1);
  284. if (mode) {
  285. val = readl(&regs->mcr) & ~LPI2C_MCR_MEN_MASK;
  286. writel(val | LPI2C_MCR_MEN(1), &regs->mcr);
  287. }
  288. return 0;
  289. }
  290. static int bus_i2c_init(struct udevice *bus, int speed)
  291. {
  292. struct imx_lpi2c_reg *regs;
  293. u32 val;
  294. int ret;
  295. regs = (struct imx_lpi2c_reg *)devfdt_get_addr(bus);
  296. /* reset peripheral */
  297. writel(LPI2C_MCR_RST_MASK, &regs->mcr);
  298. writel(0x0, &regs->mcr);
  299. /* Disable Dozen mode */
  300. writel(LPI2C_MCR_DBGEN(0) | LPI2C_MCR_DOZEN(1), &regs->mcr);
  301. /* host request disable, active high, external pin */
  302. val = readl(&regs->mcfgr0);
  303. val &= (~(LPI2C_MCFGR0_HREN_MASK | LPI2C_MCFGR0_HRPOL_MASK |
  304. LPI2C_MCFGR0_HRSEL_MASK));
  305. val |= LPI2C_MCFGR0_HRPOL(0x1);
  306. writel(val, &regs->mcfgr0);
  307. /* pincfg and ignore ack */
  308. val = readl(&regs->mcfgr1);
  309. val &= ~(LPI2C_MCFGR1_PINCFG_MASK | LPI2C_MCFGR1_IGNACK_MASK);
  310. val |= LPI2C_MCFGR1_PINCFG(0x0); /* 2 pin open drain */
  311. val |= LPI2C_MCFGR1_IGNACK(0x0); /* ignore nack */
  312. writel(val, &regs->mcfgr1);
  313. ret = bus_i2c_set_bus_speed(bus, speed);
  314. /* enable lpi2c in master mode */
  315. val = readl(&regs->mcr) & ~LPI2C_MCR_MEN_MASK;
  316. writel(val | LPI2C_MCR_MEN(1), &regs->mcr);
  317. debug("i2c : controller bus %d, speed %d:\n", bus->seq, speed);
  318. return ret;
  319. }
  320. static int imx_lpi2c_probe_chip(struct udevice *bus, u32 chip,
  321. u32 chip_flags)
  322. {
  323. lpi2c_status_t result;
  324. result = bus_i2c_start(bus, chip, 0);
  325. if (result) {
  326. bus_i2c_stop(bus);
  327. bus_i2c_init(bus, 100000);
  328. return result;
  329. }
  330. result = bus_i2c_stop(bus);
  331. if (result)
  332. bus_i2c_init(bus, 100000);
  333. return result;
  334. }
  335. static int imx_lpi2c_xfer(struct udevice *bus, struct i2c_msg *msg, int nmsgs)
  336. {
  337. int ret = 0, ret_stop;
  338. for (; nmsgs > 0; nmsgs--, msg++) {
  339. debug("i2c_xfer: chip=0x%x, len=0x%x\n", msg->addr, msg->len);
  340. if (msg->flags & I2C_M_RD)
  341. ret = bus_i2c_read(bus, msg->addr, msg->buf, msg->len);
  342. else {
  343. ret = bus_i2c_write(bus, msg->addr, msg->buf,
  344. msg->len);
  345. if (ret)
  346. break;
  347. }
  348. }
  349. if (ret)
  350. debug("i2c_write: error sending\n");
  351. ret_stop = bus_i2c_stop(bus);
  352. if (ret_stop)
  353. debug("i2c_xfer: stop bus error\n");
  354. ret |= ret_stop;
  355. return ret;
  356. }
  357. static int imx_lpi2c_set_bus_speed(struct udevice *bus, unsigned int speed)
  358. {
  359. return bus_i2c_set_bus_speed(bus, speed);
  360. }
  361. __weak int enable_i2c_clk(unsigned char enable, unsigned int i2c_num)
  362. {
  363. return 0;
  364. }
  365. static int imx_lpi2c_probe(struct udevice *bus)
  366. {
  367. struct imx_lpi2c_bus *i2c_bus = dev_get_priv(bus);
  368. fdt_addr_t addr;
  369. int ret;
  370. i2c_bus->driver_data = dev_get_driver_data(bus);
  371. addr = devfdt_get_addr(bus);
  372. if (addr == FDT_ADDR_T_NONE)
  373. return -EINVAL;
  374. i2c_bus->base = addr;
  375. i2c_bus->index = bus->seq;
  376. i2c_bus->bus = bus;
  377. /* power up i2c resource */
  378. ret = init_i2c_power(bus->seq);
  379. if (ret) {
  380. debug("init_i2c_power err = %d\n", ret);
  381. return ret;
  382. }
  383. if (IS_ENABLED(CONFIG_CLK)) {
  384. ret = clk_get_by_name(bus, "per", &i2c_bus->per_clk);
  385. if (ret) {
  386. dev_err(bus, "Failed to get per clk\n");
  387. return ret;
  388. }
  389. ret = clk_enable(&i2c_bus->per_clk);
  390. if (ret) {
  391. dev_err(bus, "Failed to enable per clk\n");
  392. return ret;
  393. }
  394. ret = clk_get_by_name(bus, "ipg", &i2c_bus->ipg_clk);
  395. if (ret) {
  396. dev_err(bus, "Failed to get ipg clk\n");
  397. return ret;
  398. }
  399. ret = clk_enable(&i2c_bus->ipg_clk);
  400. if (ret) {
  401. dev_err(bus, "Failed to enable ipg clk\n");
  402. return ret;
  403. }
  404. } else {
  405. /* To i.MX7ULP, only i2c4-7 can be handled by A7 core */
  406. ret = enable_i2c_clk(1, bus->seq);
  407. if (ret < 0)
  408. return ret;
  409. }
  410. ret = bus_i2c_init(bus, 100000);
  411. if (ret < 0)
  412. return ret;
  413. debug("i2c : controller bus %d at 0x%lx , speed %d: ",
  414. bus->seq, i2c_bus->base,
  415. i2c_bus->speed);
  416. return 0;
  417. }
  418. static const struct dm_i2c_ops imx_lpi2c_ops = {
  419. .xfer = imx_lpi2c_xfer,
  420. .probe_chip = imx_lpi2c_probe_chip,
  421. .set_bus_speed = imx_lpi2c_set_bus_speed,
  422. };
  423. static const struct udevice_id imx_lpi2c_ids[] = {
  424. { .compatible = "fsl,imx7ulp-lpi2c", },
  425. { .compatible = "fsl,imx8qm-lpi2c", },
  426. {}
  427. };
  428. U_BOOT_DRIVER(imx_lpi2c) = {
  429. .name = "imx_lpi2c",
  430. .id = UCLASS_I2C,
  431. .of_match = imx_lpi2c_ids,
  432. .probe = imx_lpi2c_probe,
  433. .priv_auto_alloc_size = sizeof(struct imx_lpi2c_bus),
  434. .ops = &imx_lpi2c_ops,
  435. };