hrcon.c 9.9 KB

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  1. /*
  2. * (C) Copyright 2014
  3. * Dirk Eibach, Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc
  4. *
  5. * SPDX-License-Identifier: GPL-2.0+
  6. */
  7. #include <common.h>
  8. #include <hwconfig.h>
  9. #include <i2c.h>
  10. #include <spi.h>
  11. #include <linux/libfdt.h>
  12. #include <fdt_support.h>
  13. #include <pci.h>
  14. #include <mpc83xx.h>
  15. #include <fsl_esdhc.h>
  16. #include <asm/io.h>
  17. #include <asm/fsl_serdes.h>
  18. #include <asm/fsl_mpc83xx_serdes.h>
  19. #include "mpc8308.h"
  20. #include <gdsys_fpga.h>
  21. #include "../common/ioep-fpga.h"
  22. #include "../common/osd.h"
  23. #include "../common/mclink.h"
  24. #include "../common/phy.h"
  25. #include "../common/fanctrl.h"
  26. #include <pca953x.h>
  27. #include <pca9698.h>
  28. #include <miiphy.h>
  29. #define MAX_MUX_CHANNELS 2
  30. enum {
  31. MCFPGA_DONE = 1 << 0,
  32. MCFPGA_INIT_N = 1 << 1,
  33. MCFPGA_PROGRAM_N = 1 << 2,
  34. MCFPGA_UPDATE_ENABLE_N = 1 << 3,
  35. MCFPGA_RESET_N = 1 << 4,
  36. };
  37. enum {
  38. GPIO_MDC = 1 << 14,
  39. GPIO_MDIO = 1 << 15,
  40. };
  41. unsigned int mclink_fpgacount;
  42. struct ihs_fpga *fpga_ptr[] = CONFIG_SYS_FPGA_PTR;
  43. struct {
  44. u8 bus;
  45. u8 addr;
  46. } hrcon_fans[] = CONFIG_HRCON_FANS;
  47. int fpga_set_reg(u32 fpga, u16 *reg, off_t regoff, u16 data)
  48. {
  49. int res;
  50. switch (fpga) {
  51. case 0:
  52. out_le16(reg, data);
  53. break;
  54. default:
  55. res = mclink_send(fpga - 1, regoff, data);
  56. if (res < 0) {
  57. printf("mclink_send reg %02lx data %04x returned %d\n",
  58. regoff, data, res);
  59. return res;
  60. }
  61. break;
  62. }
  63. return 0;
  64. }
  65. int fpga_get_reg(u32 fpga, u16 *reg, off_t regoff, u16 *data)
  66. {
  67. int res;
  68. switch (fpga) {
  69. case 0:
  70. *data = in_le16(reg);
  71. break;
  72. default:
  73. if (fpga > mclink_fpgacount)
  74. return -EINVAL;
  75. res = mclink_receive(fpga - 1, regoff, data);
  76. if (res < 0) {
  77. printf("mclink_receive reg %02lx returned %d\n",
  78. regoff, res);
  79. return res;
  80. }
  81. }
  82. return 0;
  83. }
  84. int checkboard(void)
  85. {
  86. char *s = env_get("serial#");
  87. bool hw_type_cat = pca9698_get_value(0x20, 20);
  88. puts("Board: ");
  89. printf("HRCon %s", hw_type_cat ? "CAT" : "Fiber");
  90. if (s != NULL) {
  91. puts(", serial# ");
  92. puts(s);
  93. }
  94. puts("\n");
  95. return 0;
  96. }
  97. int last_stage_init(void)
  98. {
  99. int slaves;
  100. unsigned int k;
  101. unsigned int mux_ch;
  102. unsigned char mclink_controllers[] = { 0x3c, 0x3d, 0x3e };
  103. u16 fpga_features;
  104. bool hw_type_cat = pca9698_get_value(0x20, 20);
  105. bool ch0_rgmii2_present = false;
  106. FPGA_GET_REG(0, fpga_features, &fpga_features);
  107. /* Turn on Parade DP501 */
  108. pca9698_direction_output(0x20, 10, 1);
  109. pca9698_direction_output(0x20, 11, 1);
  110. ch0_rgmii2_present = !pca9698_get_value(0x20, 30);
  111. /* wait for FPGA done, then reset FPGA */
  112. for (k = 0; k < ARRAY_SIZE(mclink_controllers); ++k) {
  113. unsigned int ctr = 0;
  114. if (i2c_probe(mclink_controllers[k]))
  115. continue;
  116. while (!(pca953x_get_val(mclink_controllers[k])
  117. & MCFPGA_DONE)) {
  118. udelay(100000);
  119. if (ctr++ > 5) {
  120. printf("no done for mclink_controller %d\n", k);
  121. break;
  122. }
  123. }
  124. pca953x_set_dir(mclink_controllers[k], MCFPGA_RESET_N, 0);
  125. pca953x_set_val(mclink_controllers[k], MCFPGA_RESET_N, 0);
  126. udelay(10);
  127. pca953x_set_val(mclink_controllers[k], MCFPGA_RESET_N,
  128. MCFPGA_RESET_N);
  129. }
  130. if (hw_type_cat) {
  131. int retval;
  132. struct mii_dev *mdiodev = mdio_alloc();
  133. if (!mdiodev)
  134. return -ENOMEM;
  135. strncpy(mdiodev->name, bb_miiphy_buses[0].name, MDIO_NAME_LEN);
  136. mdiodev->read = bb_miiphy_read;
  137. mdiodev->write = bb_miiphy_write;
  138. retval = mdio_register(mdiodev);
  139. if (retval < 0)
  140. return retval;
  141. for (mux_ch = 0; mux_ch < MAX_MUX_CHANNELS; ++mux_ch) {
  142. if ((mux_ch == 1) && !ch0_rgmii2_present)
  143. continue;
  144. setup_88e1514(bb_miiphy_buses[0].name, mux_ch);
  145. }
  146. }
  147. /* give slave-PLLs and Parade DP501 some time to be up and running */
  148. udelay(500000);
  149. mclink_fpgacount = CONFIG_SYS_MCLINK_MAX;
  150. slaves = mclink_probe();
  151. mclink_fpgacount = 0;
  152. ioep_fpga_print_info(0);
  153. osd_probe(0);
  154. #ifdef CONFIG_SYS_OSD_DH
  155. osd_probe(4);
  156. #endif
  157. if (slaves <= 0)
  158. return 0;
  159. mclink_fpgacount = slaves;
  160. for (k = 1; k <= slaves; ++k) {
  161. FPGA_GET_REG(k, fpga_features, &fpga_features);
  162. ioep_fpga_print_info(k);
  163. osd_probe(k);
  164. #ifdef CONFIG_SYS_OSD_DH
  165. osd_probe(k + 4);
  166. #endif
  167. if (hw_type_cat) {
  168. int retval;
  169. struct mii_dev *mdiodev = mdio_alloc();
  170. if (!mdiodev)
  171. return -ENOMEM;
  172. strncpy(mdiodev->name, bb_miiphy_buses[k].name,
  173. MDIO_NAME_LEN);
  174. mdiodev->read = bb_miiphy_read;
  175. mdiodev->write = bb_miiphy_write;
  176. retval = mdio_register(mdiodev);
  177. if (retval < 0)
  178. return retval;
  179. setup_88e1514(bb_miiphy_buses[k].name, 0);
  180. }
  181. }
  182. for (k = 0; k < ARRAY_SIZE(hrcon_fans); ++k) {
  183. i2c_set_bus_num(hrcon_fans[k].bus);
  184. init_fan_controller(hrcon_fans[k].addr);
  185. }
  186. return 0;
  187. }
  188. /*
  189. * provide access to fpga gpios and controls (for I2C bitbang)
  190. * (these may look all too simple but make iocon.h much more readable)
  191. */
  192. void fpga_gpio_set(unsigned int bus, int pin)
  193. {
  194. FPGA_SET_REG(bus >= 4 ? (bus - 4) : bus, gpio.set, pin);
  195. }
  196. void fpga_gpio_clear(unsigned int bus, int pin)
  197. {
  198. FPGA_SET_REG(bus >= 4 ? (bus - 4) : bus, gpio.clear, pin);
  199. }
  200. int fpga_gpio_get(unsigned int bus, int pin)
  201. {
  202. u16 val;
  203. FPGA_GET_REG(bus >= 4 ? (bus - 4) : bus, gpio.read, &val);
  204. return val & pin;
  205. }
  206. void fpga_control_set(unsigned int bus, int pin)
  207. {
  208. u16 val;
  209. FPGA_GET_REG(bus >= 4 ? (bus - 4) : bus, control, &val);
  210. FPGA_SET_REG(bus >= 4 ? (bus - 4) : bus, control, val | pin);
  211. }
  212. void fpga_control_clear(unsigned int bus, int pin)
  213. {
  214. u16 val;
  215. FPGA_GET_REG(bus >= 4 ? (bus - 4) : bus, control, &val);
  216. FPGA_SET_REG(bus >= 4 ? (bus - 4) : bus, control, val & ~pin);
  217. }
  218. void mpc8308_init(void)
  219. {
  220. pca9698_direction_output(0x20, 4, 1);
  221. }
  222. void mpc8308_set_fpga_reset(unsigned state)
  223. {
  224. pca9698_set_value(0x20, 4, state ? 0 : 1);
  225. }
  226. void mpc8308_setup_hw(void)
  227. {
  228. immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
  229. /*
  230. * set "startup-finished"-gpios
  231. */
  232. setbits_be32(&immr->gpio[0].dir, (1 << (31-11)) | (1 << (31-12)));
  233. setbits_be32(&immr->gpio[0].dat, 1 << (31-12));
  234. }
  235. int mpc8308_get_fpga_done(unsigned fpga)
  236. {
  237. return pca9698_get_value(0x20, 19);
  238. }
  239. #ifdef CONFIG_FSL_ESDHC
  240. int board_mmc_init(bd_t *bd)
  241. {
  242. immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
  243. sysconf83xx_t *sysconf = &immr->sysconf;
  244. /* Enable cache snooping in eSDHC system configuration register */
  245. out_be32(&sysconf->sdhccr, 0x02000000);
  246. return fsl_esdhc_mmc_init(bd);
  247. }
  248. #endif
  249. static struct pci_region pcie_regions_0[] = {
  250. {
  251. .bus_start = CONFIG_SYS_PCIE1_MEM_BASE,
  252. .phys_start = CONFIG_SYS_PCIE1_MEM_PHYS,
  253. .size = CONFIG_SYS_PCIE1_MEM_SIZE,
  254. .flags = PCI_REGION_MEM,
  255. },
  256. {
  257. .bus_start = CONFIG_SYS_PCIE1_IO_BASE,
  258. .phys_start = CONFIG_SYS_PCIE1_IO_PHYS,
  259. .size = CONFIG_SYS_PCIE1_IO_SIZE,
  260. .flags = PCI_REGION_IO,
  261. },
  262. };
  263. void pci_init_board(void)
  264. {
  265. immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
  266. sysconf83xx_t *sysconf = &immr->sysconf;
  267. law83xx_t *pcie_law = sysconf->pcielaw;
  268. struct pci_region *pcie_reg[] = { pcie_regions_0 };
  269. fsl_setup_serdes(CONFIG_FSL_SERDES1, FSL_SERDES_PROTO_PEX,
  270. FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
  271. /* Deassert the resets in the control register */
  272. out_be32(&sysconf->pecr1, 0xE0008000);
  273. udelay(2000);
  274. /* Configure PCI Express Local Access Windows */
  275. out_be32(&pcie_law[0].bar, CONFIG_SYS_PCIE1_BASE & LAWBAR_BAR);
  276. out_be32(&pcie_law[0].ar, LBLAWAR_EN | LBLAWAR_512MB);
  277. mpc83xx_pcie_init(1, pcie_reg);
  278. }
  279. ulong board_flash_get_legacy(ulong base, int banknum, flash_info_t *info)
  280. {
  281. info->portwidth = FLASH_CFI_16BIT;
  282. info->chipwidth = FLASH_CFI_BY16;
  283. info->interface = FLASH_CFI_X16;
  284. return 1;
  285. }
  286. #if defined(CONFIG_OF_BOARD_SETUP)
  287. int ft_board_setup(void *blob, bd_t *bd)
  288. {
  289. ft_cpu_setup(blob, bd);
  290. fsl_fdt_fixup_dr_usb(blob, bd);
  291. fdt_fixup_esdhc(blob, bd);
  292. return 0;
  293. }
  294. #endif
  295. /*
  296. * FPGA MII bitbang implementation
  297. */
  298. struct fpga_mii {
  299. unsigned fpga;
  300. int mdio;
  301. } fpga_mii[] = {
  302. { 0, 1},
  303. { 1, 1},
  304. { 2, 1},
  305. { 3, 1},
  306. };
  307. static int mii_dummy_init(struct bb_miiphy_bus *bus)
  308. {
  309. return 0;
  310. }
  311. static int mii_mdio_active(struct bb_miiphy_bus *bus)
  312. {
  313. struct fpga_mii *fpga_mii = bus->priv;
  314. if (fpga_mii->mdio)
  315. FPGA_SET_REG(fpga_mii->fpga, gpio.set, GPIO_MDIO);
  316. else
  317. FPGA_SET_REG(fpga_mii->fpga, gpio.clear, GPIO_MDIO);
  318. return 0;
  319. }
  320. static int mii_mdio_tristate(struct bb_miiphy_bus *bus)
  321. {
  322. struct fpga_mii *fpga_mii = bus->priv;
  323. FPGA_SET_REG(fpga_mii->fpga, gpio.set, GPIO_MDIO);
  324. return 0;
  325. }
  326. static int mii_set_mdio(struct bb_miiphy_bus *bus, int v)
  327. {
  328. struct fpga_mii *fpga_mii = bus->priv;
  329. if (v)
  330. FPGA_SET_REG(fpga_mii->fpga, gpio.set, GPIO_MDIO);
  331. else
  332. FPGA_SET_REG(fpga_mii->fpga, gpio.clear, GPIO_MDIO);
  333. fpga_mii->mdio = v;
  334. return 0;
  335. }
  336. static int mii_get_mdio(struct bb_miiphy_bus *bus, int *v)
  337. {
  338. u16 gpio;
  339. struct fpga_mii *fpga_mii = bus->priv;
  340. FPGA_GET_REG(fpga_mii->fpga, gpio.read, &gpio);
  341. *v = ((gpio & GPIO_MDIO) != 0);
  342. return 0;
  343. }
  344. static int mii_set_mdc(struct bb_miiphy_bus *bus, int v)
  345. {
  346. struct fpga_mii *fpga_mii = bus->priv;
  347. if (v)
  348. FPGA_SET_REG(fpga_mii->fpga, gpio.set, GPIO_MDC);
  349. else
  350. FPGA_SET_REG(fpga_mii->fpga, gpio.clear, GPIO_MDC);
  351. return 0;
  352. }
  353. static int mii_delay(struct bb_miiphy_bus *bus)
  354. {
  355. udelay(1);
  356. return 0;
  357. }
  358. struct bb_miiphy_bus bb_miiphy_buses[] = {
  359. {
  360. .name = "board0",
  361. .init = mii_dummy_init,
  362. .mdio_active = mii_mdio_active,
  363. .mdio_tristate = mii_mdio_tristate,
  364. .set_mdio = mii_set_mdio,
  365. .get_mdio = mii_get_mdio,
  366. .set_mdc = mii_set_mdc,
  367. .delay = mii_delay,
  368. .priv = &fpga_mii[0],
  369. },
  370. {
  371. .name = "board1",
  372. .init = mii_dummy_init,
  373. .mdio_active = mii_mdio_active,
  374. .mdio_tristate = mii_mdio_tristate,
  375. .set_mdio = mii_set_mdio,
  376. .get_mdio = mii_get_mdio,
  377. .set_mdc = mii_set_mdc,
  378. .delay = mii_delay,
  379. .priv = &fpga_mii[1],
  380. },
  381. {
  382. .name = "board2",
  383. .init = mii_dummy_init,
  384. .mdio_active = mii_mdio_active,
  385. .mdio_tristate = mii_mdio_tristate,
  386. .set_mdio = mii_set_mdio,
  387. .get_mdio = mii_get_mdio,
  388. .set_mdc = mii_set_mdc,
  389. .delay = mii_delay,
  390. .priv = &fpga_mii[2],
  391. },
  392. {
  393. .name = "board3",
  394. .init = mii_dummy_init,
  395. .mdio_active = mii_mdio_active,
  396. .mdio_tristate = mii_mdio_tristate,
  397. .set_mdio = mii_set_mdio,
  398. .get_mdio = mii_get_mdio,
  399. .set_mdc = mii_set_mdc,
  400. .delay = mii_delay,
  401. .priv = &fpga_mii[3],
  402. },
  403. };
  404. int bb_miiphy_buses_num = sizeof(bb_miiphy_buses) /
  405. sizeof(bb_miiphy_buses[0]);