p1022ds.c 8.8 KB

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  1. /*
  2. * Copyright 2010-2012 Freescale Semiconductor, Inc.
  3. * Authors: Srikanth Srinivasan <srikanth.srinivasan@freescale.com>
  4. * Timur Tabi <timur@freescale.com>
  5. *
  6. * SPDX-License-Identifier: GPL-2.0+
  7. */
  8. #include <common.h>
  9. #include <command.h>
  10. #include <pci.h>
  11. #include <asm/processor.h>
  12. #include <asm/mmu.h>
  13. #include <asm/cache.h>
  14. #include <asm/immap_85xx.h>
  15. #include <asm/fsl_pci.h>
  16. #include <fsl_ddr_sdram.h>
  17. #include <asm/fsl_serdes.h>
  18. #include <asm/io.h>
  19. #include <linux/libfdt.h>
  20. #include <fdt_support.h>
  21. #include <fsl_mdio.h>
  22. #include <tsec.h>
  23. #include <asm/fsl_law.h>
  24. #include <netdev.h>
  25. #include <i2c.h>
  26. #include <hwconfig.h>
  27. #include "../common/ngpixis.h"
  28. int board_early_init_f(void)
  29. {
  30. ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
  31. /* Set pmuxcr to allow both i2c1 and i2c2 */
  32. setbits_be32(&gur->pmuxcr, 0x1000);
  33. #ifdef CONFIG_SYS_RAMBOOT
  34. setbits_be32(&gur->pmuxcr,
  35. in_be32(&gur->pmuxcr) | MPC85xx_PMUXCR_SD_DATA);
  36. #endif
  37. /* Read back the register to synchronize the write. */
  38. in_be32(&gur->pmuxcr);
  39. /* Set the pin muxing to enable ETSEC2. */
  40. clrbits_be32(&gur->pmuxcr2, 0x001F8000);
  41. /* Enable the SPI */
  42. clrsetbits_8(&pixis->brdcfg0, PIXIS_ELBC_SPI_MASK, PIXIS_SPI);
  43. return 0;
  44. }
  45. int checkboard(void)
  46. {
  47. u8 sw;
  48. printf("Board: P1022DS Sys ID: 0x%02x, "
  49. "Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ",
  50. in_8(&pixis->id), in_8(&pixis->arch), in_8(&pixis->scver));
  51. sw = in_8(&PIXIS_SW(PIXIS_LBMAP_SWITCH));
  52. switch ((sw & PIXIS_LBMAP_MASK) >> 6) {
  53. case 0:
  54. printf ("vBank: %u\n", ((sw & 0x30) >> 4));
  55. break;
  56. case 1:
  57. printf ("NAND\n");
  58. break;
  59. case 2:
  60. case 3:
  61. puts ("Promjet\n");
  62. break;
  63. }
  64. return 0;
  65. }
  66. #define CONFIG_TFP410_I2C_ADDR 0x38
  67. /* Masks for the SSI_TDM and AUDCLK bits of the ngPIXIS BRDCFG1 register. */
  68. #define CONFIG_PIXIS_BRDCFG1_SSI_TDM_MASK 0x0c
  69. #define CONFIG_PIXIS_BRDCFG1_AUDCLK_MASK 0x03
  70. /* Route the I2C1 pins to the SSI port instead. */
  71. #define CONFIG_PIXIS_BRDCFG1_SSI_TDM_SSI 0x08
  72. /* Choose the 12.288Mhz codec reference clock */
  73. #define CONFIG_PIXIS_BRDCFG1_AUDCLK_12 0x02
  74. /* Choose the 11.2896Mhz codec reference clock */
  75. #define CONFIG_PIXIS_BRDCFG1_AUDCLK_11 0x01
  76. /* Connect to USB2 */
  77. #define CONFIG_PIXIS_BRDCFG0_USB2 0x10
  78. /* Connect to TFM bus */
  79. #define CONFIG_PIXIS_BRDCFG1_TDM 0x0c
  80. /* Connect to SPI */
  81. #define CONFIG_PIXIS_BRDCFG0_SPI 0x80
  82. int misc_init_r(void)
  83. {
  84. u8 temp;
  85. const char *audclk;
  86. size_t arglen;
  87. ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  88. /* For DVI, enable the TFP410 Encoder. */
  89. temp = 0xBF;
  90. if (i2c_write(CONFIG_TFP410_I2C_ADDR, 0x08, 1, &temp, sizeof(temp)) < 0)
  91. return -1;
  92. if (i2c_read(CONFIG_TFP410_I2C_ADDR, 0x08, 1, &temp, sizeof(temp)) < 0)
  93. return -1;
  94. debug("DVI Encoder Read: 0x%02x\n", temp);
  95. temp = 0x10;
  96. if (i2c_write(CONFIG_TFP410_I2C_ADDR, 0x0A, 1, &temp, sizeof(temp)) < 0)
  97. return -1;
  98. if (i2c_read(CONFIG_TFP410_I2C_ADDR, 0x0A, 1, &temp, sizeof(temp)) < 0)
  99. return -1;
  100. debug("DVI Encoder Read: 0x%02x\n",temp);
  101. /* Enable the USB2 in PMUXCR2 and FGPA */
  102. if (hwconfig("usb2")) {
  103. clrsetbits_be32(&gur->pmuxcr2, MPC85xx_PMUXCR2_ETSECUSB_MASK,
  104. MPC85xx_PMUXCR2_USB);
  105. setbits_8(&pixis->brdcfg0, CONFIG_PIXIS_BRDCFG0_USB2);
  106. }
  107. /* tdm and audio can not enable simultaneous*/
  108. if (hwconfig("tdm") && hwconfig("audclk")){
  109. printf("WARNING: TDM and AUDIO can not be enabled simultaneous !\n");
  110. return -1;
  111. }
  112. /* Enable the TDM in PMUXCR and FGPA */
  113. if (hwconfig("tdm")) {
  114. clrsetbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_TDM_MASK,
  115. MPC85xx_PMUXCR_TDM);
  116. setbits_8(&pixis->brdcfg1, CONFIG_PIXIS_BRDCFG1_TDM);
  117. /* TDM need some configration option by SPI */
  118. clrsetbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_SPI_MASK,
  119. MPC85xx_PMUXCR_SPI);
  120. setbits_8(&pixis->brdcfg0, CONFIG_PIXIS_BRDCFG0_SPI);
  121. }
  122. /*
  123. * Enable the reference clock for the WM8776 codec, and route the MUX
  124. * pins for SSI. The default is the 12.288 MHz clock
  125. */
  126. if (hwconfig("audclk")) {
  127. temp = in_8(&pixis->brdcfg1) & ~(CONFIG_PIXIS_BRDCFG1_SSI_TDM_MASK |
  128. CONFIG_PIXIS_BRDCFG1_AUDCLK_MASK);
  129. temp |= CONFIG_PIXIS_BRDCFG1_SSI_TDM_SSI;
  130. audclk = hwconfig_arg("audclk", &arglen);
  131. /* Check the first two chars only */
  132. if (audclk && (strncmp(audclk, "11", 2) == 0))
  133. temp |= CONFIG_PIXIS_BRDCFG1_AUDCLK_11;
  134. else
  135. temp |= CONFIG_PIXIS_BRDCFG1_AUDCLK_12;
  136. setbits_8(&pixis->brdcfg1, temp);
  137. }
  138. return 0;
  139. }
  140. /*
  141. * A list of PCI and SATA slots
  142. */
  143. enum slot_id {
  144. SLOT_PCIE1 = 1,
  145. SLOT_PCIE2,
  146. SLOT_PCIE3,
  147. SLOT_PCIE4,
  148. SLOT_PCIE5,
  149. SLOT_SATA1,
  150. SLOT_SATA2
  151. };
  152. /*
  153. * This array maps the slot identifiers to their names on the P1022DS board.
  154. */
  155. static const char *slot_names[] = {
  156. [SLOT_PCIE1] = "Slot 1",
  157. [SLOT_PCIE2] = "Slot 2",
  158. [SLOT_PCIE3] = "Slot 3",
  159. [SLOT_PCIE4] = "Slot 4",
  160. [SLOT_PCIE5] = "Mini-PCIe",
  161. [SLOT_SATA1] = "SATA 1",
  162. [SLOT_SATA2] = "SATA 2",
  163. };
  164. /*
  165. * This array maps a given SERDES configuration and SERDES device to the PCI or
  166. * SATA slot that it connects to. This mapping is hard-coded in the FPGA.
  167. */
  168. static u8 serdes_dev_slot[][SATA2 + 1] = {
  169. [0x01] = { [PCIE3] = SLOT_PCIE4, [PCIE2] = SLOT_PCIE5 },
  170. [0x02] = { [SATA1] = SLOT_SATA1, [SATA2] = SLOT_SATA2 },
  171. [0x09] = { [PCIE1] = SLOT_PCIE1, [PCIE3] = SLOT_PCIE4,
  172. [PCIE2] = SLOT_PCIE5 },
  173. [0x16] = { [PCIE1] = SLOT_PCIE1, [PCIE3] = SLOT_PCIE2,
  174. [PCIE2] = SLOT_PCIE3,
  175. [SATA1] = SLOT_SATA1, [SATA2] = SLOT_SATA2 },
  176. [0x17] = { [PCIE1] = SLOT_PCIE1, [PCIE3] = SLOT_PCIE2,
  177. [PCIE2] = SLOT_PCIE3 },
  178. [0x1a] = { [PCIE1] = SLOT_PCIE1, [PCIE2] = SLOT_PCIE3,
  179. [PCIE2] = SLOT_PCIE3,
  180. [SATA1] = SLOT_SATA1, [SATA2] = SLOT_SATA2 },
  181. [0x1c] = { [PCIE1] = SLOT_PCIE1,
  182. [SATA1] = SLOT_SATA1, [SATA2] = SLOT_SATA2 },
  183. [0x1e] = { [PCIE1] = SLOT_PCIE1, [PCIE3] = SLOT_PCIE3 },
  184. [0x1f] = { [PCIE1] = SLOT_PCIE1 },
  185. };
  186. /*
  187. * Returns the name of the slot to which the PCIe or SATA controller is
  188. * connected
  189. */
  190. const char *board_serdes_name(enum srds_prtcl device)
  191. {
  192. ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
  193. u32 pordevsr = in_be32(&gur->pordevsr);
  194. unsigned int srds_cfg = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >>
  195. MPC85xx_PORDEVSR_IO_SEL_SHIFT;
  196. enum slot_id slot = serdes_dev_slot[srds_cfg][device];
  197. const char *name = slot_names[slot];
  198. if (name)
  199. return name;
  200. else
  201. return "Nothing";
  202. }
  203. #ifdef CONFIG_PCI
  204. void pci_init_board(void)
  205. {
  206. fsl_pcie_init_board(0);
  207. }
  208. #endif
  209. int board_early_init_r(void)
  210. {
  211. const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
  212. int flash_esel = find_tlb_idx((void *)flashbase, 1);
  213. /*
  214. * Remap Boot flash + PROMJET region to caching-inhibited
  215. * so that flash can be erased properly.
  216. */
  217. /* Flush d-cache and invalidate i-cache of any FLASH data */
  218. flush_dcache();
  219. invalidate_icache();
  220. if (flash_esel == -1) {
  221. /* very unlikely unless something is messed up */
  222. puts("Error: Could not find TLB for FLASH BASE\n");
  223. flash_esel = 2; /* give our best effort to continue */
  224. } else {
  225. /* invalidate existing TLB entry for flash + promjet */
  226. disable_tlb(flash_esel);
  227. }
  228. set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
  229. MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  230. 0, flash_esel, BOOKE_PAGESZ_256M, 1);
  231. return 0;
  232. }
  233. /*
  234. * Initialize on-board and/or PCI Ethernet devices
  235. *
  236. * Returns:
  237. * <0, error
  238. * 0, no ethernet devices found
  239. * >0, number of ethernet devices initialized
  240. */
  241. int board_eth_init(bd_t *bis)
  242. {
  243. struct fsl_pq_mdio_info mdio_info;
  244. struct tsec_info_struct tsec_info[2];
  245. unsigned int num = 0;
  246. #ifdef CONFIG_TSEC1
  247. SET_STD_TSEC_INFO(tsec_info[num], 1);
  248. num++;
  249. #endif
  250. #ifdef CONFIG_TSEC2
  251. SET_STD_TSEC_INFO(tsec_info[num], 2);
  252. num++;
  253. #endif
  254. mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR;
  255. mdio_info.name = DEFAULT_MII_NAME;
  256. fsl_pq_mdio_init(bis, &mdio_info);
  257. return tsec_eth_init(bis, tsec_info, num) + pci_eth_init(bis);
  258. }
  259. #ifdef CONFIG_OF_BOARD_SETUP
  260. /**
  261. * ft_codec_setup - fix up the clock-frequency property of the codec node
  262. *
  263. * Update the clock-frequency property based on the value of the 'audclk'
  264. * hwconfig option. If audclk is not specified, then don't write anything
  265. * to the device tree, because it means that the codec clock is disabled.
  266. */
  267. static void ft_codec_setup(void *blob, const char *compatible)
  268. {
  269. const char *audclk;
  270. size_t arglen;
  271. u32 freq;
  272. audclk = hwconfig_arg("audclk", &arglen);
  273. if (audclk) {
  274. if (strncmp(audclk, "11", 2) == 0)
  275. freq = 11289600;
  276. else
  277. freq = 12288000;
  278. do_fixup_by_compat_u32(blob, compatible, "clock-frequency",
  279. freq, 1);
  280. }
  281. }
  282. int ft_board_setup(void *blob, bd_t *bd)
  283. {
  284. phys_addr_t base;
  285. phys_size_t size;
  286. ft_cpu_setup(blob, bd);
  287. base = env_get_bootm_low();
  288. size = env_get_bootm_size();
  289. fdt_fixup_memory(blob, (u64)base, (u64)size);
  290. #ifdef CONFIG_HAS_FSL_DR_USB
  291. fsl_fdt_fixup_dr_usb(blob, bd);
  292. #endif
  293. FT_FSL_PCI_SETUP;
  294. #ifdef CONFIG_FSL_SGMII_RISER
  295. fsl_sgmii_riser_fdt_fixup(blob);
  296. #endif
  297. /* Update the WM8776 node's clock frequency property */
  298. ft_codec_setup(blob, "wlf,wm8776");
  299. return 0;
  300. }
  301. #endif