ot1200_spl.c 4.5 KB

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  1. /*
  2. * Copyright (C) 2015, Bachmann electronic GmbH
  3. *
  4. * SPDX-License-Identifier: GPL-2.0+
  5. */
  6. #include <common.h>
  7. #include <spl.h>
  8. #include <asm/arch/mx6-ddr.h>
  9. /* Configure MX6Q/DUAL mmdc DDR io registers */
  10. static struct mx6dq_iomux_ddr_regs ot1200_ddr_ioregs = {
  11. /* SDCLK[0:1], CAS, RAS, Reset: Differential input, 48ohm */
  12. .dram_sdclk_0 = 0x00000028,
  13. .dram_sdclk_1 = 0x00000028,
  14. .dram_cas = 0x00000028,
  15. .dram_ras = 0x00000028,
  16. .dram_reset = 0x00000028,
  17. /* SDCKE[0:1]: 100k pull-up */
  18. .dram_sdcke0 = 0x00003000,
  19. .dram_sdcke1 = 0x00003000,
  20. /* SDBA2: pull-up disabled */
  21. .dram_sdba2 = 0x00000000,
  22. /* SDODT[0:1]: 100k pull-up, 48 ohm */
  23. .dram_sdodt0 = 0x00000028,
  24. .dram_sdodt1 = 0x00000028,
  25. /* SDQS[0:7]: Differential input, 48 ohm */
  26. .dram_sdqs0 = 0x00000028,
  27. .dram_sdqs1 = 0x00000028,
  28. .dram_sdqs2 = 0x00000028,
  29. .dram_sdqs3 = 0x00000028,
  30. .dram_sdqs4 = 0x00000028,
  31. .dram_sdqs5 = 0x00000028,
  32. .dram_sdqs6 = 0x00000028,
  33. .dram_sdqs7 = 0x00000028,
  34. /* DQM[0:7]: Differential input, 48 ohm */
  35. .dram_dqm0 = 0x00000028,
  36. .dram_dqm1 = 0x00000028,
  37. .dram_dqm2 = 0x00000028,
  38. .dram_dqm3 = 0x00000028,
  39. .dram_dqm4 = 0x00000028,
  40. .dram_dqm5 = 0x00000028,
  41. .dram_dqm6 = 0x00000028,
  42. .dram_dqm7 = 0x00000028,
  43. };
  44. /* Configure MX6Q/DUAL mmdc GRP io registers */
  45. static struct mx6dq_iomux_grp_regs ot1200_grp_ioregs = {
  46. /* DDR3 */
  47. .grp_ddr_type = 0x000c0000,
  48. .grp_ddrmode_ctl = 0x00020000,
  49. /* Disable DDR pullups */
  50. .grp_ddrpke = 0x00000000,
  51. /* ADDR[00:16], SDBA[0:1]: 48 ohm */
  52. .grp_addds = 0x00000028,
  53. /* CS0/CS1/SDBA2/CKE0/CKE1/SDWE: 48 ohm */
  54. .grp_ctlds = 0x00000028,
  55. /* DATA[00:63]: Differential input, 48 ohm */
  56. .grp_ddrmode = 0x00020000,
  57. .grp_b0ds = 0x00000028,
  58. .grp_b1ds = 0x00000028,
  59. .grp_b2ds = 0x00000028,
  60. .grp_b3ds = 0x00000028,
  61. .grp_b4ds = 0x00000028,
  62. .grp_b5ds = 0x00000028,
  63. .grp_b6ds = 0x00000028,
  64. .grp_b7ds = 0x00000028,
  65. };
  66. static struct mx6_ddr_sysinfo ot1200_ddr_sysinfo = {
  67. /* Width of data bus: 0=16, 1=32, 2=64 */
  68. .dsize = 2,
  69. /* config for full 4GB range so that get_mem_size() works */
  70. .cs_density = 32, /* 32Gb per CS */
  71. /* Single chip select */
  72. .ncs = 1,
  73. .cs1_mirror = 0, /* war 0 */
  74. .rtt_wr = 1, /* DDR3_RTT_60_OHM - RTT_Wr = RZQ/4 */
  75. .rtt_nom = 1, /* DDR3_RTT_60_OHM - RTT_Nom = RZQ/4 */
  76. .walat = 1, /* Write additional latency */
  77. .ralat = 5, /* Read additional latency */
  78. .mif3_mode = 3, /* Command prediction working mode */
  79. .bi_on = 1, /* Bank interleaving enabled */ /* war 1 */
  80. .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */
  81. .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */
  82. .refsel = 1, /* Refresh cycles at 32KHz */
  83. .refr = 7, /* 8 refresh commands per refresh cycle */
  84. };
  85. /* MT41K128M16JT-125 */
  86. static struct mx6_ddr3_cfg micron_2gib_1600 = {
  87. .mem_speed = 1600,
  88. .density = 2,
  89. .width = 16,
  90. .banks = 8,
  91. .rowaddr = 14,
  92. .coladdr = 10,
  93. .pagesz = 2,
  94. .trcd = 1375,
  95. .trcmin = 4875,
  96. .trasmin = 3500,
  97. .SRT = 1,
  98. };
  99. static struct mx6_mmdc_calibration micron_2gib_1600_mmdc_calib = {
  100. /* write leveling calibration determine */
  101. .p0_mpwldectrl0 = 0x00260025,
  102. .p0_mpwldectrl1 = 0x00270021,
  103. .p1_mpwldectrl0 = 0x00180034,
  104. .p1_mpwldectrl1 = 0x00180024,
  105. /* Read DQS Gating calibration */
  106. .p0_mpdgctrl0 = 0x04380344,
  107. .p0_mpdgctrl1 = 0x0330032C,
  108. .p1_mpdgctrl0 = 0x0338033C,
  109. .p1_mpdgctrl1 = 0x032C0300,
  110. /* Read Calibration: DQS delay relative to DQ read access */
  111. .p0_mprddlctl = 0x3C2E3238,
  112. .p1_mprddlctl = 0x3A2E303C,
  113. /* Write Calibration: DQ/DM delay relative to DQS write access */
  114. .p0_mpwrdlctl = 0x36384036,
  115. .p1_mpwrdlctl = 0x442E4438,
  116. };
  117. static void ot1200_spl_dram_init(void)
  118. {
  119. mx6dq_dram_iocfg(64, &ot1200_ddr_ioregs, &ot1200_grp_ioregs);
  120. mx6_dram_cfg(&ot1200_ddr_sysinfo, &micron_2gib_1600_mmdc_calib,
  121. &micron_2gib_1600);
  122. }
  123. /*
  124. * called from C runtime startup code (arch/arm/lib/crt0.S:_main)
  125. * - we have a stack and a place to store GD, both in SRAM
  126. * - no variable global data is available
  127. */
  128. void board_init_f(ulong dummy)
  129. {
  130. /* setup AIPS and disable watchdog */
  131. arch_cpu_init();
  132. /* iomux and setup of i2c */
  133. board_early_init_f();
  134. /* setup GP timer */
  135. timer_init();
  136. /* UART clocks enabled and gd valid - init serial console */
  137. preloader_console_init();
  138. /* configure MMDC for SDRAM width/size and per-model calibration */
  139. ot1200_spl_dram_init();
  140. }