board.c 9.6 KB

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  1. /*
  2. * (C) Copyright 2012 Henrik Nordstrom <henrik@henriknordstrom.net>
  3. *
  4. * (C) Copyright 2007-2011
  5. * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
  6. * Tom Cubie <tangliang@allwinnertech.com>
  7. *
  8. * Some init for sunxi platform.
  9. *
  10. * SPDX-License-Identifier: GPL-2.0+
  11. */
  12. #include <common.h>
  13. #include <mmc.h>
  14. #include <i2c.h>
  15. #include <serial.h>
  16. #include <spl.h>
  17. #include <asm/gpio.h>
  18. #include <asm/io.h>
  19. #include <asm/arch/clock.h>
  20. #include <asm/arch/gpio.h>
  21. #include <asm/arch/spl.h>
  22. #include <asm/arch/sys_proto.h>
  23. #include <asm/arch/timer.h>
  24. #include <asm/arch/tzpc.h>
  25. #include <asm/arch/mmc.h>
  26. #include <linux/compiler.h>
  27. struct fel_stash {
  28. uint32_t sp;
  29. uint32_t lr;
  30. uint32_t cpsr;
  31. uint32_t sctlr;
  32. uint32_t vbar;
  33. uint32_t cr;
  34. };
  35. struct fel_stash fel_stash __attribute__((section(".data")));
  36. #ifdef CONFIG_ARM64
  37. #include <asm/armv8/mmu.h>
  38. static struct mm_region sunxi_mem_map[] = {
  39. {
  40. /* SRAM, MMIO regions */
  41. .virt = 0x0UL,
  42. .phys = 0x0UL,
  43. .size = 0x40000000UL,
  44. .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
  45. PTE_BLOCK_NON_SHARE
  46. }, {
  47. /* RAM */
  48. .virt = 0x40000000UL,
  49. .phys = 0x40000000UL,
  50. .size = 0x80000000UL,
  51. .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
  52. PTE_BLOCK_INNER_SHARE
  53. }, {
  54. /* List terminator */
  55. 0,
  56. }
  57. };
  58. struct mm_region *mem_map = sunxi_mem_map;
  59. #endif
  60. static int gpio_init(void)
  61. {
  62. #if CONFIG_CONS_INDEX == 1 && defined(CONFIG_UART0_PORT_F)
  63. #if defined(CONFIG_MACH_SUN4I) || \
  64. defined(CONFIG_MACH_SUN7I) || \
  65. defined(CONFIG_MACH_SUN8I_R40)
  66. /* disable GPB22,23 as uart0 tx,rx to avoid conflict */
  67. sunxi_gpio_set_cfgpin(SUNXI_GPB(22), SUNXI_GPIO_INPUT);
  68. sunxi_gpio_set_cfgpin(SUNXI_GPB(23), SUNXI_GPIO_INPUT);
  69. #endif
  70. #if defined(CONFIG_MACH_SUN8I) && !defined(CONFIG_MACH_SUN8I_R40)
  71. sunxi_gpio_set_cfgpin(SUNXI_GPF(2), SUN8I_GPF_UART0);
  72. sunxi_gpio_set_cfgpin(SUNXI_GPF(4), SUN8I_GPF_UART0);
  73. #else
  74. sunxi_gpio_set_cfgpin(SUNXI_GPF(2), SUNXI_GPF_UART0);
  75. sunxi_gpio_set_cfgpin(SUNXI_GPF(4), SUNXI_GPF_UART0);
  76. #endif
  77. sunxi_gpio_set_pull(SUNXI_GPF(4), 1);
  78. #elif CONFIG_CONS_INDEX == 1 && (defined(CONFIG_MACH_SUN4I) || \
  79. defined(CONFIG_MACH_SUN7I) || \
  80. defined(CONFIG_MACH_SUN8I_R40))
  81. sunxi_gpio_set_cfgpin(SUNXI_GPB(22), SUN4I_GPB_UART0);
  82. sunxi_gpio_set_cfgpin(SUNXI_GPB(23), SUN4I_GPB_UART0);
  83. sunxi_gpio_set_pull(SUNXI_GPB(23), SUNXI_GPIO_PULL_UP);
  84. #elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN5I)
  85. sunxi_gpio_set_cfgpin(SUNXI_GPB(19), SUN5I_GPB_UART0);
  86. sunxi_gpio_set_cfgpin(SUNXI_GPB(20), SUN5I_GPB_UART0);
  87. sunxi_gpio_set_pull(SUNXI_GPB(20), SUNXI_GPIO_PULL_UP);
  88. #elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN6I)
  89. sunxi_gpio_set_cfgpin(SUNXI_GPH(20), SUN6I_GPH_UART0);
  90. sunxi_gpio_set_cfgpin(SUNXI_GPH(21), SUN6I_GPH_UART0);
  91. sunxi_gpio_set_pull(SUNXI_GPH(21), SUNXI_GPIO_PULL_UP);
  92. #elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN8I_A33)
  93. sunxi_gpio_set_cfgpin(SUNXI_GPB(0), SUN8I_A33_GPB_UART0);
  94. sunxi_gpio_set_cfgpin(SUNXI_GPB(1), SUN8I_A33_GPB_UART0);
  95. sunxi_gpio_set_pull(SUNXI_GPB(1), SUNXI_GPIO_PULL_UP);
  96. #elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUNXI_H3_H5)
  97. sunxi_gpio_set_cfgpin(SUNXI_GPA(4), SUN8I_H3_GPA_UART0);
  98. sunxi_gpio_set_cfgpin(SUNXI_GPA(5), SUN8I_H3_GPA_UART0);
  99. sunxi_gpio_set_pull(SUNXI_GPA(5), SUNXI_GPIO_PULL_UP);
  100. #elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN50I)
  101. sunxi_gpio_set_cfgpin(SUNXI_GPB(8), SUN50I_GPB_UART0);
  102. sunxi_gpio_set_cfgpin(SUNXI_GPB(9), SUN50I_GPB_UART0);
  103. sunxi_gpio_set_pull(SUNXI_GPB(9), SUNXI_GPIO_PULL_UP);
  104. #elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN8I_A83T)
  105. sunxi_gpio_set_cfgpin(SUNXI_GPB(9), SUN8I_A83T_GPB_UART0);
  106. sunxi_gpio_set_cfgpin(SUNXI_GPB(10), SUN8I_A83T_GPB_UART0);
  107. sunxi_gpio_set_pull(SUNXI_GPB(10), SUNXI_GPIO_PULL_UP);
  108. #elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN8I_V3S)
  109. sunxi_gpio_set_cfgpin(SUNXI_GPB(8), SUN8I_V3S_GPB_UART0);
  110. sunxi_gpio_set_cfgpin(SUNXI_GPB(9), SUN8I_V3S_GPB_UART0);
  111. sunxi_gpio_set_pull(SUNXI_GPB(9), SUNXI_GPIO_PULL_UP);
  112. #elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN9I)
  113. sunxi_gpio_set_cfgpin(SUNXI_GPH(12), SUN9I_GPH_UART0);
  114. sunxi_gpio_set_cfgpin(SUNXI_GPH(13), SUN9I_GPH_UART0);
  115. sunxi_gpio_set_pull(SUNXI_GPH(13), SUNXI_GPIO_PULL_UP);
  116. #elif CONFIG_CONS_INDEX == 2 && defined(CONFIG_MACH_SUN5I)
  117. sunxi_gpio_set_cfgpin(SUNXI_GPG(3), SUN5I_GPG_UART1);
  118. sunxi_gpio_set_cfgpin(SUNXI_GPG(4), SUN5I_GPG_UART1);
  119. sunxi_gpio_set_pull(SUNXI_GPG(4), SUNXI_GPIO_PULL_UP);
  120. #elif CONFIG_CONS_INDEX == 3 && defined(CONFIG_MACH_SUN8I)
  121. sunxi_gpio_set_cfgpin(SUNXI_GPB(0), SUN8I_GPB_UART2);
  122. sunxi_gpio_set_cfgpin(SUNXI_GPB(1), SUN8I_GPB_UART2);
  123. sunxi_gpio_set_pull(SUNXI_GPB(1), SUNXI_GPIO_PULL_UP);
  124. #elif CONFIG_CONS_INDEX == 5 && defined(CONFIG_MACH_SUN8I)
  125. sunxi_gpio_set_cfgpin(SUNXI_GPL(2), SUN8I_GPL_R_UART);
  126. sunxi_gpio_set_cfgpin(SUNXI_GPL(3), SUN8I_GPL_R_UART);
  127. sunxi_gpio_set_pull(SUNXI_GPL(3), SUNXI_GPIO_PULL_UP);
  128. #else
  129. #error Unsupported console port number. Please fix pin mux settings in board.c
  130. #endif
  131. return 0;
  132. }
  133. #if defined(CONFIG_SPL_BOARD_LOAD_IMAGE) && defined(CONFIG_SPL_BUILD)
  134. static int spl_board_load_image(struct spl_image_info *spl_image,
  135. struct spl_boot_device *bootdev)
  136. {
  137. debug("Returning to FEL sp=%x, lr=%x\n", fel_stash.sp, fel_stash.lr);
  138. return_to_fel(fel_stash.sp, fel_stash.lr);
  139. return 0;
  140. }
  141. SPL_LOAD_IMAGE_METHOD("FEL", 0, BOOT_DEVICE_BOARD, spl_board_load_image);
  142. #endif
  143. void s_init(void)
  144. {
  145. /*
  146. * Undocumented magic taken from boot0, without this DRAM
  147. * access gets messed up (seems cache related).
  148. * The boot0 sources describe this as: "config ema for cache sram"
  149. */
  150. #if defined CONFIG_MACH_SUN6I
  151. setbits_le32(SUNXI_SRAMC_BASE + 0x44, 0x1800);
  152. #elif defined CONFIG_MACH_SUN8I
  153. __maybe_unused uint version;
  154. /* Unlock sram version info reg, read it, relock */
  155. setbits_le32(SUNXI_SRAMC_BASE + 0x24, (1 << 15));
  156. version = readl(SUNXI_SRAMC_BASE + 0x24) >> 16;
  157. clrbits_le32(SUNXI_SRAMC_BASE + 0x24, (1 << 15));
  158. /*
  159. * Ideally this would be a switch case, but we do not know exactly
  160. * which versions there are and which version needs which settings,
  161. * so reproduce the per SoC code from the BSP.
  162. */
  163. #if defined CONFIG_MACH_SUN8I_A23
  164. if (version == 0x1650)
  165. setbits_le32(SUNXI_SRAMC_BASE + 0x44, 0x1800);
  166. else /* 0x1661 ? */
  167. setbits_le32(SUNXI_SRAMC_BASE + 0x44, 0xc0);
  168. #elif defined CONFIG_MACH_SUN8I_A33
  169. if (version != 0x1667)
  170. setbits_le32(SUNXI_SRAMC_BASE + 0x44, 0xc0);
  171. #endif
  172. /* A83T BSP never modifies SUNXI_SRAMC_BASE + 0x44 */
  173. /* No H3 BSP, boot0 seems to not modify SUNXI_SRAMC_BASE + 0x44 */
  174. #endif
  175. #if !defined(CONFIG_ARM_CORTEX_CPU_IS_UP) && !defined(CONFIG_ARM64)
  176. /* Enable SMP mode for CPU0, by setting bit 6 of Auxiliary Ctl reg */
  177. asm volatile(
  178. "mrc p15, 0, r0, c1, c0, 1\n"
  179. "orr r0, r0, #1 << 6\n"
  180. "mcr p15, 0, r0, c1, c0, 1\n"
  181. ::: "r0");
  182. #endif
  183. #if defined CONFIG_MACH_SUN6I || defined CONFIG_MACH_SUN8I_H3
  184. /* Enable non-secure access to some peripherals */
  185. tzpc_init();
  186. #endif
  187. clock_init();
  188. timer_init();
  189. gpio_init();
  190. #ifndef CONFIG_DM_I2C
  191. i2c_init_board();
  192. #endif
  193. eth_init_board();
  194. }
  195. #ifdef CONFIG_SPL_BUILD
  196. #endif
  197. /* The sunxi internal brom will try to loader external bootloader
  198. * from mmc0, nand flash, mmc2.
  199. */
  200. uint32_t sunxi_get_boot_device(void)
  201. {
  202. int boot_source;
  203. /*
  204. * When booting from the SD card or NAND memory, the "eGON.BT0"
  205. * signature is expected to be found in memory at the address 0x0004
  206. * (see the "mksunxiboot" tool, which generates this header).
  207. *
  208. * When booting in the FEL mode over USB, this signature is patched in
  209. * memory and replaced with something else by the 'fel' tool. This other
  210. * signature is selected in such a way, that it can't be present in a
  211. * valid bootable SD card image (because the BROM would refuse to
  212. * execute the SPL in this case).
  213. *
  214. * This checks for the signature and if it is not found returns to
  215. * the FEL code in the BROM to wait and receive the main u-boot
  216. * binary over USB. If it is found, it determines where SPL was
  217. * read from.
  218. */
  219. if (!is_boot0_magic(SPL_ADDR + 4)) /* eGON.BT0 */
  220. return BOOT_DEVICE_BOARD;
  221. boot_source = readb(SPL_ADDR + 0x28);
  222. switch (boot_source) {
  223. case SUNXI_BOOTED_FROM_MMC0:
  224. return BOOT_DEVICE_MMC1;
  225. case SUNXI_BOOTED_FROM_NAND:
  226. return BOOT_DEVICE_NAND;
  227. case SUNXI_BOOTED_FROM_MMC2:
  228. return BOOT_DEVICE_MMC2;
  229. case SUNXI_BOOTED_FROM_SPI:
  230. return BOOT_DEVICE_SPI;
  231. }
  232. panic("Unknown boot source %d\n", boot_source);
  233. return -1; /* Never reached */
  234. }
  235. #ifdef CONFIG_SPL_BUILD
  236. u32 spl_boot_device(void)
  237. {
  238. return sunxi_get_boot_device();
  239. }
  240. void board_init_f(ulong dummy)
  241. {
  242. spl_init();
  243. preloader_console_init();
  244. #ifdef CONFIG_SPL_I2C_SUPPORT
  245. /* Needed early by sunxi_board_init if PMU is enabled */
  246. i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
  247. #endif
  248. sunxi_board_init();
  249. }
  250. #endif
  251. void reset_cpu(ulong addr)
  252. {
  253. #if defined(CONFIG_SUNXI_GEN_SUN4I) || defined(CONFIG_MACH_SUN8I_R40)
  254. static const struct sunxi_wdog *wdog =
  255. &((struct sunxi_timer_reg *)SUNXI_TIMER_BASE)->wdog;
  256. /* Set the watchdog for its shortest interval (.5s) and wait */
  257. writel(WDT_MODE_RESET_EN | WDT_MODE_EN, &wdog->mode);
  258. writel(WDT_CTRL_KEY | WDT_CTRL_RESTART, &wdog->ctl);
  259. while (1) {
  260. /* sun5i sometimes gets stuck without this */
  261. writel(WDT_MODE_RESET_EN | WDT_MODE_EN, &wdog->mode);
  262. }
  263. #elif defined(CONFIG_SUNXI_GEN_SUN6I)
  264. static const struct sunxi_wdog *wdog =
  265. ((struct sunxi_timer_reg *)SUNXI_TIMER_BASE)->wdog;
  266. /* Set the watchdog for its shortest interval (.5s) and wait */
  267. writel(WDT_CFG_RESET, &wdog->cfg);
  268. writel(WDT_MODE_EN, &wdog->mode);
  269. writel(WDT_CTRL_KEY | WDT_CTRL_RESTART, &wdog->ctl);
  270. while (1) { }
  271. #endif
  272. }
  273. #if !defined(CONFIG_SYS_DCACHE_OFF) && !defined(CONFIG_ARM64)
  274. void enable_caches(void)
  275. {
  276. /* Enable D-cache. I-cache is already enabled in start.S */
  277. dcache_enable();
  278. }
  279. #endif