freeze_controller.c 5.6 KB

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  1. /*
  2. * Copyright (C) 2013 Altera Corporation <www.altera.com>
  3. *
  4. * SPDX-License-Identifier: GPL-2.0+
  5. */
  6. #include <common.h>
  7. #include <asm/io.h>
  8. #include <asm/arch/clock_manager.h>
  9. #include <asm/arch/freeze_controller.h>
  10. #include <linux/errno.h>
  11. static const struct socfpga_freeze_controller *freeze_controller_base =
  12. (void *)(SOCFPGA_SYSMGR_ADDRESS + SYSMGR_FRZCTRL_ADDRESS);
  13. /*
  14. * Default state from cold reset is FREEZE_ALL; the global
  15. * flag is set to TRUE to indicate the IO banks are frozen
  16. */
  17. static uint32_t frzctrl_channel_freeze[FREEZE_CHANNEL_NUM]
  18. = { FREEZE_CTRL_FROZEN, FREEZE_CTRL_FROZEN,
  19. FREEZE_CTRL_FROZEN, FREEZE_CTRL_FROZEN};
  20. /* Freeze HPS IOs */
  21. void sys_mgr_frzctrl_freeze_req(void)
  22. {
  23. u32 ioctrl_reg_offset;
  24. u32 reg_value;
  25. u32 reg_cfg_mask;
  26. u32 channel_id;
  27. /* select software FSM */
  28. writel(SYSMGR_FRZCTRL_SRC_VIO1_ENUM_SW, &freeze_controller_base->src);
  29. /* Freeze channel 0 to 2 */
  30. for (channel_id = 0; channel_id <= 2; channel_id++) {
  31. ioctrl_reg_offset = (u32)(
  32. &freeze_controller_base->vioctrl + channel_id);
  33. /*
  34. * Assert active low enrnsl, plniotri
  35. * and niotri signals
  36. */
  37. reg_cfg_mask =
  38. SYSMGR_FRZCTRL_VIOCTRL_SLEW_MASK
  39. | SYSMGR_FRZCTRL_VIOCTRL_WKPULLUP_MASK
  40. | SYSMGR_FRZCTRL_VIOCTRL_TRISTATE_MASK;
  41. clrbits_le32(ioctrl_reg_offset, reg_cfg_mask);
  42. /*
  43. * Note: Delay for 20ns at min
  44. * Assert active low bhniotri signal and de-assert
  45. * active high csrdone
  46. */
  47. reg_cfg_mask
  48. = SYSMGR_FRZCTRL_VIOCTRL_BUSHOLD_MASK
  49. | SYSMGR_FRZCTRL_VIOCTRL_CFG_MASK;
  50. clrbits_le32(ioctrl_reg_offset, reg_cfg_mask);
  51. /* Set global flag to indicate channel is frozen */
  52. frzctrl_channel_freeze[channel_id] = FREEZE_CTRL_FROZEN;
  53. }
  54. /* Freeze channel 3 */
  55. /*
  56. * Assert active low enrnsl, plniotri and
  57. * niotri signals
  58. */
  59. reg_cfg_mask
  60. = SYSMGR_FRZCTRL_HIOCTRL_SLEW_MASK
  61. | SYSMGR_FRZCTRL_HIOCTRL_WKPULLUP_MASK
  62. | SYSMGR_FRZCTRL_HIOCTRL_TRISTATE_MASK;
  63. clrbits_le32(&freeze_controller_base->hioctrl, reg_cfg_mask);
  64. /*
  65. * assert active low bhniotri & nfrzdrv signals,
  66. * de-assert active high csrdone and assert
  67. * active high frzreg and nfrzdrv signals
  68. */
  69. reg_value = readl(&freeze_controller_base->hioctrl);
  70. reg_cfg_mask
  71. = SYSMGR_FRZCTRL_HIOCTRL_BUSHOLD_MASK
  72. | SYSMGR_FRZCTRL_HIOCTRL_CFG_MASK;
  73. reg_value
  74. = (reg_value & ~reg_cfg_mask)
  75. | SYSMGR_FRZCTRL_HIOCTRL_REGRST_MASK
  76. | SYSMGR_FRZCTRL_HIOCTRL_OCTRST_MASK;
  77. writel(reg_value, &freeze_controller_base->hioctrl);
  78. /*
  79. * assert active high reinit signal and de-assert
  80. * active high pllbiasen signals
  81. */
  82. reg_value = readl(&freeze_controller_base->hioctrl);
  83. reg_value
  84. = (reg_value &
  85. ~SYSMGR_FRZCTRL_HIOCTRL_OCT_CFGEN_CALSTART_MASK)
  86. | SYSMGR_FRZCTRL_HIOCTRL_DLLRST_MASK;
  87. writel(reg_value, &freeze_controller_base->hioctrl);
  88. /* Set global flag to indicate channel is frozen */
  89. frzctrl_channel_freeze[channel_id] = FREEZE_CTRL_FROZEN;
  90. }
  91. /* Unfreeze/Thaw HPS IOs */
  92. void sys_mgr_frzctrl_thaw_req(void)
  93. {
  94. u32 ioctrl_reg_offset;
  95. u32 reg_cfg_mask;
  96. u32 reg_value;
  97. u32 channel_id;
  98. unsigned long eosc1_freq;
  99. /* select software FSM */
  100. writel(SYSMGR_FRZCTRL_SRC_VIO1_ENUM_SW, &freeze_controller_base->src);
  101. /* Thaw channel 0 to 2 */
  102. for (channel_id = 0; channel_id <= 2; channel_id++) {
  103. ioctrl_reg_offset
  104. = (u32)(&freeze_controller_base->vioctrl + channel_id);
  105. /*
  106. * Assert active low bhniotri signal and
  107. * de-assert active high csrdone
  108. */
  109. reg_cfg_mask
  110. = SYSMGR_FRZCTRL_VIOCTRL_BUSHOLD_MASK
  111. | SYSMGR_FRZCTRL_VIOCTRL_CFG_MASK;
  112. setbits_le32(ioctrl_reg_offset, reg_cfg_mask);
  113. /*
  114. * Note: Delay for 20ns at min
  115. * de-assert active low plniotri and niotri signals
  116. */
  117. reg_cfg_mask
  118. = SYSMGR_FRZCTRL_VIOCTRL_WKPULLUP_MASK
  119. | SYSMGR_FRZCTRL_VIOCTRL_TRISTATE_MASK;
  120. setbits_le32(ioctrl_reg_offset, reg_cfg_mask);
  121. /*
  122. * Note: Delay for 20ns at min
  123. * de-assert active low enrnsl signal
  124. */
  125. setbits_le32(ioctrl_reg_offset,
  126. SYSMGR_FRZCTRL_VIOCTRL_SLEW_MASK);
  127. /* Set global flag to indicate channel is thawed */
  128. frzctrl_channel_freeze[channel_id] = FREEZE_CTRL_THAWED;
  129. }
  130. /* Thaw channel 3 */
  131. /* de-assert active high reinit signal */
  132. clrbits_le32(&freeze_controller_base->hioctrl,
  133. SYSMGR_FRZCTRL_HIOCTRL_DLLRST_MASK);
  134. /*
  135. * Note: Delay for 40ns at min
  136. * assert active high pllbiasen signals
  137. */
  138. setbits_le32(&freeze_controller_base->hioctrl,
  139. SYSMGR_FRZCTRL_HIOCTRL_OCT_CFGEN_CALSTART_MASK);
  140. /* Delay 1000 intosc cycles. The intosc is based on eosc1. */
  141. eosc1_freq = cm_get_osc_clk_hz(1) / 1000; /* kHz */
  142. udelay(DIV_ROUND_UP(1000000, eosc1_freq));
  143. /*
  144. * de-assert active low bhniotri signals,
  145. * assert active high csrdone and nfrzdrv signal
  146. */
  147. reg_value = readl(&freeze_controller_base->hioctrl);
  148. reg_value = (reg_value
  149. | SYSMGR_FRZCTRL_HIOCTRL_BUSHOLD_MASK
  150. | SYSMGR_FRZCTRL_HIOCTRL_CFG_MASK)
  151. & ~SYSMGR_FRZCTRL_HIOCTRL_OCTRST_MASK;
  152. writel(reg_value, &freeze_controller_base->hioctrl);
  153. /*
  154. * Delay 33 intosc
  155. * Use worst case which is fatest eosc1=50MHz, delay required
  156. * is 1/50MHz * 33 = 660ns ~= 1us
  157. */
  158. udelay(1);
  159. /* de-assert active low plniotri and niotri signals */
  160. reg_cfg_mask
  161. = SYSMGR_FRZCTRL_HIOCTRL_WKPULLUP_MASK
  162. | SYSMGR_FRZCTRL_HIOCTRL_TRISTATE_MASK;
  163. setbits_le32(&freeze_controller_base->hioctrl, reg_cfg_mask);
  164. /*
  165. * Note: Delay for 40ns at min
  166. * de-assert active high frzreg signal
  167. */
  168. clrbits_le32(&freeze_controller_base->hioctrl,
  169. SYSMGR_FRZCTRL_HIOCTRL_REGRST_MASK);
  170. /*
  171. * Note: Delay for 40ns at min
  172. * de-assert active low enrnsl signal
  173. */
  174. setbits_le32(&freeze_controller_base->hioctrl,
  175. SYSMGR_FRZCTRL_HIOCTRL_SLEW_MASK);
  176. /* Set global flag to indicate channel is thawed */
  177. frzctrl_channel_freeze[channel_id] = FREEZE_CTRL_THAWED;
  178. }