rk3399-board-spl.c 4.5 KB

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  1. /*
  2. * (C) Copyright 2016 Rockchip Electronics Co., Ltd
  3. * (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH
  4. *
  5. * SPDX-License-Identifier: GPL-2.0+
  6. */
  7. #include <common.h>
  8. #include <asm/arch/bootrom.h>
  9. #include <asm/arch/clock.h>
  10. #include <asm/arch/grf_rk3399.h>
  11. #include <asm/arch/hardware.h>
  12. #include <asm/arch/periph.h>
  13. #include <asm/io.h>
  14. #include <debug_uart.h>
  15. #include <dm.h>
  16. #include <dm/pinctrl.h>
  17. #include <ram.h>
  18. #include <spl.h>
  19. #include <syscon.h>
  20. void board_return_to_bootrom(void)
  21. {
  22. back_to_bootrom(BROM_BOOT_NEXTSTAGE);
  23. }
  24. static const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1] = {
  25. [BROM_BOOTSOURCE_EMMC] = "/sdhci@fe330000",
  26. [BROM_BOOTSOURCE_SPINOR] = "/spi@ff1d0000",
  27. [BROM_BOOTSOURCE_SD] = "/dwmmc@fe320000",
  28. };
  29. const char *board_spl_was_booted_from(void)
  30. {
  31. u32 bootdevice_brom_id = readl(RK3399_BROM_BOOTSOURCE_ID_ADDR);
  32. const char *bootdevice_ofpath = NULL;
  33. if (bootdevice_brom_id < ARRAY_SIZE(boot_devices))
  34. bootdevice_ofpath = boot_devices[bootdevice_brom_id];
  35. if (bootdevice_ofpath)
  36. debug("%s: brom_bootdevice_id %x maps to '%s'\n",
  37. __func__, bootdevice_brom_id, bootdevice_ofpath);
  38. else
  39. debug("%s: failed to resolve brom_bootdevice_id %x\n",
  40. __func__, bootdevice_brom_id);
  41. return bootdevice_ofpath;
  42. }
  43. u32 spl_boot_device(void)
  44. {
  45. u32 boot_device = BOOT_DEVICE_MMC1;
  46. if (CONFIG_IS_ENABLED(ROCKCHIP_BACK_TO_BROM))
  47. return BOOT_DEVICE_BOOTROM;
  48. return boot_device;
  49. }
  50. #define TIMER_CHN10_BASE 0xff8680a0
  51. #define TIMER_END_COUNT_L 0x00
  52. #define TIMER_END_COUNT_H 0x04
  53. #define TIMER_INIT_COUNT_L 0x10
  54. #define TIMER_INIT_COUNT_H 0x14
  55. #define TIMER_CONTROL_REG 0x1c
  56. #define TIMER_EN 0x1
  57. #define TIMER_FMODE (0 << 1)
  58. #define TIMER_RMODE (1 << 1)
  59. void secure_timer_init(void)
  60. {
  61. writel(0xffffffff, TIMER_CHN10_BASE + TIMER_END_COUNT_L);
  62. writel(0xffffffff, TIMER_CHN10_BASE + TIMER_END_COUNT_H);
  63. writel(0, TIMER_CHN10_BASE + TIMER_INIT_COUNT_L);
  64. writel(0, TIMER_CHN10_BASE + TIMER_INIT_COUNT_H);
  65. writel(TIMER_EN | TIMER_FMODE, TIMER_CHN10_BASE + TIMER_CONTROL_REG);
  66. }
  67. void board_debug_uart_init(void)
  68. {
  69. #define GRF_BASE 0xff770000
  70. struct rk3399_grf_regs * const grf = (void *)GRF_BASE;
  71. #if defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xff180000)
  72. /* Enable early UART0 on the RK3399 */
  73. rk_clrsetreg(&grf->gpio2c_iomux,
  74. GRF_GPIO2C0_SEL_MASK,
  75. GRF_UART0BT_SIN << GRF_GPIO2C0_SEL_SHIFT);
  76. rk_clrsetreg(&grf->gpio2c_iomux,
  77. GRF_GPIO2C1_SEL_MASK,
  78. GRF_UART0BT_SOUT << GRF_GPIO2C1_SEL_SHIFT);
  79. #else
  80. /* Enable early UART2 channel C on the RK3399 */
  81. rk_clrsetreg(&grf->gpio4c_iomux,
  82. GRF_GPIO4C3_SEL_MASK,
  83. GRF_UART2DGBC_SIN << GRF_GPIO4C3_SEL_SHIFT);
  84. rk_clrsetreg(&grf->gpio4c_iomux,
  85. GRF_GPIO4C4_SEL_MASK,
  86. GRF_UART2DBGC_SOUT << GRF_GPIO4C4_SEL_SHIFT);
  87. /* Set channel C as UART2 input */
  88. rk_clrsetreg(&grf->soc_con7,
  89. GRF_UART_DBG_SEL_MASK,
  90. GRF_UART_DBG_SEL_C << GRF_UART_DBG_SEL_SHIFT);
  91. #endif
  92. }
  93. void board_init_f(ulong dummy)
  94. {
  95. struct udevice *pinctrl;
  96. struct udevice *dev;
  97. struct rk3399_pmusgrf_regs *sgrf;
  98. struct rk3399_grf_regs *grf;
  99. int ret;
  100. #define EARLY_UART
  101. #ifdef EARLY_UART
  102. /*
  103. * Debug UART can be used from here if required:
  104. *
  105. * debug_uart_init();
  106. * printch('a');
  107. * printhex8(0x1234);
  108. * printascii("string");
  109. */
  110. debug_uart_init();
  111. printascii("U-Boot SPL board init");
  112. #endif
  113. ret = spl_early_init();
  114. if (ret) {
  115. debug("spl_early_init() failed: %d\n", ret);
  116. hang();
  117. }
  118. /*
  119. * Disable DDR and SRAM security regions.
  120. *
  121. * As we are entered from the BootROM, the region from
  122. * 0x0 through 0xfffff (i.e. the first MB of memory) will
  123. * be protected. This will cause issues with the DW_MMC
  124. * driver, which tries to DMA from/to the stack (likely)
  125. * located in this range.
  126. */
  127. sgrf = syscon_get_first_range(ROCKCHIP_SYSCON_PMUSGRF);
  128. rk_clrsetreg(&sgrf->ddr_rgn_con[16], 0x1ff, 0);
  129. rk_clrreg(&sgrf->slv_secure_con4, 0x2000);
  130. /* eMMC clock generator: disable the clock multipilier */
  131. grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
  132. rk_clrreg(&grf->emmccore_con[11], 0x0ff);
  133. secure_timer_init();
  134. ret = uclass_get_device(UCLASS_PINCTRL, 0, &pinctrl);
  135. if (ret) {
  136. debug("Pinctrl init failed: %d\n", ret);
  137. return;
  138. }
  139. ret = uclass_get_device(UCLASS_RAM, 0, &dev);
  140. if (ret) {
  141. debug("DRAM init failed: %d\n", ret);
  142. return;
  143. }
  144. }
  145. #ifdef CONFIG_SPL_LOAD_FIT
  146. int board_fit_config_name_match(const char *name)
  147. {
  148. /* Just empty function now - can't decide what to choose */
  149. debug("%s: %s\n", __func__, name);
  150. return 0;
  151. }
  152. #endif