rk322x-board-spl.c 2.2 KB

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  1. /*
  2. * (C) Copyright 2017 Rockchip Electronics Co., Ltd
  3. *
  4. * SPDX-License-Identifier: GPL-2.0+
  5. */
  6. #include <common.h>
  7. #include <debug_uart.h>
  8. #include <dm.h>
  9. #include <ram.h>
  10. #include <spl.h>
  11. #include <asm/io.h>
  12. #include <asm/arch/bootrom.h>
  13. #include <asm/arch/cru_rk322x.h>
  14. #include <asm/arch/grf_rk322x.h>
  15. #include <asm/arch/hardware.h>
  16. #include <asm/arch/timer.h>
  17. #include <asm/arch/uart.h>
  18. u32 spl_boot_device(void)
  19. {
  20. return BOOT_DEVICE_MMC1;
  21. }
  22. #define GRF_BASE 0x11000000
  23. #define SGRF_BASE 0x10140000
  24. #define DEBUG_UART_BASE 0x11030000
  25. void board_debug_uart_init(void)
  26. {
  27. static struct rk322x_grf * const grf = (void *)GRF_BASE;
  28. enum {
  29. GPIO1B2_SHIFT = 4,
  30. GPIO1B2_MASK = 3 << GPIO1B2_SHIFT,
  31. GPIO1B2_GPIO = 0,
  32. GPIO1B2_UART1_SIN,
  33. GPIO1B2_UART21_SIN,
  34. GPIO1B1_SHIFT = 2,
  35. GPIO1B1_MASK = 3 << GPIO1B1_SHIFT,
  36. GPIO1B1_GPIO = 0,
  37. GPIO1B1_UART1_SOUT,
  38. GPIO1B1_UART21_SOUT,
  39. };
  40. enum {
  41. CON_IOMUX_UART2SEL_SHIFT= 8,
  42. CON_IOMUX_UART2SEL_MASK = 1 << CON_IOMUX_UART2SEL_SHIFT,
  43. CON_IOMUX_UART2SEL_2 = 0,
  44. CON_IOMUX_UART2SEL_21,
  45. };
  46. /* Enable early UART2 channel 1 on the RK322x */
  47. rk_clrsetreg(&grf->gpio1b_iomux,
  48. GPIO1B1_MASK | GPIO1B2_MASK,
  49. GPIO1B2_UART21_SIN << GPIO1B2_SHIFT |
  50. GPIO1B1_UART21_SOUT << GPIO1B1_SHIFT);
  51. /* Set channel C as UART2 input */
  52. rk_clrsetreg(&grf->con_iomux,
  53. CON_IOMUX_UART2SEL_MASK,
  54. CON_IOMUX_UART2SEL_21 << CON_IOMUX_UART2SEL_SHIFT);
  55. }
  56. #define SGRF_DDR_CON0 0x10150000
  57. void board_init_f(ulong dummy)
  58. {
  59. struct udevice *dev;
  60. int ret;
  61. /*
  62. * Debug UART can be used from here if required:
  63. *
  64. * debug_uart_init();
  65. * printch('a');
  66. * printhex8(0x1234);
  67. * printascii("string");
  68. */
  69. debug_uart_init();
  70. printascii("SPL Init");
  71. ret = spl_early_init();
  72. if (ret) {
  73. debug("spl_early_init() failed: %d\n", ret);
  74. hang();
  75. }
  76. rockchip_timer_init();
  77. printf("timer init done\n");
  78. ret = uclass_get_device(UCLASS_RAM, 0, &dev);
  79. if (ret) {
  80. printf("DRAM init failed: %d\n", ret);
  81. return;
  82. }
  83. /* Disable the ddr secure region setting to make it non-secure */
  84. rk_clrreg(SGRF_DDR_CON0, 0x4000);
  85. #if defined(CONFIG_SPL_ROCKCHIP_BACK_TO_BROM) && !defined(CONFIG_SPL_BOARD_INIT)
  86. back_to_bootrom(BROM_BOOT_NEXTSTAGE);
  87. #endif
  88. }