cpu.c 3.2 KB

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  1. /*
  2. * Copyright (C) 2016 Stefan Roese <sr@denx.de>
  3. *
  4. * SPDX-License-Identifier: GPL-2.0+
  5. */
  6. #include <common.h>
  7. #include <dm.h>
  8. #include <fdtdec.h>
  9. #include <linux/libfdt.h>
  10. #include <asm/io.h>
  11. #include <asm/system.h>
  12. #include <asm/arch/cpu.h>
  13. #include <asm/arch/soc.h>
  14. #include <asm/armv8/mmu.h>
  15. /* Armada 7k/8k */
  16. #define MVEBU_RFU_BASE (MVEBU_REGISTER(0x6f0000))
  17. #define RFU_GLOBAL_SW_RST (MVEBU_RFU_BASE + 0x84)
  18. #define RFU_SW_RESET_OFFSET 0
  19. /*
  20. * The following table includes all memory regions for Armada 7k and
  21. * 8k SoCs. The Armada 7k is missing the CP110 slave regions here. Lets
  22. * define these regions at the beginning of the struct so that they
  23. * can be easier removed later dynamically if an Armada 7k device is detected.
  24. * For a detailed memory map, please see doc/mvebu/armada-8k-memory.txt
  25. */
  26. #define ARMADA_7K8K_COMMON_REGIONS_START 2
  27. static struct mm_region mvebu_mem_map[] = {
  28. /* Armada 80x0 memory regions include the CP1 (slave) units */
  29. {
  30. /* SRAM, MMIO regions - CP110 slave region */
  31. .phys = 0xf4000000UL,
  32. .virt = 0xf4000000UL,
  33. .size = 0x02000000UL, /* 32MiB internal registers */
  34. .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
  35. PTE_BLOCK_NON_SHARE
  36. },
  37. {
  38. /* PCI CP1 regions */
  39. .phys = 0xfa000000UL,
  40. .virt = 0xfa000000UL,
  41. .size = 0x04000000UL, /* 64MiB CP110 slave PCI space */
  42. .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
  43. PTE_BLOCK_NON_SHARE
  44. },
  45. /* Armada 80x0 and 70x0 common memory regions start here */
  46. {
  47. /* RAM */
  48. .phys = 0x0UL,
  49. .virt = 0x0UL,
  50. .size = 0x80000000UL,
  51. .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
  52. PTE_BLOCK_INNER_SHARE
  53. },
  54. {
  55. /* SRAM, MMIO regions - AP806 region */
  56. .phys = 0xf0000000UL,
  57. .virt = 0xf0000000UL,
  58. .size = 0x01000000UL, /* 16MiB internal registers */
  59. .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
  60. PTE_BLOCK_NON_SHARE
  61. },
  62. {
  63. /* SRAM, MMIO regions - CP110 master region */
  64. .phys = 0xf2000000UL,
  65. .virt = 0xf2000000UL,
  66. .size = 0x02000000UL, /* 32MiB internal registers */
  67. .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
  68. PTE_BLOCK_NON_SHARE
  69. },
  70. {
  71. /* PCI CP0 regions */
  72. .phys = 0xf6000000UL,
  73. .virt = 0xf6000000UL,
  74. .size = 0x04000000UL, /* 64MiB CP110 master PCI space */
  75. .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
  76. PTE_BLOCK_NON_SHARE
  77. },
  78. {
  79. 0,
  80. }
  81. };
  82. struct mm_region *mem_map = mvebu_mem_map;
  83. void enable_caches(void)
  84. {
  85. /*
  86. * Armada 7k is not equipped with the CP110 slave CP. In case this
  87. * code runs on an Armada 7k device, lets remove the CP110 slave
  88. * entries from the memory mapping by moving the start to the
  89. * common regions.
  90. */
  91. if (of_machine_is_compatible("marvell,armada7040"))
  92. mem_map = &mvebu_mem_map[ARMADA_7K8K_COMMON_REGIONS_START];
  93. icache_enable();
  94. dcache_enable();
  95. }
  96. void reset_cpu(ulong ignored)
  97. {
  98. u32 reg;
  99. reg = readl(RFU_GLOBAL_SW_RST);
  100. reg &= ~(1 << RFU_SW_RESET_OFFSET);
  101. writel(reg, RFU_GLOBAL_SW_RST);
  102. }
  103. /*
  104. * TODO - implement this functionality using platform
  105. * clock driver once it gets available
  106. * Return NAND clock in Hz
  107. */
  108. u32 mvebu_get_nand_clock(void)
  109. {
  110. unsigned long NAND_FLASH_CLK_CTRL = 0xF2440700UL;
  111. unsigned long NF_CLOCK_SEL_MASK = 0x1;
  112. u32 reg;
  113. reg = readl(NAND_FLASH_CLK_CTRL);
  114. if (reg & NF_CLOCK_SEL_MASK)
  115. return 400 * 1000000;
  116. else
  117. return 250 * 1000000;
  118. }