clock.c 21 KB

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  1. /*
  2. * Copyright 2017 NXP
  3. *
  4. * Peng Fan <peng.fan@nxp.com>
  5. *
  6. * SPDX-License-Identifier: GPL-2.0+
  7. */
  8. #include <common.h>
  9. #include <asm/arch/clock.h>
  10. #include <asm/arch/imx-regs.h>
  11. #include <asm/io.h>
  12. #include <asm/arch/sys_proto.h>
  13. #include <errno.h>
  14. #include <linux/iopoll.h>
  15. static struct anamix_pll *ana_pll = (struct anamix_pll *)ANATOP_BASE_ADDR;
  16. static u32 decode_frac_pll(enum clk_root_src frac_pll)
  17. {
  18. u32 pll_cfg0, pll_cfg1, pllout;
  19. u32 pll_refclk_sel, pll_refclk;
  20. u32 divr_val, divq_val, divf_val, divff, divfi;
  21. u32 pllout_div_shift, pllout_div_mask, pllout_div;
  22. switch (frac_pll) {
  23. case ARM_PLL_CLK:
  24. pll_cfg0 = readl(&ana_pll->arm_pll_cfg0);
  25. pll_cfg1 = readl(&ana_pll->arm_pll_cfg1);
  26. pllout_div_shift = HW_FRAC_ARM_PLL_DIV_SHIFT;
  27. pllout_div_mask = HW_FRAC_ARM_PLL_DIV_MASK;
  28. break;
  29. default:
  30. printf("Frac PLL %d not supporte\n", frac_pll);
  31. return 0;
  32. }
  33. pllout_div = readl(&ana_pll->frac_pllout_div_cfg);
  34. pllout_div = (pllout_div & pllout_div_mask) >> pllout_div_shift;
  35. /* Power down */
  36. if (pll_cfg0 & FRAC_PLL_PD_MASK)
  37. return 0;
  38. /* output not enabled */
  39. if ((pll_cfg0 & FRAC_PLL_CLKE_MASK) == 0)
  40. return 0;
  41. pll_refclk_sel = pll_cfg0 & FRAC_PLL_REFCLK_SEL_MASK;
  42. if (pll_refclk_sel == FRAC_PLL_REFCLK_SEL_OSC_25M)
  43. pll_refclk = 25000000u;
  44. else if (pll_refclk_sel == FRAC_PLL_REFCLK_SEL_OSC_27M)
  45. pll_refclk = 27000000u;
  46. else if (pll_refclk_sel == FRAC_PLL_REFCLK_SEL_HDMI_PHY_27M)
  47. pll_refclk = 27000000u;
  48. else
  49. pll_refclk = 0;
  50. if (pll_cfg0 & FRAC_PLL_BYPASS_MASK)
  51. return pll_refclk;
  52. divr_val = (pll_cfg0 & FRAC_PLL_REFCLK_DIV_VAL_MASK) >>
  53. FRAC_PLL_REFCLK_DIV_VAL_SHIFT;
  54. divq_val = pll_cfg0 & FRAC_PLL_OUTPUT_DIV_VAL_MASK;
  55. divff = (pll_cfg1 & FRAC_PLL_FRAC_DIV_CTL_MASK) >>
  56. FRAC_PLL_FRAC_DIV_CTL_SHIFT;
  57. divfi = pll_cfg1 & FRAC_PLL_INT_DIV_CTL_MASK;
  58. divf_val = 1 + divfi + divff / (1 << 24);
  59. pllout = pll_refclk / (divr_val + 1) * 8 * divf_val /
  60. ((divq_val + 1) * 2);
  61. return pllout / (pllout_div + 1);
  62. }
  63. static u32 decode_sscg_pll(enum clk_root_src sscg_pll)
  64. {
  65. u32 pll_cfg0, pll_cfg1, pll_cfg2;
  66. u32 pll_refclk_sel, pll_refclk;
  67. u32 divr1, divr2, divf1, divf2, divq, div;
  68. u32 sse;
  69. u32 pll_clke;
  70. u32 pllout_div_shift, pllout_div_mask, pllout_div;
  71. u32 pllout;
  72. switch (sscg_pll) {
  73. case SYSTEM_PLL1_800M_CLK:
  74. case SYSTEM_PLL1_400M_CLK:
  75. case SYSTEM_PLL1_266M_CLK:
  76. case SYSTEM_PLL1_200M_CLK:
  77. case SYSTEM_PLL1_160M_CLK:
  78. case SYSTEM_PLL1_133M_CLK:
  79. case SYSTEM_PLL1_100M_CLK:
  80. case SYSTEM_PLL1_80M_CLK:
  81. case SYSTEM_PLL1_40M_CLK:
  82. pll_cfg0 = readl(&ana_pll->sys_pll1_cfg0);
  83. pll_cfg1 = readl(&ana_pll->sys_pll1_cfg1);
  84. pll_cfg2 = readl(&ana_pll->sys_pll1_cfg2);
  85. pllout_div_shift = HW_SSCG_SYSTEM_PLL1_DIV_SHIFT;
  86. pllout_div_mask = HW_SSCG_SYSTEM_PLL1_DIV_MASK;
  87. break;
  88. case SYSTEM_PLL2_1000M_CLK:
  89. case SYSTEM_PLL2_500M_CLK:
  90. case SYSTEM_PLL2_333M_CLK:
  91. case SYSTEM_PLL2_250M_CLK:
  92. case SYSTEM_PLL2_200M_CLK:
  93. case SYSTEM_PLL2_166M_CLK:
  94. case SYSTEM_PLL2_125M_CLK:
  95. case SYSTEM_PLL2_100M_CLK:
  96. case SYSTEM_PLL2_50M_CLK:
  97. pll_cfg0 = readl(&ana_pll->sys_pll2_cfg0);
  98. pll_cfg1 = readl(&ana_pll->sys_pll2_cfg1);
  99. pll_cfg2 = readl(&ana_pll->sys_pll2_cfg2);
  100. pllout_div_shift = HW_SSCG_SYSTEM_PLL2_DIV_SHIFT;
  101. pllout_div_mask = HW_SSCG_SYSTEM_PLL2_DIV_MASK;
  102. break;
  103. case SYSTEM_PLL3_CLK:
  104. pll_cfg0 = readl(&ana_pll->sys_pll3_cfg0);
  105. pll_cfg1 = readl(&ana_pll->sys_pll3_cfg1);
  106. pll_cfg2 = readl(&ana_pll->sys_pll3_cfg2);
  107. pllout_div_shift = HW_SSCG_SYSTEM_PLL3_DIV_SHIFT;
  108. pllout_div_mask = HW_SSCG_SYSTEM_PLL3_DIV_MASK;
  109. break;
  110. case DRAM_PLL1_CLK:
  111. pll_cfg0 = readl(&ana_pll->dram_pll_cfg0);
  112. pll_cfg1 = readl(&ana_pll->dram_pll_cfg1);
  113. pll_cfg2 = readl(&ana_pll->dram_pll_cfg2);
  114. pllout_div_shift = HW_SSCG_DRAM_PLL_DIV_SHIFT;
  115. pllout_div_mask = HW_SSCG_DRAM_PLL_DIV_MASK;
  116. break;
  117. default:
  118. printf("sscg pll %d not supporte\n", sscg_pll);
  119. return 0;
  120. }
  121. switch (sscg_pll) {
  122. case DRAM_PLL1_CLK:
  123. pll_clke = SSCG_PLL_DRAM_PLL_CLKE_MASK;
  124. div = 1;
  125. break;
  126. case SYSTEM_PLL3_CLK:
  127. pll_clke = SSCG_PLL_PLL3_CLKE_MASK;
  128. div = 1;
  129. break;
  130. case SYSTEM_PLL2_1000M_CLK:
  131. case SYSTEM_PLL1_800M_CLK:
  132. pll_clke = SSCG_PLL_CLKE_MASK;
  133. div = 1;
  134. break;
  135. case SYSTEM_PLL2_500M_CLK:
  136. case SYSTEM_PLL1_400M_CLK:
  137. pll_clke = SSCG_PLL_DIV2_CLKE_MASK;
  138. div = 2;
  139. break;
  140. case SYSTEM_PLL2_333M_CLK:
  141. case SYSTEM_PLL1_266M_CLK:
  142. pll_clke = SSCG_PLL_DIV3_CLKE_MASK;
  143. div = 3;
  144. break;
  145. case SYSTEM_PLL2_250M_CLK:
  146. case SYSTEM_PLL1_200M_CLK:
  147. pll_clke = SSCG_PLL_DIV4_CLKE_MASK;
  148. div = 4;
  149. break;
  150. case SYSTEM_PLL2_200M_CLK:
  151. case SYSTEM_PLL1_160M_CLK:
  152. pll_clke = SSCG_PLL_DIV5_CLKE_MASK;
  153. div = 5;
  154. break;
  155. case SYSTEM_PLL2_166M_CLK:
  156. case SYSTEM_PLL1_133M_CLK:
  157. pll_clke = SSCG_PLL_DIV6_CLKE_MASK;
  158. div = 6;
  159. break;
  160. case SYSTEM_PLL2_125M_CLK:
  161. case SYSTEM_PLL1_100M_CLK:
  162. pll_clke = SSCG_PLL_DIV8_CLKE_MASK;
  163. div = 8;
  164. break;
  165. case SYSTEM_PLL2_100M_CLK:
  166. case SYSTEM_PLL1_80M_CLK:
  167. pll_clke = SSCG_PLL_DIV10_CLKE_MASK;
  168. div = 10;
  169. break;
  170. case SYSTEM_PLL2_50M_CLK:
  171. case SYSTEM_PLL1_40M_CLK:
  172. pll_clke = SSCG_PLL_DIV20_CLKE_MASK;
  173. div = 20;
  174. break;
  175. default:
  176. printf("sscg pll %d not supporte\n", sscg_pll);
  177. return 0;
  178. }
  179. /* Power down */
  180. if (pll_cfg0 & SSCG_PLL_PD_MASK)
  181. return 0;
  182. /* output not enabled */
  183. if ((pll_cfg0 & pll_clke) == 0)
  184. return 0;
  185. pllout_div = readl(&ana_pll->sscg_pllout_div_cfg);
  186. pllout_div = (pllout_div & pllout_div_mask) >> pllout_div_shift;
  187. pll_refclk_sel = pll_cfg0 & SSCG_PLL_REFCLK_SEL_MASK;
  188. if (pll_refclk_sel == SSCG_PLL_REFCLK_SEL_OSC_25M)
  189. pll_refclk = 25000000u;
  190. else if (pll_refclk_sel == SSCG_PLL_REFCLK_SEL_OSC_27M)
  191. pll_refclk = 27000000u;
  192. else if (pll_refclk_sel == SSCG_PLL_REFCLK_SEL_HDMI_PHY_27M)
  193. pll_refclk = 27000000u;
  194. else
  195. pll_refclk = 0;
  196. /* We assume bypass1/2 are the same value */
  197. if ((pll_cfg0 & SSCG_PLL_BYPASS1_MASK) ||
  198. (pll_cfg0 & SSCG_PLL_BYPASS2_MASK))
  199. return pll_refclk;
  200. divr1 = (pll_cfg2 & SSCG_PLL_REF_DIVR1_MASK) >>
  201. SSCG_PLL_REF_DIVR1_SHIFT;
  202. divr2 = (pll_cfg2 & SSCG_PLL_REF_DIVR2_MASK) >>
  203. SSCG_PLL_REF_DIVR2_SHIFT;
  204. divf1 = (pll_cfg2 & SSCG_PLL_FEEDBACK_DIV_F1_MASK) >>
  205. SSCG_PLL_FEEDBACK_DIV_F1_SHIFT;
  206. divf2 = (pll_cfg2 & SSCG_PLL_FEEDBACK_DIV_F2_MASK) >>
  207. SSCG_PLL_FEEDBACK_DIV_F2_SHIFT;
  208. divq = (pll_cfg2 & SSCG_PLL_OUTPUT_DIV_VAL_MASK) >>
  209. SSCG_PLL_OUTPUT_DIV_VAL_SHIFT;
  210. sse = pll_cfg1 & SSCG_PLL_SSE_MASK;
  211. if (sse)
  212. sse = 8;
  213. else
  214. sse = 2;
  215. pllout = pll_refclk / (divr1 + 1) * sse * (divf1 + 1) /
  216. (divr2 + 1) * (divf2 + 1) / (divq + 1);
  217. return pllout / (pllout_div + 1) / div;
  218. }
  219. static u32 get_root_src_clk(enum clk_root_src root_src)
  220. {
  221. switch (root_src) {
  222. case OSC_25M_CLK:
  223. return 25000000;
  224. case OSC_27M_CLK:
  225. return 25000000;
  226. case OSC_32K_CLK:
  227. return 32000;
  228. case ARM_PLL_CLK:
  229. return decode_frac_pll(root_src);
  230. case SYSTEM_PLL1_800M_CLK:
  231. case SYSTEM_PLL1_400M_CLK:
  232. case SYSTEM_PLL1_266M_CLK:
  233. case SYSTEM_PLL1_200M_CLK:
  234. case SYSTEM_PLL1_160M_CLK:
  235. case SYSTEM_PLL1_133M_CLK:
  236. case SYSTEM_PLL1_100M_CLK:
  237. case SYSTEM_PLL1_80M_CLK:
  238. case SYSTEM_PLL1_40M_CLK:
  239. case SYSTEM_PLL2_1000M_CLK:
  240. case SYSTEM_PLL2_500M_CLK:
  241. case SYSTEM_PLL2_333M_CLK:
  242. case SYSTEM_PLL2_250M_CLK:
  243. case SYSTEM_PLL2_200M_CLK:
  244. case SYSTEM_PLL2_166M_CLK:
  245. case SYSTEM_PLL2_125M_CLK:
  246. case SYSTEM_PLL2_100M_CLK:
  247. case SYSTEM_PLL2_50M_CLK:
  248. case SYSTEM_PLL3_CLK:
  249. return decode_sscg_pll(root_src);
  250. default:
  251. return 0;
  252. }
  253. return 0;
  254. }
  255. static u32 get_root_clk(enum clk_root_index clock_id)
  256. {
  257. enum clk_root_src root_src;
  258. u32 post_podf, pre_podf, root_src_clk;
  259. if (clock_root_enabled(clock_id) <= 0)
  260. return 0;
  261. if (clock_get_prediv(clock_id, &pre_podf) < 0)
  262. return 0;
  263. if (clock_get_postdiv(clock_id, &post_podf) < 0)
  264. return 0;
  265. if (clock_get_src(clock_id, &root_src) < 0)
  266. return 0;
  267. root_src_clk = get_root_src_clk(root_src);
  268. return root_src_clk / (post_podf + 1) / (pre_podf + 1);
  269. }
  270. #ifdef CONFIG_MXC_OCOTP
  271. void enable_ocotp_clk(unsigned char enable)
  272. {
  273. clock_enable(CCGR_OCOTP, !!enable);
  274. }
  275. #endif
  276. int enable_i2c_clk(unsigned char enable, unsigned int i2c_num)
  277. {
  278. /* 0 - 3 is valid i2c num */
  279. if (i2c_num > 3)
  280. return -EINVAL;
  281. clock_enable(CCGR_I2C1 + i2c_num, !!enable);
  282. return 0;
  283. }
  284. unsigned int mxc_get_clock(enum clk_root_index clk)
  285. {
  286. u32 val;
  287. if (clk >= CLK_ROOT_MAX)
  288. return 0;
  289. if (clk == MXC_ARM_CLK)
  290. return get_root_clk(ARM_A53_CLK_ROOT);
  291. if (clk == MXC_IPG_CLK) {
  292. clock_get_target_val(IPG_CLK_ROOT, &val);
  293. val = val & 0x3;
  294. return get_root_clk(AHB_CLK_ROOT) / (val + 1);
  295. }
  296. return get_root_clk(clk);
  297. }
  298. u32 imx_get_uartclk(void)
  299. {
  300. return mxc_get_clock(UART1_CLK_ROOT);
  301. }
  302. void mxs_set_lcdclk(u32 base_addr, u32 freq)
  303. {
  304. /*
  305. * LCDIF_PIXEL_CLK: select 800MHz root clock,
  306. * select pre divider 8, output is 100 MHz
  307. */
  308. clock_set_target_val(LCDIF_PIXEL_CLK_ROOT, CLK_ROOT_ON |
  309. CLK_ROOT_SOURCE_SEL(4) |
  310. CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV8));
  311. }
  312. void init_wdog_clk(void)
  313. {
  314. clock_enable(CCGR_WDOG1, 0);
  315. clock_enable(CCGR_WDOG2, 0);
  316. clock_enable(CCGR_WDOG3, 0);
  317. clock_set_target_val(WDOG_CLK_ROOT, CLK_ROOT_ON |
  318. CLK_ROOT_SOURCE_SEL(0));
  319. clock_set_target_val(WDOG_CLK_ROOT, CLK_ROOT_ON |
  320. CLK_ROOT_SOURCE_SEL(0));
  321. clock_set_target_val(WDOG_CLK_ROOT, CLK_ROOT_ON |
  322. CLK_ROOT_SOURCE_SEL(0));
  323. clock_enable(CCGR_WDOG1, 1);
  324. clock_enable(CCGR_WDOG2, 1);
  325. clock_enable(CCGR_WDOG3, 1);
  326. }
  327. void init_usb_clk(void)
  328. {
  329. if (!is_usb_boot()) {
  330. clock_enable(CCGR_USB_CTRL1, 0);
  331. clock_enable(CCGR_USB_CTRL2, 0);
  332. clock_enable(CCGR_USB_PHY1, 0);
  333. clock_enable(CCGR_USB_PHY2, 0);
  334. /* 500MHz */
  335. clock_set_target_val(USB_BUS_CLK_ROOT, CLK_ROOT_ON |
  336. CLK_ROOT_SOURCE_SEL(1));
  337. /* 100MHz */
  338. clock_set_target_val(USB_CORE_REF_CLK_ROOT, CLK_ROOT_ON |
  339. CLK_ROOT_SOURCE_SEL(1));
  340. /* 100MHz */
  341. clock_set_target_val(USB_PHY_REF_CLK_ROOT, CLK_ROOT_ON |
  342. CLK_ROOT_SOURCE_SEL(1));
  343. clock_enable(CCGR_USB_CTRL1, 1);
  344. clock_enable(CCGR_USB_CTRL2, 1);
  345. clock_enable(CCGR_USB_PHY1, 1);
  346. clock_enable(CCGR_USB_PHY2, 1);
  347. }
  348. }
  349. void init_uart_clk(u32 index)
  350. {
  351. /* Set uart clock root 25M OSC */
  352. switch (index) {
  353. case 0:
  354. clock_enable(CCGR_UART1, 0);
  355. clock_set_target_val(UART1_CLK_ROOT, CLK_ROOT_ON |
  356. CLK_ROOT_SOURCE_SEL(0));
  357. clock_enable(CCGR_UART1, 1);
  358. return;
  359. case 1:
  360. clock_enable(CCGR_UART2, 0);
  361. clock_set_target_val(UART2_CLK_ROOT, CLK_ROOT_ON |
  362. CLK_ROOT_SOURCE_SEL(0));
  363. clock_enable(CCGR_UART2, 1);
  364. return;
  365. case 2:
  366. clock_enable(CCGR_UART3, 0);
  367. clock_set_target_val(UART3_CLK_ROOT, CLK_ROOT_ON |
  368. CLK_ROOT_SOURCE_SEL(0));
  369. clock_enable(CCGR_UART3, 1);
  370. return;
  371. case 3:
  372. clock_enable(CCGR_UART4, 0);
  373. clock_set_target_val(UART4_CLK_ROOT, CLK_ROOT_ON |
  374. CLK_ROOT_SOURCE_SEL(0));
  375. clock_enable(CCGR_UART4, 1);
  376. return;
  377. default:
  378. printf("Invalid uart index\n");
  379. return;
  380. }
  381. }
  382. void init_clk_usdhc(u32 index)
  383. {
  384. /*
  385. * set usdhc clock root
  386. * sys pll1 400M
  387. */
  388. switch (index) {
  389. case 0:
  390. clock_enable(CCGR_USDHC1, 0);
  391. clock_set_target_val(USDHC1_CLK_ROOT, CLK_ROOT_ON |
  392. CLK_ROOT_SOURCE_SEL(1) |
  393. CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV2));
  394. clock_enable(CCGR_USDHC1, 1);
  395. return;
  396. case 1:
  397. clock_enable(CCGR_USDHC2, 0);
  398. clock_set_target_val(USDHC2_CLK_ROOT, CLK_ROOT_ON |
  399. CLK_ROOT_SOURCE_SEL(1) |
  400. CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV2));
  401. clock_enable(CCGR_USDHC2, 1);
  402. return;
  403. default:
  404. printf("Invalid usdhc index\n");
  405. return;
  406. }
  407. }
  408. int set_clk_qspi(void)
  409. {
  410. /*
  411. * set qspi root
  412. * sys pll1 100M
  413. */
  414. clock_enable(CCGR_QSPI, 0);
  415. clock_set_target_val(QSPI_CLK_ROOT, CLK_ROOT_ON |
  416. CLK_ROOT_SOURCE_SEL(7));
  417. clock_enable(CCGR_QSPI, 1);
  418. return 0;
  419. }
  420. #ifdef CONFIG_FEC_MXC
  421. int set_clk_enet(enum enet_freq type)
  422. {
  423. u32 target;
  424. u32 enet1_ref;
  425. switch (type) {
  426. case ENET_125MHZ:
  427. enet1_ref = ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_125M_CLK;
  428. break;
  429. case ENET_50MHZ:
  430. enet1_ref = ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_50M_CLK;
  431. break;
  432. case ENET_25MHZ:
  433. enet1_ref = ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_25M_CLK;
  434. break;
  435. default:
  436. return -EINVAL;
  437. }
  438. /* disable the clock first */
  439. clock_enable(CCGR_ENET1, 0);
  440. clock_enable(CCGR_SIM_ENET, 0);
  441. /* set enet axi clock 266Mhz */
  442. target = CLK_ROOT_ON | ENET_AXI_CLK_ROOT_FROM_SYS1_PLL_266M |
  443. CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
  444. CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1);
  445. clock_set_target_val(ENET_AXI_CLK_ROOT, target);
  446. target = CLK_ROOT_ON | enet1_ref |
  447. CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
  448. CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1);
  449. clock_set_target_val(ENET_REF_CLK_ROOT, target);
  450. target = CLK_ROOT_ON |
  451. ENET1_TIME_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK |
  452. CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
  453. CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV4);
  454. clock_set_target_val(ENET_TIMER_CLK_ROOT, target);
  455. /* enable clock */
  456. clock_enable(CCGR_SIM_ENET, 1);
  457. clock_enable(CCGR_ENET1, 1);
  458. return 0;
  459. }
  460. #endif
  461. u32 imx_get_fecclk(void)
  462. {
  463. return get_root_clk(ENET_AXI_CLK_ROOT);
  464. }
  465. #ifdef CONFIG_SPL_BUILD
  466. void dram_pll_init(void)
  467. {
  468. struct src *src = (struct src *)SRC_BASE_ADDR;
  469. void __iomem *pll_control_reg = &ana_pll->dram_pll_cfg0;
  470. u32 pwdn_mask = 0, pll_clke = 0, bypass1 = 0, bypass2 = 0;
  471. u32 val;
  472. int ret;
  473. setbits_le32(GPC_BASE_ADDR + 0xEC, BIT(7));
  474. setbits_le32(GPC_BASE_ADDR + 0xF8, BIT(5));
  475. pwdn_mask = SSCG_PLL_PD_MASK;
  476. pll_clke = SSCG_PLL_DRAM_PLL_CLKE_MASK;
  477. bypass1 = SSCG_PLL_BYPASS1_MASK;
  478. bypass2 = SSCG_PLL_BYPASS2_MASK;
  479. /* Enable DDR1 and DDR2 domain */
  480. writel(SRC_DDR1_ENABLE_MASK, &src->ddr1_rcr);
  481. writel(SRC_DDR1_ENABLE_MASK, &src->ddr2_rcr);
  482. /* Clear power down bit */
  483. clrbits_le32(pll_control_reg, pwdn_mask);
  484. /* Eanble ARM_PLL/SYS_PLL */
  485. setbits_le32(pll_control_reg, pll_clke);
  486. /* Clear bypass */
  487. clrbits_le32(pll_control_reg, bypass1);
  488. __udelay(100);
  489. clrbits_le32(pll_control_reg, bypass2);
  490. /* Wait lock */
  491. ret = readl_poll_timeout(pll_control_reg, val,
  492. val & SSCG_PLL_LOCK_MASK, 1);
  493. if (ret)
  494. printf("%s timeout\n", __func__);
  495. }
  496. int frac_pll_init(u32 pll, enum frac_pll_out_val val)
  497. {
  498. void __iomem *pll_cfg0, __iomem *pll_cfg1;
  499. u32 val_cfg0, val_cfg1;
  500. int ret;
  501. switch (pll) {
  502. case ANATOP_ARM_PLL:
  503. pll_cfg0 = &ana_pll->arm_pll_cfg0;
  504. pll_cfg1 = &ana_pll->arm_pll_cfg1;
  505. if (val == FRAC_PLL_OUT_1000M)
  506. val_cfg1 = FRAC_PLL_INT_DIV_CTL_VAL(49);
  507. else
  508. val_cfg1 = FRAC_PLL_INT_DIV_CTL_VAL(79);
  509. val_cfg0 = FRAC_PLL_CLKE_MASK | FRAC_PLL_REFCLK_SEL_OSC_25M |
  510. FRAC_PLL_LOCK_SEL_MASK | FRAC_PLL_NEWDIV_VAL_MASK |
  511. FRAC_PLL_REFCLK_DIV_VAL(4) |
  512. FRAC_PLL_OUTPUT_DIV_VAL(0);
  513. break;
  514. default:
  515. return -EINVAL;
  516. }
  517. /* bypass the clock */
  518. setbits_le32(pll_cfg0, FRAC_PLL_BYPASS_MASK);
  519. /* Set the value */
  520. writel(val_cfg1, pll_cfg1);
  521. writel(val_cfg0 | FRAC_PLL_BYPASS_MASK, pll_cfg0);
  522. val_cfg0 = readl(pll_cfg0);
  523. /* unbypass the clock */
  524. clrbits_le32(pll_cfg0, FRAC_PLL_BYPASS_MASK);
  525. ret = readl_poll_timeout(pll_cfg0, val_cfg0,
  526. val_cfg0 & FRAC_PLL_LOCK_MASK, 1);
  527. if (ret)
  528. printf("%s timeout\n", __func__);
  529. clrbits_le32(pll_cfg0, FRAC_PLL_NEWDIV_VAL_MASK);
  530. return 0;
  531. }
  532. int sscg_pll_init(u32 pll)
  533. {
  534. void __iomem *pll_cfg0, __iomem *pll_cfg1, __iomem *pll_cfg2;
  535. u32 val_cfg0, val_cfg1, val_cfg2, val;
  536. u32 bypass1_mask = 0x20, bypass2_mask = 0x10;
  537. int ret;
  538. switch (pll) {
  539. case ANATOP_SYSTEM_PLL1:
  540. pll_cfg0 = &ana_pll->sys_pll1_cfg0;
  541. pll_cfg1 = &ana_pll->sys_pll1_cfg1;
  542. pll_cfg2 = &ana_pll->sys_pll1_cfg2;
  543. /* 800MHz */
  544. val_cfg2 = SSCG_PLL_FEEDBACK_DIV_F1_VAL(3) |
  545. SSCG_PLL_FEEDBACK_DIV_F2_VAL(3);
  546. val_cfg1 = 0;
  547. val_cfg0 = SSCG_PLL_CLKE_MASK | SSCG_PLL_DIV2_CLKE_MASK |
  548. SSCG_PLL_DIV3_CLKE_MASK | SSCG_PLL_DIV4_CLKE_MASK |
  549. SSCG_PLL_DIV5_CLKE_MASK | SSCG_PLL_DIV6_CLKE_MASK |
  550. SSCG_PLL_DIV8_CLKE_MASK | SSCG_PLL_DIV10_CLKE_MASK |
  551. SSCG_PLL_DIV20_CLKE_MASK | SSCG_PLL_LOCK_SEL_MASK |
  552. SSCG_PLL_REFCLK_SEL_OSC_25M;
  553. break;
  554. case ANATOP_SYSTEM_PLL2:
  555. pll_cfg0 = &ana_pll->sys_pll2_cfg0;
  556. pll_cfg1 = &ana_pll->sys_pll2_cfg1;
  557. pll_cfg2 = &ana_pll->sys_pll2_cfg2;
  558. /* 1000MHz */
  559. val_cfg2 = SSCG_PLL_FEEDBACK_DIV_F1_VAL(3) |
  560. SSCG_PLL_FEEDBACK_DIV_F2_VAL(4);
  561. val_cfg1 = 0;
  562. val_cfg0 = SSCG_PLL_CLKE_MASK | SSCG_PLL_DIV2_CLKE_MASK |
  563. SSCG_PLL_DIV3_CLKE_MASK | SSCG_PLL_DIV4_CLKE_MASK |
  564. SSCG_PLL_DIV5_CLKE_MASK | SSCG_PLL_DIV6_CLKE_MASK |
  565. SSCG_PLL_DIV8_CLKE_MASK | SSCG_PLL_DIV10_CLKE_MASK |
  566. SSCG_PLL_DIV20_CLKE_MASK | SSCG_PLL_LOCK_SEL_MASK |
  567. SSCG_PLL_REFCLK_SEL_OSC_25M;
  568. break;
  569. case ANATOP_SYSTEM_PLL3:
  570. pll_cfg0 = &ana_pll->sys_pll3_cfg0;
  571. pll_cfg1 = &ana_pll->sys_pll3_cfg1;
  572. pll_cfg2 = &ana_pll->sys_pll3_cfg2;
  573. /* 800MHz */
  574. val_cfg2 = SSCG_PLL_FEEDBACK_DIV_F1_VAL(3) |
  575. SSCG_PLL_FEEDBACK_DIV_F2_VAL(3);
  576. val_cfg1 = 0;
  577. val_cfg0 = SSCG_PLL_PLL3_CLKE_MASK | SSCG_PLL_LOCK_SEL_MASK |
  578. SSCG_PLL_REFCLK_SEL_OSC_25M;
  579. break;
  580. default:
  581. return -EINVAL;
  582. }
  583. /*bypass*/
  584. setbits_le32(pll_cfg0, bypass1_mask | bypass2_mask);
  585. /* set value */
  586. writel(val_cfg2, pll_cfg2);
  587. writel(val_cfg1, pll_cfg1);
  588. /*unbypass1 and wait 70us */
  589. writel(val_cfg0 | bypass2_mask, pll_cfg1);
  590. __udelay(70);
  591. /* unbypass2 and wait lock */
  592. writel(val_cfg0, pll_cfg1);
  593. ret = readl_poll_timeout(pll_cfg0, val, val & SSCG_PLL_LOCK_MASK, 1);
  594. if (ret)
  595. printf("%s timeout\n", __func__);
  596. return ret;
  597. }
  598. int clock_init(void)
  599. {
  600. u32 grade;
  601. clock_set_target_val(ARM_A53_CLK_ROOT, CLK_ROOT_ON |
  602. CLK_ROOT_SOURCE_SEL(0));
  603. /*
  604. * 8MQ only supports two grades: consumer and industrial.
  605. * We set ARM clock to 1Ghz for consumer, 800Mhz for industrial
  606. */
  607. grade = get_cpu_temp_grade(NULL, NULL);
  608. if (!grade) {
  609. frac_pll_init(ANATOP_ARM_PLL, FRAC_PLL_OUT_1000M);
  610. clock_set_target_val(ARM_A53_CLK_ROOT, CLK_ROOT_ON |
  611. CLK_ROOT_SOURCE_SEL(1) |
  612. CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1));
  613. } else {
  614. frac_pll_init(ANATOP_ARM_PLL, FRAC_PLL_OUT_1600M);
  615. clock_set_target_val(ARM_A53_CLK_ROOT, CLK_ROOT_ON |
  616. CLK_ROOT_SOURCE_SEL(1) |
  617. CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV2));
  618. }
  619. /*
  620. * According to ANAMIX SPEC
  621. * sys pll1 fixed at 800MHz
  622. * sys pll2 fixed at 1GHz
  623. * Here we only enable the outputs.
  624. */
  625. setbits_le32(&ana_pll->sys_pll1_cfg0, SSCG_PLL_CLKE_MASK |
  626. SSCG_PLL_DIV2_CLKE_MASK | SSCG_PLL_DIV3_CLKE_MASK |
  627. SSCG_PLL_DIV4_CLKE_MASK | SSCG_PLL_DIV5_CLKE_MASK |
  628. SSCG_PLL_DIV6_CLKE_MASK | SSCG_PLL_DIV8_CLKE_MASK |
  629. SSCG_PLL_DIV10_CLKE_MASK | SSCG_PLL_DIV20_CLKE_MASK);
  630. setbits_le32(&ana_pll->sys_pll2_cfg0, SSCG_PLL_CLKE_MASK |
  631. SSCG_PLL_DIV2_CLKE_MASK | SSCG_PLL_DIV3_CLKE_MASK |
  632. SSCG_PLL_DIV4_CLKE_MASK | SSCG_PLL_DIV5_CLKE_MASK |
  633. SSCG_PLL_DIV6_CLKE_MASK | SSCG_PLL_DIV8_CLKE_MASK |
  634. SSCG_PLL_DIV10_CLKE_MASK | SSCG_PLL_DIV20_CLKE_MASK);
  635. clock_set_target_val(NAND_USDHC_BUS_CLK_ROOT, CLK_ROOT_ON |
  636. CLK_ROOT_SOURCE_SEL(1));
  637. init_wdog_clk();
  638. clock_enable(CCGR_TSENSOR, 1);
  639. return 0;
  640. }
  641. #endif
  642. /*
  643. * Dump some clockes.
  644. */
  645. #ifndef CONFIG_SPL_BUILD
  646. int do_mx8m_showclocks(cmd_tbl_t *cmdtp, int flag, int argc,
  647. char * const argv[])
  648. {
  649. u32 freq;
  650. freq = decode_frac_pll(ARM_PLL_CLK);
  651. printf("ARM_PLL %8d MHz\n", freq / 1000000);
  652. freq = decode_sscg_pll(SYSTEM_PLL1_800M_CLK);
  653. printf("SYS_PLL1_800 %8d MHz\n", freq / 1000000);
  654. freq = decode_sscg_pll(SYSTEM_PLL1_400M_CLK);
  655. printf("SYS_PLL1_400 %8d MHz\n", freq / 1000000);
  656. freq = decode_sscg_pll(SYSTEM_PLL1_266M_CLK);
  657. printf("SYS_PLL1_266 %8d MHz\n", freq / 1000000);
  658. freq = decode_sscg_pll(SYSTEM_PLL1_200M_CLK);
  659. printf("SYS_PLL1_200 %8d MHz\n", freq / 1000000);
  660. freq = decode_sscg_pll(SYSTEM_PLL1_160M_CLK);
  661. printf("SYS_PLL1_160 %8d MHz\n", freq / 1000000);
  662. freq = decode_sscg_pll(SYSTEM_PLL1_133M_CLK);
  663. printf("SYS_PLL1_133 %8d MHz\n", freq / 1000000);
  664. freq = decode_sscg_pll(SYSTEM_PLL1_100M_CLK);
  665. printf("SYS_PLL1_100 %8d MHz\n", freq / 1000000);
  666. freq = decode_sscg_pll(SYSTEM_PLL1_80M_CLK);
  667. printf("SYS_PLL1_80 %8d MHz\n", freq / 1000000);
  668. freq = decode_sscg_pll(SYSTEM_PLL1_40M_CLK);
  669. printf("SYS_PLL1_40 %8d MHz\n", freq / 1000000);
  670. freq = decode_sscg_pll(SYSTEM_PLL2_1000M_CLK);
  671. printf("SYS_PLL2_1000 %8d MHz\n", freq / 1000000);
  672. freq = decode_sscg_pll(SYSTEM_PLL2_500M_CLK);
  673. printf("SYS_PLL2_500 %8d MHz\n", freq / 1000000);
  674. freq = decode_sscg_pll(SYSTEM_PLL2_333M_CLK);
  675. printf("SYS_PLL2_333 %8d MHz\n", freq / 1000000);
  676. freq = decode_sscg_pll(SYSTEM_PLL2_250M_CLK);
  677. printf("SYS_PLL2_250 %8d MHz\n", freq / 1000000);
  678. freq = decode_sscg_pll(SYSTEM_PLL2_200M_CLK);
  679. printf("SYS_PLL2_200 %8d MHz\n", freq / 1000000);
  680. freq = decode_sscg_pll(SYSTEM_PLL2_166M_CLK);
  681. printf("SYS_PLL2_166 %8d MHz\n", freq / 1000000);
  682. freq = decode_sscg_pll(SYSTEM_PLL2_125M_CLK);
  683. printf("SYS_PLL2_125 %8d MHz\n", freq / 1000000);
  684. freq = decode_sscg_pll(SYSTEM_PLL2_100M_CLK);
  685. printf("SYS_PLL2_100 %8d MHz\n", freq / 1000000);
  686. freq = decode_sscg_pll(SYSTEM_PLL2_50M_CLK);
  687. printf("SYS_PLL2_50 %8d MHz\n", freq / 1000000);
  688. freq = decode_sscg_pll(SYSTEM_PLL3_CLK);
  689. printf("SYS_PLL3 %8d MHz\n", freq / 1000000);
  690. freq = mxc_get_clock(UART1_CLK_ROOT);
  691. printf("UART1 %8d MHz\n", freq / 1000000);
  692. freq = mxc_get_clock(USDHC1_CLK_ROOT);
  693. printf("USDHC1 %8d MHz\n", freq / 1000000);
  694. freq = mxc_get_clock(QSPI_CLK_ROOT);
  695. printf("QSPI %8d MHz\n", freq / 1000000);
  696. return 0;
  697. }
  698. U_BOOT_CMD(
  699. clocks, CONFIG_SYS_MAXARGS, 1, do_mx8m_showclocks,
  700. "display clocks",
  701. ""
  702. );
  703. #endif