rk3368.c 7.3 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (c) 2016 Rockchip Electronics Co., Ltd
  4. * Copyright (c) 2016 Andreas Färber
  5. */
  6. #include <common.h>
  7. #include <init.h>
  8. #include <syscon.h>
  9. #include <asm/armv8/mmu.h>
  10. #include <asm/io.h>
  11. #include <asm/arch-rockchip/bootrom.h>
  12. #include <asm/arch-rockchip/clock.h>
  13. #include <asm/arch-rockchip/cru_rk3368.h>
  14. #include <asm/arch-rockchip/grf_rk3368.h>
  15. #include <asm/arch-rockchip/hardware.h>
  16. #include <linux/bitops.h>
  17. #include <linux/delay.h>
  18. DECLARE_GLOBAL_DATA_PTR;
  19. #define IMEM_BASE 0xFF8C0000
  20. /* Max MCU's SRAM value is 8K, begin at (IMEM_BASE + 4K) */
  21. #define MCU_SRAM_BASE (IMEM_BASE + 1024 * 4)
  22. #define MCU_SRAM_BASE_BIT31_BIT28 ((MCU_SRAM_BASE & GENMASK(31, 28)) >> 28)
  23. #define MCU_SRAM_BASE_BIT27_BIT12 ((MCU_SRAM_BASE & GENMASK(27, 12)) >> 12)
  24. /* exsram may using by mcu to accessing dram(0x0-0x20000000) */
  25. #define MCU_EXSRAM_BASE (0)
  26. #define MCU_EXSRAM_BASE_BIT31_BIT28 ((MCU_EXSRAM_BASE & GENMASK(31, 28)) >> 28)
  27. #define MCU_EXSRAM_BASE_BIT27_BIT12 ((MCU_EXSRAM_BASE & GENMASK(27, 12)) >> 12)
  28. /* experi no used, reserved value = 0 */
  29. #define MCU_EXPERI_BASE (0)
  30. #define MCU_EXPERI_BASE_BIT31_BIT28 ((MCU_EXPERI_BASE & GENMASK(31, 28)) >> 28)
  31. #define MCU_EXPERI_BASE_BIT27_BIT12 ((MCU_EXPERI_BASE & GENMASK(27, 12)) >> 12)
  32. static struct mm_region rk3368_mem_map[] = {
  33. {
  34. .virt = 0x0UL,
  35. .phys = 0x0UL,
  36. .size = 0x80000000UL,
  37. .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
  38. PTE_BLOCK_INNER_SHARE
  39. }, {
  40. .virt = 0xf0000000UL,
  41. .phys = 0xf0000000UL,
  42. .size = 0x10000000UL,
  43. .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
  44. PTE_BLOCK_NON_SHARE |
  45. PTE_BLOCK_PXN | PTE_BLOCK_UXN
  46. }, {
  47. /* List terminator */
  48. 0,
  49. }
  50. };
  51. struct mm_region *mem_map = rk3368_mem_map;
  52. const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1] = {
  53. [BROM_BOOTSOURCE_EMMC] = "/dwmmc@ff0f0000",
  54. [BROM_BOOTSOURCE_SD] = "/dwmmc@ff0c0000",
  55. };
  56. #ifdef CONFIG_ARCH_EARLY_INIT_R
  57. static int mcu_init(void)
  58. {
  59. struct rk3368_grf *grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
  60. struct rk3368_cru *cru = rockchip_get_cru();
  61. rk_clrsetreg(&grf->soc_con14, MCU_SRAM_BASE_BIT31_BIT28_MASK,
  62. MCU_SRAM_BASE_BIT31_BIT28 << MCU_SRAM_BASE_BIT31_BIT28_SHIFT);
  63. rk_clrsetreg(&grf->soc_con11, MCU_SRAM_BASE_BIT27_BIT12_MASK,
  64. MCU_SRAM_BASE_BIT27_BIT12 << MCU_SRAM_BASE_BIT27_BIT12_SHIFT);
  65. rk_clrsetreg(&grf->soc_con14, MCU_EXSRAM_BASE_BIT31_BIT28_MASK,
  66. MCU_EXSRAM_BASE_BIT31_BIT28 << MCU_EXSRAM_BASE_BIT31_BIT28_SHIFT);
  67. rk_clrsetreg(&grf->soc_con12, MCU_EXSRAM_BASE_BIT27_BIT12_MASK,
  68. MCU_EXSRAM_BASE_BIT27_BIT12 << MCU_EXSRAM_BASE_BIT27_BIT12_SHIFT);
  69. rk_clrsetreg(&grf->soc_con14, MCU_EXPERI_BASE_BIT31_BIT28_MASK,
  70. MCU_EXPERI_BASE_BIT31_BIT28 << MCU_EXPERI_BASE_BIT31_BIT28_SHIFT);
  71. rk_clrsetreg(&grf->soc_con13, MCU_EXPERI_BASE_BIT27_BIT12_MASK,
  72. MCU_EXPERI_BASE_BIT27_BIT12 << MCU_EXPERI_BASE_BIT27_BIT12_SHIFT);
  73. rk_clrsetreg(&cru->clksel_con[12], MCU_PLL_SEL_MASK | MCU_CLK_DIV_MASK,
  74. (MCU_PLL_SEL_GPLL << MCU_PLL_SEL_SHIFT) |
  75. (5 << MCU_CLK_DIV_SHIFT));
  76. /* mcu dereset, for start running */
  77. rk_clrreg(&cru->softrst_con[1], MCU_PO_SRST_MASK | MCU_SYS_SRST_MASK);
  78. return 0;
  79. }
  80. int arch_early_init_r(void)
  81. {
  82. return mcu_init();
  83. }
  84. #endif
  85. #ifdef CONFIG_SPL_BUILD
  86. /*
  87. * The SPL (and also the full U-Boot stage on the RK3368) will run in
  88. * secure mode (i.e. EL3) and an ATF will eventually be booted before
  89. * starting up the operating system... so we can initialize the SGRF
  90. * here and rely on the ATF installing the final (secure) policy
  91. * later.
  92. */
  93. static inline uintptr_t sgrf_soc_con_addr(unsigned int no)
  94. {
  95. const uintptr_t SGRF_BASE =
  96. (uintptr_t)syscon_get_first_range(ROCKCHIP_SYSCON_SGRF);
  97. return SGRF_BASE + sizeof(u32) * no;
  98. }
  99. static inline uintptr_t sgrf_busdmac_addr(unsigned int no)
  100. {
  101. const uintptr_t SGRF_BASE =
  102. (uintptr_t)syscon_get_first_range(ROCKCHIP_SYSCON_SGRF);
  103. const uintptr_t SGRF_BUSDMAC_OFFSET = 0x100;
  104. const uintptr_t SGRF_BUSDMAC_BASE = SGRF_BASE + SGRF_BUSDMAC_OFFSET;
  105. return SGRF_BUSDMAC_BASE + sizeof(u32) * no;
  106. }
  107. static void sgrf_init(void)
  108. {
  109. struct rk3368_cru * const cru =
  110. (struct rk3368_cru * const)rockchip_get_cru();
  111. const u16 SGRF_SOC_CON_SEC = GENMASK(15, 0);
  112. const u16 SGRF_BUSDMAC_CON0_SEC = BIT(2);
  113. const u16 SGRF_BUSDMAC_CON1_SEC = GENMASK(15, 12);
  114. /* Set all configurable IP to 'non secure'-mode */
  115. rk_setreg(sgrf_soc_con_addr(5), SGRF_SOC_CON_SEC);
  116. rk_setreg(sgrf_soc_con_addr(6), SGRF_SOC_CON_SEC);
  117. rk_setreg(sgrf_soc_con_addr(7), SGRF_SOC_CON_SEC);
  118. /*
  119. * From rockchip-uboot/arch/arm/cpu/armv8/rk33xx/cpu.c
  120. * Original comment: "ddr space set no secure mode"
  121. */
  122. rk_clrreg(sgrf_soc_con_addr(8), SGRF_SOC_CON_SEC);
  123. rk_clrreg(sgrf_soc_con_addr(9), SGRF_SOC_CON_SEC);
  124. rk_clrreg(sgrf_soc_con_addr(10), SGRF_SOC_CON_SEC);
  125. /* Set 'secure dma' to 'non secure'-mode */
  126. rk_setreg(sgrf_busdmac_addr(0), SGRF_BUSDMAC_CON0_SEC);
  127. rk_setreg(sgrf_busdmac_addr(1), SGRF_BUSDMAC_CON1_SEC);
  128. dsb(); /* barrier */
  129. rk_setreg(&cru->softrst_con[1], DMA1_SRST_REQ);
  130. rk_setreg(&cru->softrst_con[4], DMA2_SRST_REQ);
  131. dsb(); /* barrier */
  132. udelay(10);
  133. rk_clrreg(&cru->softrst_con[1], DMA1_SRST_REQ);
  134. rk_clrreg(&cru->softrst_con[4], DMA2_SRST_REQ);
  135. }
  136. int arch_cpu_init(void)
  137. {
  138. /* Reset security, so we can use DMA in the MMC drivers */
  139. sgrf_init();
  140. return 0;
  141. }
  142. #endif
  143. #ifdef CONFIG_DEBUG_UART_BOARD_INIT
  144. void board_debug_uart_init(void)
  145. {
  146. /*
  147. * N.B.: This is called before the device-model has been
  148. * initialised. For this reason, we can not access
  149. * the GRF address range using the syscon API.
  150. */
  151. #if defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xff180000)
  152. struct rk3368_grf * const grf =
  153. (struct rk3368_grf * const)0xff770000;
  154. enum {
  155. GPIO2D1_MASK = GENMASK(3, 2),
  156. GPIO2D1_GPIO = 0,
  157. GPIO2D1_UART0_SOUT = (1 << 2),
  158. GPIO2D0_MASK = GENMASK(1, 0),
  159. GPIO2D0_GPIO = 0,
  160. GPIO2D0_UART0_SIN = (1 << 0),
  161. };
  162. /* Enable early UART0 on the RK3368 */
  163. rk_clrsetreg(&grf->gpio2d_iomux,
  164. GPIO2D0_MASK, GPIO2D0_UART0_SIN);
  165. rk_clrsetreg(&grf->gpio2d_iomux,
  166. GPIO2D1_MASK, GPIO2D1_UART0_SOUT);
  167. #elif defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xff1c0000)
  168. struct rk3368_pmu_grf * const pmugrf __maybe_unused =
  169. (struct rk3368_pmu_grf * const)0xff738000;
  170. enum {
  171. /* UART4 */
  172. GPIO0D2_MASK = GENMASK(5, 4),
  173. GPIO0D2_GPIO = 0,
  174. GPIO0D2_UART4_SOUT = (3 << 4),
  175. GPIO0D3_MASK = GENMASK(7, 6),
  176. GPIO0D3_GPIO = 0,
  177. GPIO0D3_UART4_SIN = (3 << 6),
  178. };
  179. /* Enable early UART4 on the PX5 */
  180. rk_clrsetreg(&pmugrf->gpio0d_iomux,
  181. GPIO0D2_MASK | GPIO0D3_MASK,
  182. GPIO0D2_UART4_SOUT | GPIO0D3_UART4_SIN);
  183. #elif defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xff690000)
  184. struct rk3368_grf * const grf =
  185. (struct rk3368_grf * const)0xff770000;
  186. enum {
  187. GPIO2A6_SHIFT = 12,
  188. GPIO2A6_MASK = GENMASK(13, 12),
  189. GPIO2A6_GPIO = 0,
  190. GPIO2A6_UART2_SIN = (2 << GPIO2A6_SHIFT),
  191. GPIO2A5_SHIFT = 10,
  192. GPIO2A5_MASK = GENMASK(11, 10),
  193. GPIO2A5_GPIO = 0,
  194. GPIO2A5_UART2_SOUT = (2 << GPIO2A5_SHIFT),
  195. };
  196. /* Enable early UART2 on the RK3368 */
  197. rk_clrsetreg(&grf->gpio2a_iomux,
  198. GPIO2A6_MASK, GPIO2A6_UART2_SIN);
  199. rk_clrsetreg(&grf->gpio2a_iomux,
  200. GPIO2A5_MASK, GPIO2A5_UART2_SOUT);
  201. #endif
  202. }
  203. #endif