pipe3-phy.c 5.9 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * TI PIPE3 PHY
  4. *
  5. * (C) Copyright 2013
  6. * Texas Instruments, <www.ti.com>
  7. */
  8. #include <common.h>
  9. #include <sata.h>
  10. #include <asm/arch/clock.h>
  11. #include <asm/arch/sys_proto.h>
  12. #include <asm/io.h>
  13. #include <linux/bitops.h>
  14. #include <linux/delay.h>
  15. #include <linux/errno.h>
  16. #include "pipe3-phy.h"
  17. /* PLLCTRL Registers */
  18. #define PLL_STATUS 0x00000004
  19. #define PLL_GO 0x00000008
  20. #define PLL_CONFIGURATION1 0x0000000C
  21. #define PLL_CONFIGURATION2 0x00000010
  22. #define PLL_CONFIGURATION3 0x00000014
  23. #define PLL_CONFIGURATION4 0x00000020
  24. #define PLL_REGM_MASK 0x001FFE00
  25. #define PLL_REGM_SHIFT 9
  26. #define PLL_REGM_F_MASK 0x0003FFFF
  27. #define PLL_REGM_F_SHIFT 0
  28. #define PLL_REGN_MASK 0x000001FE
  29. #define PLL_REGN_SHIFT 1
  30. #define PLL_SELFREQDCO_MASK 0x0000000E
  31. #define PLL_SELFREQDCO_SHIFT 1
  32. #define PLL_SD_MASK 0x0003FC00
  33. #define PLL_SD_SHIFT 10
  34. #define SET_PLL_GO 0x1
  35. #define PLL_TICOPWDN BIT(16)
  36. #define PLL_LDOPWDN BIT(15)
  37. #define PLL_LOCK 0x2
  38. #define PLL_IDLE 0x1
  39. /* PHY POWER CONTROL Register */
  40. #define OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_CMD_MASK 0x003FC000
  41. #define OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_CMD_SHIFT 0xE
  42. #define OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_FREQ_MASK 0xFFC00000
  43. #define OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_FREQ_SHIFT 0x16
  44. #define OMAP_CTRL_PIPE3_PHY_TX_RX_POWERON 0x3
  45. #define OMAP_CTRL_PIPE3_PHY_TX_RX_POWEROFF 0x0
  46. #define PLL_IDLE_TIME 100 /* in milliseconds */
  47. #define PLL_LOCK_TIME 100 /* in milliseconds */
  48. static inline u32 omap_pipe3_readl(void __iomem *addr, unsigned offset)
  49. {
  50. return __raw_readl(addr + offset);
  51. }
  52. static inline void omap_pipe3_writel(void __iomem *addr, unsigned offset,
  53. u32 data)
  54. {
  55. __raw_writel(data, addr + offset);
  56. }
  57. static struct pipe3_dpll_params *omap_pipe3_get_dpll_params(struct omap_pipe3
  58. *pipe3)
  59. {
  60. u32 rate;
  61. struct pipe3_dpll_map *dpll_map = pipe3->dpll_map;
  62. rate = get_sys_clk_freq();
  63. for (; dpll_map->rate; dpll_map++) {
  64. if (rate == dpll_map->rate)
  65. return &dpll_map->params;
  66. }
  67. printf("%s: No DPLL configuration for %u Hz SYS CLK\n",
  68. __func__, rate);
  69. return NULL;
  70. }
  71. static int omap_pipe3_wait_lock(struct omap_pipe3 *phy)
  72. {
  73. u32 val;
  74. int timeout = PLL_LOCK_TIME;
  75. do {
  76. mdelay(1);
  77. val = omap_pipe3_readl(phy->pll_ctrl_base, PLL_STATUS);
  78. if (val & PLL_LOCK)
  79. break;
  80. } while (--timeout);
  81. if (!(val & PLL_LOCK)) {
  82. printf("%s: DPLL failed to lock\n", __func__);
  83. return -EBUSY;
  84. }
  85. return 0;
  86. }
  87. static int omap_pipe3_dpll_program(struct omap_pipe3 *phy)
  88. {
  89. u32 val;
  90. struct pipe3_dpll_params *dpll_params;
  91. dpll_params = omap_pipe3_get_dpll_params(phy);
  92. if (!dpll_params) {
  93. printf("%s: Invalid DPLL parameters\n", __func__);
  94. return -EINVAL;
  95. }
  96. val = omap_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION1);
  97. val &= ~PLL_REGN_MASK;
  98. val |= dpll_params->n << PLL_REGN_SHIFT;
  99. omap_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION1, val);
  100. val = omap_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION2);
  101. val &= ~PLL_SELFREQDCO_MASK;
  102. val |= dpll_params->freq << PLL_SELFREQDCO_SHIFT;
  103. omap_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION2, val);
  104. val = omap_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION1);
  105. val &= ~PLL_REGM_MASK;
  106. val |= dpll_params->m << PLL_REGM_SHIFT;
  107. omap_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION1, val);
  108. val = omap_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION4);
  109. val &= ~PLL_REGM_F_MASK;
  110. val |= dpll_params->mf << PLL_REGM_F_SHIFT;
  111. omap_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION4, val);
  112. val = omap_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION3);
  113. val &= ~PLL_SD_MASK;
  114. val |= dpll_params->sd << PLL_SD_SHIFT;
  115. omap_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION3, val);
  116. omap_pipe3_writel(phy->pll_ctrl_base, PLL_GO, SET_PLL_GO);
  117. return omap_pipe3_wait_lock(phy);
  118. }
  119. static void omap_control_phy_power(struct omap_pipe3 *phy, int on)
  120. {
  121. u32 val, rate;
  122. val = readl(phy->power_reg);
  123. rate = get_sys_clk_freq();
  124. rate = rate/1000000;
  125. if (on) {
  126. val &= ~(OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_CMD_MASK |
  127. OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_FREQ_MASK);
  128. val |= OMAP_CTRL_PIPE3_PHY_TX_RX_POWERON <<
  129. OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_CMD_SHIFT;
  130. val |= rate <<
  131. OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_FREQ_SHIFT;
  132. } else {
  133. val &= ~OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_CMD_MASK;
  134. val |= OMAP_CTRL_PIPE3_PHY_TX_RX_POWEROFF <<
  135. OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_CMD_SHIFT;
  136. }
  137. writel(val, phy->power_reg);
  138. }
  139. int phy_pipe3_power_on(struct omap_pipe3 *phy)
  140. {
  141. int ret;
  142. u32 val;
  143. /* Program the DPLL only if not locked */
  144. val = omap_pipe3_readl(phy->pll_ctrl_base, PLL_STATUS);
  145. if (!(val & PLL_LOCK)) {
  146. ret = omap_pipe3_dpll_program(phy);
  147. if (ret)
  148. return ret;
  149. } else {
  150. /* else just bring it out of IDLE mode */
  151. val = omap_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION2);
  152. if (val & PLL_IDLE) {
  153. val &= ~PLL_IDLE;
  154. omap_pipe3_writel(phy->pll_ctrl_base,
  155. PLL_CONFIGURATION2, val);
  156. ret = omap_pipe3_wait_lock(phy);
  157. if (ret)
  158. return ret;
  159. }
  160. }
  161. /* Power up the PHY */
  162. omap_control_phy_power(phy, 1);
  163. return 0;
  164. }
  165. int phy_pipe3_power_off(struct omap_pipe3 *phy)
  166. {
  167. u32 val;
  168. int timeout = PLL_IDLE_TIME;
  169. /* Power down the PHY */
  170. omap_control_phy_power(phy, 0);
  171. /* Put DPLL in IDLE mode */
  172. val = omap_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION2);
  173. val |= PLL_IDLE;
  174. omap_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION2, val);
  175. /* wait for LDO and Oscillator to power down */
  176. do {
  177. mdelay(1);
  178. val = omap_pipe3_readl(phy->pll_ctrl_base, PLL_STATUS);
  179. if ((val & PLL_TICOPWDN) && (val & PLL_LDOPWDN))
  180. break;
  181. } while (--timeout);
  182. if (!(val & PLL_TICOPWDN) || !(val & PLL_LDOPWDN)) {
  183. printf("%s: Failed to power down DPLL: PLL_STATUS 0x%x\n",
  184. __func__, val);
  185. return -EBUSY;
  186. }
  187. return 0;
  188. }