clock_ti816x.c 11 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407
  1. /*
  2. * clock_ti816x.c
  3. *
  4. * Clocks for TI816X based boards
  5. *
  6. * Copyright (C) 2013, Adeneo Embedded <www.adeneo-embedded.com>
  7. * Antoine Tenart, <atenart@adeneo-embedded.com>
  8. *
  9. * Based on TI-PSP-04.00.02.14 :
  10. *
  11. * Copyright (C) 2009, Texas Instruments, Incorporated
  12. *
  13. * This program is free software; you can redistribute it and/or
  14. * modify it under the terms of the GNU General Public License as
  15. * published by the Free Software Foundation; either version 2 of
  16. * the License, or (at your option) any later version.
  17. *
  18. * This program is distributed in the hope that it will be useful,
  19. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  20. * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the
  21. * GNU General Public License for more details.
  22. */
  23. #include <common.h>
  24. #include <asm/arch/ddr_defs.h>
  25. #include <asm/arch/cpu.h>
  26. #include <asm/arch/clock.h>
  27. #include <asm/arch/hardware.h>
  28. #include <asm/io.h>
  29. #include <linux/bitops.h>
  30. #include <asm/emif.h>
  31. #define CM_PLL_BASE (CTRL_BASE + 0x0400)
  32. /* Main PLL */
  33. #define MAIN_N 64
  34. #define MAIN_P 0x1
  35. #define MAIN_INTFREQ1 0x8
  36. #define MAIN_FRACFREQ1 0x800000
  37. #define MAIN_MDIV1 0x2
  38. #define MAIN_INTFREQ2 0xE
  39. #define MAIN_FRACFREQ2 0x0
  40. #define MAIN_MDIV2 0x1
  41. #define MAIN_INTFREQ3 0x8
  42. #define MAIN_FRACFREQ3 0xAAAAB0
  43. #define MAIN_MDIV3 0x3
  44. #define MAIN_INTFREQ4 0x9
  45. #define MAIN_FRACFREQ4 0x55554F
  46. #define MAIN_MDIV4 0x3
  47. #define MAIN_INTFREQ5 0x9
  48. #define MAIN_FRACFREQ5 0x374BC6
  49. #define MAIN_MDIV5 0xC
  50. #define MAIN_MDIV6 0x48
  51. #define MAIN_MDIV7 0x4
  52. /* DDR PLL */
  53. #define DDR_N 59
  54. #define DDR_P 0x1
  55. #define DDR_MDIV1 0x2
  56. #define DDR_INTFREQ2 0x8
  57. #define DDR_FRACFREQ2 0xD99999
  58. #define DDR_MDIV2 0x1E
  59. #define DDR_INTFREQ3 0x8
  60. #define DDR_FRACFREQ3 0x0
  61. #define DDR_MDIV3 0x4
  62. #define DDR_INTFREQ4 0xE /* Expansion DDR clk */
  63. #define DDR_FRACFREQ4 0x0
  64. #define DDR_MDIV4 0x4
  65. #define DDR_INTFREQ5 0xE /* Expansion DDR clk */
  66. #define DDR_FRACFREQ5 0x0
  67. #define DDR_MDIV5 0x4
  68. #define CONTROL_STATUS (CTRL_BASE + 0x40)
  69. #define DDR_RCD (CTRL_BASE + 0x070C)
  70. #define CM_TIMER1_CLKSEL (PRCM_BASE + 0x390)
  71. #define CM_ALWON_CUST_EFUSE_CLKCTRL (PRCM_BASE + 0x1628)
  72. #define INTCPS_SYSCONFIG 0x48200010
  73. #define CM_SYSCLK10_CLKSEL 0x48180324
  74. struct cm_pll {
  75. unsigned int mainpll_ctrl; /* offset 0x400 */
  76. unsigned int mainpll_pwd;
  77. unsigned int mainpll_freq1;
  78. unsigned int mainpll_div1;
  79. unsigned int mainpll_freq2;
  80. unsigned int mainpll_div2;
  81. unsigned int mainpll_freq3;
  82. unsigned int mainpll_div3;
  83. unsigned int mainpll_freq4;
  84. unsigned int mainpll_div4;
  85. unsigned int mainpll_freq5;
  86. unsigned int mainpll_div5;
  87. unsigned int resv0[1];
  88. unsigned int mainpll_div6;
  89. unsigned int resv1[1];
  90. unsigned int mainpll_div7;
  91. unsigned int ddrpll_ctrl; /* offset 0x440 */
  92. unsigned int ddrpll_pwd;
  93. unsigned int resv2[1];
  94. unsigned int ddrpll_div1;
  95. unsigned int ddrpll_freq2;
  96. unsigned int ddrpll_div2;
  97. unsigned int ddrpll_freq3;
  98. unsigned int ddrpll_div3;
  99. unsigned int ddrpll_freq4;
  100. unsigned int ddrpll_div4;
  101. unsigned int ddrpll_freq5;
  102. unsigned int ddrpll_div5;
  103. unsigned int videopll_ctrl; /* offset 0x470 */
  104. unsigned int videopll_pwd;
  105. unsigned int videopll_freq1;
  106. unsigned int videopll_div1;
  107. unsigned int videopll_freq2;
  108. unsigned int videopll_div2;
  109. unsigned int videopll_freq3;
  110. unsigned int videopll_div3;
  111. unsigned int resv3[4];
  112. unsigned int audiopll_ctrl; /* offset 0x4A0 */
  113. unsigned int audiopll_pwd;
  114. unsigned int resv4[2];
  115. unsigned int audiopll_freq2;
  116. unsigned int audiopll_div2;
  117. unsigned int audiopll_freq3;
  118. unsigned int audiopll_div3;
  119. unsigned int audiopll_freq4;
  120. unsigned int audiopll_div4;
  121. unsigned int audiopll_freq5;
  122. unsigned int audiopll_div5;
  123. };
  124. const struct cm_alwon *cmalwon = (struct cm_alwon *)CM_ALWON_BASE;
  125. const struct cm_def *cmdef = (struct cm_def *)CM_DEFAULT_BASE;
  126. const struct cm_pll *cmpll = (struct cm_pll *)CM_PLL_BASE;
  127. const struct wd_timer *wdtimer = (struct wd_timer *)WDT_BASE;
  128. void enable_dmm_clocks(void)
  129. {
  130. writel(PRCM_MOD_EN, &cmdef->dmmclkctrl);
  131. /* Wait for dmm to be fully functional, including OCP */
  132. while (((readl(&cmdef->dmmclkctrl) >> 17) & 0x3) != 0)
  133. ;
  134. }
  135. void enable_emif_clocks(void)
  136. {
  137. writel(PRCM_MOD_EN, &cmdef->fwclkctrl);
  138. writel(PRCM_MOD_EN, &cmdef->l3fastclkstctrl);
  139. writel(PRCM_MOD_EN, &cmdef->emif0clkctrl);
  140. writel(PRCM_MOD_EN, &cmdef->emif1clkctrl);
  141. /* Wait for clocks to be active */
  142. while ((readl(&cmdef->l3fastclkstctrl) & 0x300) != 0x300)
  143. ;
  144. /* Wait for emif0 to be fully functional, including OCP */
  145. while (((readl(&cmdef->emif0clkctrl) >> 17) & 0x3) != 0)
  146. ;
  147. /* Wait for emif1 to be fully functional, including OCP */
  148. while (((readl(&cmdef->emif1clkctrl) >> 17) & 0x3) != 0)
  149. ;
  150. }
  151. /* assume delay is aprox at least 1us */
  152. static void ddr_delay(int d)
  153. {
  154. int i;
  155. /*
  156. * read a control register.
  157. * this is a bit more delay and cannot be optimized by the compiler
  158. * assuming one read takes 200 cycles and A8 is runing 1 GHz
  159. * somewhat conservative setting
  160. */
  161. for (i = 0; i < 50*d; i++)
  162. readl(CONTROL_STATUS);
  163. }
  164. static void main_pll_init_ti816x(void)
  165. {
  166. u32 main_pll_ctrl = 0;
  167. /* Put the PLL in bypass mode by setting BIT2 in its ctrl reg */
  168. main_pll_ctrl = readl(&cmpll->mainpll_ctrl);
  169. main_pll_ctrl &= 0xFFFFFFFB;
  170. main_pll_ctrl |= BIT(2);
  171. writel(main_pll_ctrl, &cmpll->mainpll_ctrl);
  172. /* Enable PLL by setting BIT3 in its ctrl reg */
  173. main_pll_ctrl = readl(&cmpll->mainpll_ctrl);
  174. main_pll_ctrl &= 0xFFFFFFF7;
  175. main_pll_ctrl |= BIT(3);
  176. writel(main_pll_ctrl, &cmpll->mainpll_ctrl);
  177. /* Write the values of N,P in the CTRL reg */
  178. main_pll_ctrl = readl(&cmpll->mainpll_ctrl);
  179. main_pll_ctrl &= 0xFF;
  180. main_pll_ctrl |= (MAIN_N<<16 | MAIN_P<<8);
  181. writel(main_pll_ctrl, &cmpll->mainpll_ctrl);
  182. /* Power up clock1-7 */
  183. writel(0x0, &cmpll->mainpll_pwd);
  184. /* Program the freq and divider values for clock1-7 */
  185. writel((1<<31 | 1<<28 | (MAIN_INTFREQ1<<24) | MAIN_FRACFREQ1),
  186. &cmpll->mainpll_freq1);
  187. writel(((1<<8) | MAIN_MDIV1), &cmpll->mainpll_div1);
  188. writel((1<<31 | 1<<28 | (MAIN_INTFREQ2<<24) | MAIN_FRACFREQ2),
  189. &cmpll->mainpll_freq2);
  190. writel(((1<<8) | MAIN_MDIV2), &cmpll->mainpll_div2);
  191. writel((1<<31 | 1<<28 | (MAIN_INTFREQ3<<24) | MAIN_FRACFREQ3),
  192. &cmpll->mainpll_freq3);
  193. writel(((1<<8) | MAIN_MDIV3), &cmpll->mainpll_div3);
  194. writel((1<<31 | 1<<28 | (MAIN_INTFREQ4<<24) | MAIN_FRACFREQ4),
  195. &cmpll->mainpll_freq4);
  196. writel(((1<<8) | MAIN_MDIV4), &cmpll->mainpll_div4);
  197. writel((1<<31 | 1<<28 | (MAIN_INTFREQ5<<24) | MAIN_FRACFREQ5),
  198. &cmpll->mainpll_freq5);
  199. writel(((1<<8) | MAIN_MDIV5), &cmpll->mainpll_div5);
  200. writel((1<<8 | MAIN_MDIV6), &cmpll->mainpll_div6);
  201. writel((1<<8 | MAIN_MDIV7), &cmpll->mainpll_div7);
  202. /* Wait for PLL to lock */
  203. while ((readl(&cmpll->mainpll_ctrl) & BIT(7)) != BIT(7))
  204. ;
  205. /* Put the PLL in normal mode, disable bypass */
  206. main_pll_ctrl = readl(&cmpll->mainpll_ctrl);
  207. main_pll_ctrl &= 0xFFFFFFFB;
  208. writel(main_pll_ctrl, &cmpll->mainpll_ctrl);
  209. }
  210. static void ddr_pll_bypass_ti816x(void)
  211. {
  212. u32 ddr_pll_ctrl = 0;
  213. /* Put the PLL in bypass mode by setting BIT2 in its ctrl reg */
  214. ddr_pll_ctrl = readl(&cmpll->ddrpll_ctrl);
  215. ddr_pll_ctrl &= 0xFFFFFFFB;
  216. ddr_pll_ctrl |= BIT(2);
  217. writel(ddr_pll_ctrl, &cmpll->ddrpll_ctrl);
  218. }
  219. static void ddr_pll_init_ti816x(void)
  220. {
  221. u32 ddr_pll_ctrl = 0;
  222. /* Enable PLL by setting BIT3 in its ctrl reg */
  223. ddr_pll_ctrl = readl(&cmpll->ddrpll_ctrl);
  224. ddr_pll_ctrl &= 0xFFFFFFF7;
  225. ddr_pll_ctrl |= BIT(3);
  226. writel(ddr_pll_ctrl, &cmpll->ddrpll_ctrl);
  227. /* Write the values of N,P in the CTRL reg */
  228. ddr_pll_ctrl = readl(&cmpll->ddrpll_ctrl);
  229. ddr_pll_ctrl &= 0xFF;
  230. ddr_pll_ctrl |= (DDR_N<<16 | DDR_P<<8);
  231. writel(ddr_pll_ctrl, &cmpll->ddrpll_ctrl);
  232. ddr_delay(10);
  233. /* Power up clock1-5 */
  234. writel(0x0, &cmpll->ddrpll_pwd);
  235. /* Program the freq and divider values for clock1-3 */
  236. writel(((0<<8) | DDR_MDIV1), &cmpll->ddrpll_div1);
  237. ddr_delay(1);
  238. writel(((1<<8) | DDR_MDIV1), &cmpll->ddrpll_div1);
  239. writel((1<<31 | 1<<28 | (DDR_INTFREQ2<<24) | DDR_FRACFREQ2),
  240. &cmpll->ddrpll_freq2);
  241. writel(((1<<8) | DDR_MDIV2), &cmpll->ddrpll_div2);
  242. writel(((0<<8) | DDR_MDIV3), &cmpll->ddrpll_div3);
  243. ddr_delay(1);
  244. writel(((1<<8) | DDR_MDIV3), &cmpll->ddrpll_div3);
  245. ddr_delay(1);
  246. writel((0<<31 | 1<<28 | (DDR_INTFREQ3<<24) | DDR_FRACFREQ3),
  247. &cmpll->ddrpll_freq3);
  248. ddr_delay(1);
  249. writel((1<<31 | 1<<28 | (DDR_INTFREQ3<<24) | DDR_FRACFREQ3),
  250. &cmpll->ddrpll_freq3);
  251. ddr_delay(5);
  252. /* Wait for PLL to lock */
  253. while ((readl(&cmpll->ddrpll_ctrl) & BIT(7)) != BIT(7))
  254. ;
  255. /* Power up RCD */
  256. writel(BIT(0), DDR_RCD);
  257. }
  258. static void peripheral_enable(void)
  259. {
  260. /* Wake-up the l3_slow clock */
  261. writel(PRCM_MOD_EN, &cmalwon->l3slowclkstctrl);
  262. /*
  263. * Note on Timers:
  264. * There are 8 timers(0-7) out of which timer 0 is a secure timer.
  265. * Timer 0 mux should not be changed
  266. *
  267. * To access the timer registers we need the to be
  268. * enabled which is what we do in the first step
  269. */
  270. /* Enable timer1 */
  271. writel(PRCM_MOD_EN, &cmalwon->timer1clkctrl);
  272. /* Select timer1 clock to be CLKIN (27MHz) */
  273. writel(BIT(1), CM_TIMER1_CLKSEL);
  274. /* Wait for timer1 to be ON-ACTIVE */
  275. while (((readl(&cmalwon->l3slowclkstctrl)
  276. & (0x80000<<1))>>20) != 1)
  277. ;
  278. /* Wait for timer1 to be enabled */
  279. while (((readl(&cmalwon->timer1clkctrl) & 0x30000)>>16) != 0)
  280. ;
  281. /* Active posted mode */
  282. writel(PRCM_MOD_EN, (DM_TIMER1_BASE + 0x54));
  283. while (readl(DM_TIMER1_BASE + 0x10) & BIT(0))
  284. ;
  285. /* Start timer1 */
  286. writel(BIT(0), (DM_TIMER1_BASE + 0x38));
  287. /* eFuse */
  288. writel(PRCM_MOD_EN, CM_ALWON_CUST_EFUSE_CLKCTRL);
  289. while (readl(CM_ALWON_CUST_EFUSE_CLKCTRL) != PRCM_MOD_EN)
  290. ;
  291. /* Enable gpio0 */
  292. writel(PRCM_MOD_EN, &cmalwon->gpio0clkctrl);
  293. while (readl(&cmalwon->gpio0clkctrl) != PRCM_MOD_EN)
  294. ;
  295. writel((BIT(1) | BIT(8)), &cmalwon->gpio0clkctrl);
  296. /* Enable gpio1 */
  297. writel(PRCM_MOD_EN, &cmalwon->gpio1clkctrl);
  298. while (readl(&cmalwon->gpio1clkctrl) != PRCM_MOD_EN)
  299. ;
  300. writel((BIT(1) | BIT(8)), &cmalwon->gpio1clkctrl);
  301. /* Enable spi */
  302. writel(PRCM_MOD_EN, &cmalwon->spiclkctrl);
  303. while (readl(&cmalwon->spiclkctrl) != PRCM_MOD_EN)
  304. ;
  305. /* Enable i2c0 */
  306. writel(PRCM_MOD_EN, &cmalwon->i2c0clkctrl);
  307. while (readl(&cmalwon->i2c0clkctrl) != PRCM_MOD_EN)
  308. ;
  309. /* Enable ethernet0 */
  310. writel(PRCM_MOD_EN, &cmalwon->ethclkstctrl);
  311. writel(PRCM_MOD_EN, &cmalwon->ethernet0clkctrl);
  312. writel(PRCM_MOD_EN, &cmalwon->ethernet1clkctrl);
  313. /* Enable hsmmc */
  314. writel(PRCM_MOD_EN, &cmalwon->sdioclkctrl);
  315. while (readl(&cmalwon->sdioclkctrl) != PRCM_MOD_EN)
  316. ;
  317. }
  318. void setup_clocks_for_console(void)
  319. {
  320. /* Fix ROM code bug - from TI-PSP-04.00.02.14 */
  321. writel(0x0, CM_SYSCLK10_CLKSEL);
  322. ddr_pll_bypass_ti816x();
  323. /* Enable uart0-2 */
  324. writel(PRCM_MOD_EN, &cmalwon->uart0clkctrl);
  325. while (readl(&cmalwon->uart0clkctrl) != PRCM_MOD_EN)
  326. ;
  327. writel(PRCM_MOD_EN, &cmalwon->uart1clkctrl);
  328. while (readl(&cmalwon->uart1clkctrl) != PRCM_MOD_EN)
  329. ;
  330. writel(PRCM_MOD_EN, &cmalwon->uart2clkctrl);
  331. while (readl(&cmalwon->uart2clkctrl) != PRCM_MOD_EN)
  332. ;
  333. while ((readl(&cmalwon->l3slowclkstctrl) & 0x2100) != 0x2100)
  334. ;
  335. }
  336. void setup_early_clocks(void)
  337. {
  338. setup_clocks_for_console();
  339. }
  340. void prcm_init(void)
  341. {
  342. /* Enable the control */
  343. writel(PRCM_MOD_EN, &cmalwon->controlclkctrl);
  344. main_pll_init_ti816x();
  345. ddr_pll_init_ti816x();
  346. /*
  347. * With clk freqs setup to desired values,
  348. * enable the required peripherals
  349. */
  350. peripheral_enable();
  351. }