init.c 2.4 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright (C) 2018 MediaTek Inc.
  4. * Author: Ryder Lee <ryder.lee@mediatek.com>
  5. */
  6. #include <clk.h>
  7. #include <common.h>
  8. #include <dm.h>
  9. #include <fdtdec.h>
  10. #include <init.h>
  11. #include <log.h>
  12. #include <ram.h>
  13. #include <asm/arch/misc.h>
  14. #include <asm/sections.h>
  15. #include <dm/uclass.h>
  16. #include <linux/bitops.h>
  17. #include <linux/io.h>
  18. #include <dt-bindings/clock/mt7629-clk.h>
  19. #define L2_CFG_BASE 0x10200000
  20. #define L2_CFG_SIZE 0x1000
  21. #define L2_SHARE_CFG_MP0 0x7f0
  22. #define L2_SHARE_MODE_OFF BIT(8)
  23. DECLARE_GLOBAL_DATA_PTR;
  24. int mtk_pll_early_init(void)
  25. {
  26. unsigned long pll_rates[] = {
  27. [CLK_APMIXED_ARMPLL] = 1250000000,
  28. [CLK_APMIXED_MAINPLL] = 1120000000,
  29. [CLK_APMIXED_UNIV2PLL] = 1200000000,
  30. [CLK_APMIXED_ETH1PLL] = 500000000,
  31. [CLK_APMIXED_ETH2PLL] = 700000000,
  32. [CLK_APMIXED_SGMIPLL] = 650000000,
  33. };
  34. struct udevice *dev;
  35. int ret, i;
  36. ret = uclass_get_device_by_driver(UCLASS_CLK,
  37. DM_GET_DRIVER(mtk_clk_apmixedsys), &dev);
  38. if (ret)
  39. return ret;
  40. /* configure default rate then enable apmixedsys */
  41. for (i = 0; i < ARRAY_SIZE(pll_rates); i++) {
  42. struct clk clk = { .id = i, .dev = dev };
  43. ret = clk_set_rate(&clk, pll_rates[i]);
  44. if (ret)
  45. return ret;
  46. ret = clk_enable(&clk);
  47. if (ret)
  48. return ret;
  49. }
  50. /* setup mcu bus */
  51. ret = uclass_get_device_by_driver(UCLASS_SYSCON,
  52. DM_GET_DRIVER(mtk_mcucfg), &dev);
  53. if (ret)
  54. return ret;
  55. return 0;
  56. }
  57. int mtk_soc_early_init(void)
  58. {
  59. struct udevice *dev;
  60. int ret;
  61. /* initialize early clocks */
  62. ret = mtk_pll_early_init();
  63. if (ret)
  64. return ret;
  65. ret = uclass_first_device_err(UCLASS_RAM, &dev);
  66. if (ret)
  67. return ret;
  68. return 0;
  69. }
  70. int mach_cpu_init(void)
  71. {
  72. void __iomem *base;
  73. base = ioremap(L2_CFG_BASE, L2_CFG_SIZE);
  74. /* disable L2C shared mode */
  75. writel(L2_SHARE_MODE_OFF, base + L2_SHARE_CFG_MP0);
  76. return 0;
  77. }
  78. int dram_init(void)
  79. {
  80. struct ram_info ram;
  81. struct udevice *dev;
  82. int ret;
  83. ret = uclass_first_device_err(UCLASS_RAM, &dev);
  84. if (ret)
  85. return ret;
  86. ret = ram_get_info(dev, &ram);
  87. if (ret)
  88. return ret;
  89. debug("RAM init base=%lx, size=%x\n", ram.base, ram.size);
  90. gd->ram_size = ram.size;
  91. return 0;
  92. }
  93. int print_cpuinfo(void)
  94. {
  95. void __iomem *chipid;
  96. u32 hwcode, swver;
  97. chipid = ioremap(VER_BASE, VER_SIZE);
  98. hwcode = readl(chipid + APHW_CODE);
  99. swver = readl(chipid + APSW_VER);
  100. printf("CPU: MediaTek MT%04x E%d\n", hwcode, (swver & 0xf) + 1);
  101. return 0;
  102. }