hardware-k2l.h 3.1 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * K2L: SoC definitions
  4. *
  5. * (C) Copyright 2012-2014
  6. * Texas Instruments Incorporated, <www.ti.com>
  7. */
  8. #ifndef __ASM_ARCH_HARDWARE_K2L_H
  9. #define __ASM_ARCH_HARDWARE_K2L_H
  10. #ifndef __ASSEMBLY__
  11. #include <linux/bitops.h>
  12. #endif
  13. #define KS2_ARM_PLL_EN BIT(13)
  14. /* PA SS Registers */
  15. #define KS2_PASS_BASE 0x26000000
  16. /* Power and Sleep Controller (PSC) Domains */
  17. #define KS2_LPSC_MOD 0
  18. #define KS2_LPSC_DFE_IQN_SYS 1
  19. #define KS2_LPSC_USB 2
  20. #define KS2_LPSC_EMIF25_SPI 3
  21. #define KS2_LPSC_TSIP 4
  22. #define KS2_LPSC_DEBUGSS_TRC 5
  23. #define KS2_LPSC_TETB_TRC 6
  24. #define KS2_LPSC_PKTPROC 7
  25. #define KS2_LPSC_PA KS2_LPSC_PKTPROC
  26. #define KS2_LPSC_SGMII 8
  27. #define KS2_LPSC_CPGMAC KS2_LPSC_SGMII
  28. #define KS2_LPSC_CRYPTO 9
  29. #define KS2_LPSC_PCIE0 10
  30. #define KS2_LPSC_PCIE1 11
  31. #define KS2_LPSC_JESD_MISC 12
  32. #define KS2_LPSC_CHIP_SRSS 13
  33. #define KS2_LPSC_MSMC 14
  34. #define KS2_LPSC_GEM_1 16
  35. #define KS2_LPSC_GEM_2 17
  36. #define KS2_LPSC_GEM_3 18
  37. #define KS2_LPSC_EMIF4F_DDR3 23
  38. #define KS2_LPSC_TAC 25
  39. #define KS2_LPSC_RAC 26
  40. #define KS2_LPSC_DDUC4X_CFR2X_BB 27
  41. #define KS2_LPSC_FFTC_A 28
  42. #define KS2_LPSC_OSR 34
  43. #define KS2_LPSC_TCP3D_0 35
  44. #define KS2_LPSC_TCP3D_1 37
  45. #define KS2_LPSC_VCP2X4_A 39
  46. #define KS2_LPSC_VCP2X4_B 40
  47. #define KS2_LPSC_VCP2X4_C 41
  48. #define KS2_LPSC_VCP2X4_D 42
  49. #define KS2_LPSC_BCP 47
  50. #define KS2_LPSC_DPD4X 48
  51. #define KS2_LPSC_FFTC_B 49
  52. #define KS2_LPSC_IQN_AIL 50
  53. /* Chip Interrupt Controller */
  54. #define KS2_CIC2_DDR3_ECC_IRQ_NUM 0x0D3
  55. #define KS2_CIC2_DDR3_ECC_CHAN_NUM 0x01D
  56. /* OSR */
  57. #define KS2_OSR_DATA_BASE 0x70000000 /* OSR data base */
  58. #define KS2_OSR_CFG_BASE 0x02348c00 /* OSR config base */
  59. #define KS2_OSR_ECC_VEC 0x08 /* ECC Vector reg */
  60. #define KS2_OSR_ECC_CTRL 0x14 /* ECC control reg */
  61. /* OSR ECC Vector register */
  62. #define KS2_OSR_ECC_VEC_TRIG_RD BIT(15) /* trigger a read op */
  63. #define KS2_OSR_ECC_VEC_RD_DONE BIT(24) /* read complete */
  64. #define KS2_OSR_ECC_VEC_RAM_ID_SH 0 /* RAM ID shift */
  65. #define KS2_OSR_ECC_VEC_RD_ADDR_SH 16 /* read address shift */
  66. /* OSR ECC control register */
  67. #define KS2_OSR_ECC_CTRL_EN BIT(0) /* ECC enable bit */
  68. #define KS2_OSR_ECC_CTRL_CHK BIT(1) /* ECC check bit */
  69. #define KS2_OSR_ECC_CTRL_RMW BIT(2) /* ECC check bit */
  70. /* Number of OSR RAM banks */
  71. #define KS2_OSR_NUM_RAM_BANKS 4
  72. /* OSR memory size */
  73. #define KS2_OSR_SIZE 0x100000
  74. /* SGMII SerDes */
  75. #define KS2_SGMII_SERDES2_BASE 0x02320000
  76. #define KS2_LANES_PER_SGMII_SERDES 2
  77. /* Number of DSP cores */
  78. #define KS2_NUM_DSPS 4
  79. /* NETCP pktdma */
  80. #define KS2_NETCP_PDMA_CTRL_BASE 0x26186000
  81. #define KS2_NETCP_PDMA_TX_BASE 0x26187000
  82. #define KS2_NETCP_PDMA_TX_CH_NUM 21
  83. #define KS2_NETCP_PDMA_RX_BASE 0x26188000
  84. #define KS2_NETCP_PDMA_RX_CH_NUM 91
  85. #define KS2_NETCP_PDMA_SCHED_BASE 0x26186100
  86. #define KS2_NETCP_PDMA_RX_FLOW_BASE 0x26189000
  87. #define KS2_NETCP_PDMA_RX_FLOW_NUM 96
  88. #define KS2_NETCP_PDMA_TX_SND_QUEUE 896
  89. /* NETCP */
  90. #define KS2_NETCP_BASE 0x26000000
  91. #ifndef __ASSEMBLY__
  92. static inline int ddr3_get_size(void)
  93. {
  94. return 2;
  95. }
  96. #endif
  97. #endif /* __ASM_ARCH_HARDWARE_K2L_H */