flow.h 1.6 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * (C) Copyright 2010-2013
  4. * NVIDIA Corporation <www.nvidia.com>
  5. */
  6. #ifndef _TEGRA124_FLOW_H_
  7. #define _TEGRA124_FLOW_H_
  8. #ifndef __ASSEMBLY__
  9. #include <linux/bitops.h>
  10. #endif
  11. struct flow_ctlr {
  12. u32 halt_cpu_events; /* offset 0x00 */
  13. u32 halt_cop_events; /* offset 0x04 */
  14. u32 cpu_csr; /* offset 0x08 */
  15. u32 cop_csr; /* offset 0x0c */
  16. u32 xrq_events; /* offset 0x10 */
  17. u32 halt_cpu1_events; /* offset 0x14 */
  18. u32 cpu1_csr; /* offset 0x18 */
  19. u32 halt_cpu2_events; /* offset 0x1c */
  20. u32 cpu2_csr; /* offset 0x20 */
  21. u32 halt_cpu3_events; /* offset 0x24 */
  22. u32 cpu3_csr; /* offset 0x28 */
  23. u32 cluster_control; /* offset 0x2c */
  24. u32 halt_cop1_events; /* offset 0x30 */
  25. u32 halt_cop1_csr; /* offset 0x34 */
  26. u32 cpu_pwr_csr; /* offset 0x38 */
  27. u32 mpid; /* offset 0x3c */
  28. u32 ram_repair; /* offset 0x40 */
  29. u32 flow_dbg_sel; /* offset 0x44 */
  30. u32 flow_dbg_cnt0; /* offset 0x48 */
  31. u32 flow_dbg_cnt1; /* offset 0x4c */
  32. u32 flow_dbg_qual; /* offset 0x50 */
  33. u32 flow_ctrl_spare; /* offset 0x54 */
  34. u32 ram_repair_cluster1;/* offset 0x58 */
  35. };
  36. /* HALT_COP_EVENTS_0, 0x04 */
  37. #define EVENT_MSEC (1 << 24)
  38. #define EVENT_USEC (1 << 25)
  39. #define EVENT_JTAG (1 << 28)
  40. #define EVENT_MODE_STOP (2 << 29)
  41. /* FLOW_CTLR_CLUSTER_CONTROL_0 0x2c */
  42. #define ACTIVE_LP (1 << 0)
  43. /* CPUn_CSR_0 */
  44. #define CSR_ENABLE (1 << 0)
  45. #define CSR_IMMEDIATE_WAKE (1 << 3)
  46. #define CSR_WAIT_WFI_SHIFT 8
  47. #define CSR_PWR_OFF_STS (1 << 16)
  48. #define RAM_REPAIR_REQ BIT(0)
  49. #define RAM_REPAIR_STS BIT(1)
  50. #define RAM_REPAIR_BYPASS_EN BIT(2)
  51. #endif /* _TEGRA124_FLOW_H_ */