grf_rk3368.h 2.7 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * (C) Copyright 2016 Rockchip Electronics Co., Ltd
  4. * (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH
  5. */
  6. #ifndef _ASM_ARCH_GRF_RK3368_H
  7. #define _ASM_ARCH_GRF_RK3368_H
  8. #ifndef __ASSEMBLY__
  9. #include <linux/bitops.h>
  10. #endif
  11. struct rk3368_grf {
  12. u32 gpio1a_iomux;
  13. u32 gpio1b_iomux;
  14. u32 gpio1c_iomux;
  15. u32 gpio1d_iomux;
  16. u32 gpio2a_iomux;
  17. u32 gpio2b_iomux;
  18. u32 gpio2c_iomux;
  19. u32 gpio2d_iomux;
  20. u32 gpio3a_iomux;
  21. u32 gpio3b_iomux;
  22. u32 gpio3c_iomux;
  23. u32 gpio3d_iomux;
  24. u32 reserved[0x34];
  25. u32 gpio1a_pull;
  26. u32 gpio1b_pull;
  27. u32 gpio1c_pull;
  28. u32 gpio1d_pull;
  29. u32 gpio2a_pull;
  30. u32 gpio2b_pull;
  31. u32 gpio2c_pull;
  32. u32 gpio2d_pull;
  33. u32 gpio3a_pull;
  34. u32 gpio3b_pull;
  35. u32 gpio3c_pull;
  36. u32 gpio3d_pull;
  37. u32 reserved1[0x34];
  38. u32 gpio1a_drv;
  39. u32 gpio1b_drv;
  40. u32 gpio1c_drv;
  41. u32 gpio1d_drv;
  42. u32 gpio2a_drv;
  43. u32 gpio2b_drv;
  44. u32 gpio2c_drv;
  45. u32 gpio2d_drv;
  46. u32 gpio3a_drv;
  47. u32 gpio3b_drv;
  48. u32 gpio3c_drv;
  49. u32 gpio3d_drv;
  50. u32 reserved2[0x34];
  51. u32 gpio1l_sr;
  52. u32 gpio1h_sr;
  53. u32 gpio2l_sr;
  54. u32 gpio2h_sr;
  55. u32 gpio3l_sr;
  56. u32 gpio3h_sr;
  57. u32 reserved3[0x1a];
  58. u32 gpio_smt;
  59. u32 reserved4[0x1f];
  60. u32 soc_con0;
  61. u32 soc_con1;
  62. u32 soc_con2;
  63. u32 soc_con3;
  64. u32 soc_con4;
  65. u32 soc_con5;
  66. u32 soc_con6;
  67. u32 soc_con7;
  68. u32 soc_con8;
  69. u32 soc_con9;
  70. u32 soc_con10;
  71. u32 soc_con11;
  72. u32 soc_con12;
  73. u32 soc_con13;
  74. u32 soc_con14;
  75. u32 soc_con15;
  76. u32 soc_con16;
  77. u32 soc_con17;
  78. u32 reserved5[0x6e];
  79. u32 ddrc0_con0;
  80. };
  81. check_member(rk3368_grf, soc_con17, 0x444);
  82. check_member(rk3368_grf, ddrc0_con0, 0x600);
  83. struct rk3368_pmu_grf {
  84. u32 gpio0a_iomux;
  85. u32 gpio0b_iomux;
  86. u32 gpio0c_iomux;
  87. u32 gpio0d_iomux;
  88. u32 gpio0a_pull;
  89. u32 gpio0b_pull;
  90. u32 gpio0c_pull;
  91. u32 gpio0d_pull;
  92. u32 gpio0a_drv;
  93. u32 gpio0b_drv;
  94. u32 gpio0c_drv;
  95. u32 gpio0d_drv;
  96. u32 gpio0l_sr;
  97. u32 gpio0h_sr;
  98. u32 reserved[0x72];
  99. u32 os_reg[4];
  100. };
  101. check_member(rk3368_pmu_grf, gpio0h_sr, 0x34);
  102. check_member(rk3368_pmu_grf, os_reg[0], 0x200);
  103. /*GRF_SOC_CON11/12/13*/
  104. enum {
  105. MCU_SRAM_BASE_BIT27_BIT12_SHIFT = 0,
  106. MCU_SRAM_BASE_BIT27_BIT12_MASK = GENMASK(15, 0),
  107. };
  108. /*GRF_SOC_CON12*/
  109. enum {
  110. MCU_EXSRAM_BASE_BIT27_BIT12_SHIFT = 0,
  111. MCU_EXSRAM_BASE_BIT27_BIT12_MASK = GENMASK(15, 0),
  112. };
  113. /*GRF_SOC_CON13*/
  114. enum {
  115. MCU_EXPERI_BASE_BIT27_BIT12_SHIFT = 0,
  116. MCU_EXPERI_BASE_BIT27_BIT12_MASK = GENMASK(15, 0),
  117. };
  118. /*GRF_SOC_CON14*/
  119. enum {
  120. MCU_EXPERI_BASE_BIT31_BIT28_SHIFT = 12,
  121. MCU_EXPERI_BASE_BIT31_BIT28_MASK = GENMASK(15, 12),
  122. MCU_EXSRAM_BASE_BIT31_BIT28_SHIFT = 8,
  123. MCU_EXSRAM_BASE_BIT31_BIT28_MASK = GENMASK(11, 8),
  124. MCU_SRAM_BASE_BIT31_BIT28_SHIFT = 4,
  125. MCU_SRAM_BASE_BIT31_BIT28_MASK = GENMASK(7, 4),
  126. MCU_CODE_BASE_BIT31_BIT28_SHIFT = 0,
  127. MCU_CODE_BASE_BIT31_BIT28_MASK = GENMASK(3, 0),
  128. };
  129. #endif