g12a.h 2.2 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright (C) 2018 BayLibre, SAS
  4. * Author: Neil Armstrong <narmstrong@baylibre.com>
  5. */
  6. #ifndef __G12A_H__
  7. #define __G12A_H__
  8. #ifndef __ASSEMBLY__
  9. #include <linux/bitops.h>
  10. #endif
  11. #define G12A_AOBUS_BASE 0xff800000
  12. #define G12A_PERIPHS_BASE 0xff634400
  13. #define G12A_HIU_BASE 0xff63c000
  14. #define G12A_ETH_PHY_BASE 0xff64c000
  15. #define G12A_ETH_BASE 0xff3f0000
  16. /* Always-On Peripherals registers */
  17. #define G12A_AO_ADDR(off) (G12A_AOBUS_BASE + ((off) << 2))
  18. #define G12A_AO_SEC_GP_CFG0 G12A_AO_ADDR(0x90)
  19. #define G12A_AO_SEC_GP_CFG3 G12A_AO_ADDR(0x93)
  20. #define G12A_AO_SEC_GP_CFG4 G12A_AO_ADDR(0x94)
  21. #define G12A_AO_SEC_GP_CFG5 G12A_AO_ADDR(0x95)
  22. #define G12A_AO_BOOT_DEVICE 0xF
  23. #define G12A_AO_MEM_SIZE_MASK 0xFFFF0000
  24. #define G12A_AO_MEM_SIZE_SHIFT 16
  25. #define G12A_AO_BL31_RSVMEM_SIZE_MASK 0xFFFF0000
  26. #define G12A_AO_BL31_RSVMEM_SIZE_SHIFT 16
  27. #define G12A_AO_BL32_RSVMEM_SIZE_MASK 0xFFFF
  28. /* Peripherals registers */
  29. #define G12A_PERIPHS_ADDR(off) (G12A_PERIPHS_BASE + ((off) << 2))
  30. #define G12A_ETH_REG_0 G12A_PERIPHS_ADDR(0x50)
  31. #define G12A_ETH_REG_1 G12A_PERIPHS_ADDR(0x51)
  32. #define G12A_ETH_REG_0_PHY_INTF_RGMII BIT(0)
  33. #define G12A_ETH_REG_0_PHY_INTF_RMII BIT(2)
  34. #define G12A_ETH_REG_0_TX_PHASE(x) (((x) & 3) << 5)
  35. #define G12A_ETH_REG_0_TX_RATIO(x) (((x) & 7) << 7)
  36. #define G12A_ETH_REG_0_PHY_CLK_EN BIT(10)
  37. #define G12A_ETH_REG_0_INVERT_RMII_CLK BIT(11)
  38. #define G12A_ETH_REG_0_CLK_EN BIT(12)
  39. #define G12A_ETH_PHY_ADDR(off) (G12A_ETH_PHY_BASE + ((off) << 2))
  40. #define ETH_PLL_CNTL0 G12A_ETH_PHY_ADDR(0x11)
  41. #define ETH_PLL_CNTL1 G12A_ETH_PHY_ADDR(0x12)
  42. #define ETH_PLL_CNTL2 G12A_ETH_PHY_ADDR(0x13)
  43. #define ETH_PLL_CNTL3 G12A_ETH_PHY_ADDR(0x14)
  44. #define ETH_PLL_CNTL4 G12A_ETH_PHY_ADDR(0x15)
  45. #define ETH_PLL_CNTL5 G12A_ETH_PHY_ADDR(0x16)
  46. #define ETH_PLL_CNTL6 G12A_ETH_PHY_ADDR(0x17)
  47. #define ETH_PLL_CNTL7 G12A_ETH_PHY_ADDR(0x18)
  48. #define ETH_PHY_CNTL0 G12A_ETH_PHY_ADDR(0x20)
  49. #define ETH_PHY_CNTL1 G12A_ETH_PHY_ADDR(0x21)
  50. #define ETH_PHY_CNTL2 G12A_ETH_PHY_ADDR(0x22)
  51. /* HIU registers */
  52. #define G12A_HIU_ADDR(off) (G12A_HIU_BASE + ((off) << 2))
  53. #define G12A_MEM_PD_REG_0 G12A_HIU_ADDR(0x40)
  54. /* Ethernet memory power domain */
  55. #define G12A_MEM_PD_REG_0_ETH_MASK (BIT(2) | BIT(3))
  56. #endif /* __G12A_H__ */