axg.h 1.6 KB

1234567891011121314151617181920212223242526272829303132333435363738394041424344454647484950515253545556
  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright (C) 2018 BayLibre, SAS
  4. * Author: Neil Armstrong <narmstrong@baylibre.com>
  5. */
  6. #ifndef __AXG_H__
  7. #define __AXG_H__
  8. #ifndef __ASSEMBLY__
  9. #include <linux/bitops.h>
  10. #endif
  11. #define AXG_AOBUS_BASE 0xff800000
  12. #define AXG_PERIPHS_BASE 0xff634400
  13. #define AXG_HIU_BASE 0xff63c000
  14. #define AXG_ETH_BASE 0xff3f0000
  15. /* Always-On Peripherals registers */
  16. #define AXG_AO_ADDR(off) (AXG_AOBUS_BASE + ((off) << 2))
  17. #define AXG_AO_SEC_GP_CFG0 AXG_AO_ADDR(0x90)
  18. #define AXG_AO_SEC_GP_CFG3 AXG_AO_ADDR(0x93)
  19. #define AXG_AO_SEC_GP_CFG4 AXG_AO_ADDR(0x94)
  20. #define AXG_AO_SEC_GP_CFG5 AXG_AO_ADDR(0x95)
  21. #define AXG_AO_BOOT_DEVICE 0xF
  22. #define AXG_AO_MEM_SIZE_MASK 0xFFFF0000
  23. #define AXG_AO_MEM_SIZE_SHIFT 16
  24. #define AXG_AO_BL31_RSVMEM_SIZE_MASK 0xFFFF0000
  25. #define AXG_AO_BL31_RSVMEM_SIZE_SHIFT 16
  26. #define AXG_AO_BL32_RSVMEM_SIZE_MASK 0xFFFF
  27. /* Peripherals registers */
  28. #define AXG_PERIPHS_ADDR(off) (AXG_PERIPHS_BASE + ((off) << 2))
  29. #define AXG_ETH_REG_0 AXG_PERIPHS_ADDR(0x50)
  30. #define AXG_ETH_REG_1 AXG_PERIPHS_ADDR(0x51)
  31. #define AXG_ETH_REG_0_PHY_INTF_RGMII BIT(0)
  32. #define AXG_ETH_REG_0_PHY_INTF_RMII BIT(2)
  33. #define AXG_ETH_REG_0_TX_PHASE(x) (((x) & 3) << 5)
  34. #define AXG_ETH_REG_0_TX_RATIO(x) (((x) & 7) << 7)
  35. #define AXG_ETH_REG_0_PHY_CLK_EN BIT(10)
  36. #define AXG_ETH_REG_0_INVERT_RMII_CLK BIT(11)
  37. #define AXG_ETH_REG_0_CLK_EN BIT(12)
  38. /* HIU registers */
  39. #define AXG_HIU_ADDR(off) (AXG_HIU_BASE + ((off) << 2))
  40. #define AXG_MEM_PD_REG_0 AXG_HIU_ADDR(0x40)
  41. /* Ethernet memory power domain */
  42. #define AXG_MEM_PD_REG_0_ETH_MASK (BIT(2) | BIT(3))
  43. #endif /* __AXG_H__ */