immap_lsch2.h 24 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright 2013-2015 Freescale Semiconductor, Inc.
  4. */
  5. #ifndef __ARCH_FSL_LSCH2_IMMAP_H__
  6. #define __ARCH_FSL_LSCH2_IMMAP_H__
  7. #include <fsl_immap.h>
  8. #ifndef __ASSEMBLY__
  9. #include <linux/bitops.h>
  10. #endif
  11. #define CONFIG_SYS_IMMR 0x01000000
  12. #define CONFIG_SYS_DCSRBAR 0x20000000
  13. #define CONFIG_SYS_DCSR_DCFG_ADDR (CONFIG_SYS_DCSRBAR + 0x00140000)
  14. #define CONFIG_SYS_DCSR_COP_CCP_ADDR (CONFIG_SYS_DCSRBAR + 0x02008040)
  15. #define CONFIG_SYS_FSL_DDR_ADDR (CONFIG_SYS_IMMR + 0x00080000)
  16. #define CONFIG_SYS_GIC400_ADDR (CONFIG_SYS_IMMR + 0x00400000)
  17. #define CONFIG_SYS_IFC_ADDR (CONFIG_SYS_IMMR + 0x00530000)
  18. #define SYS_FSL_QSPI_ADDR (CONFIG_SYS_IMMR + 0x00550000)
  19. #define CONFIG_SYS_FSL_ESDHC_ADDR (CONFIG_SYS_IMMR + 0x00560000)
  20. #define CONFIG_SYS_FSL_CSU_ADDR (CONFIG_SYS_IMMR + 0x00510000)
  21. #define CONFIG_SYS_FSL_GUTS_ADDR (CONFIG_SYS_IMMR + 0x00ee0000)
  22. #define CONFIG_SYS_FSL_RST_ADDR (CONFIG_SYS_IMMR + 0x00ee00b0)
  23. #define CONFIG_SYS_FSL_SCFG_ADDR (CONFIG_SYS_IMMR + 0x00570000)
  24. #define CONFIG_SYS_FSL_BMAN_ADDR (CONFIG_SYS_IMMR + 0x00890000)
  25. #define CONFIG_SYS_FSL_QMAN_ADDR (CONFIG_SYS_IMMR + 0x00880000)
  26. #define CONFIG_SYS_FSL_FMAN_ADDR (CONFIG_SYS_IMMR + 0x00a00000)
  27. #define CONFIG_SYS_FSL_SERDES_ADDR (CONFIG_SYS_IMMR + 0x00ea0000)
  28. #define CONFIG_SYS_FSL_DCFG_ADDR (CONFIG_SYS_IMMR + 0x00ee0000)
  29. #define CONFIG_SYS_FSL_CLK_ADDR (CONFIG_SYS_IMMR + 0x00ee1000)
  30. #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x011c0500)
  31. #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x011c0600)
  32. #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_IMMR + 0x011d0500)
  33. #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_IMMR + 0x011d0600)
  34. #define CONFIG_SYS_XHCI_USB1_ADDR (CONFIG_SYS_IMMR + 0x01f00000)
  35. #define CONFIG_SYS_XHCI_USB2_ADDR (CONFIG_SYS_IMMR + 0x02000000)
  36. #define CONFIG_SYS_XHCI_USB3_ADDR (CONFIG_SYS_IMMR + 0x02100000)
  37. #define CONFIG_SYS_EHCI_USB1_ADDR (CONFIG_SYS_IMMR + 0x07600000)
  38. #define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_IMMR + 0x2400000)
  39. #define CONFIG_SYS_PCIE2_ADDR (CONFIG_SYS_IMMR + 0x2500000)
  40. #define CONFIG_SYS_PCIE3_ADDR (CONFIG_SYS_IMMR + 0x2600000)
  41. #define CONFIG_SYS_SEC_MON_ADDR (CONFIG_SYS_IMMR + 0xe90000)
  42. #define CONFIG_SYS_SFP_ADDR (CONFIG_SYS_IMMR + 0xe80200)
  43. #define CONFIG_SYS_BMAN_NUM_PORTALS 10
  44. #define CONFIG_SYS_BMAN_MEM_BASE 0x508000000
  45. #define CONFIG_SYS_BMAN_MEM_PHYS (0xf00000000ull + \
  46. CONFIG_SYS_BMAN_MEM_BASE)
  47. #define CONFIG_SYS_BMAN_MEM_SIZE 0x08000000
  48. #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x10000
  49. #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x10000
  50. #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE
  51. #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
  52. #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \
  53. CONFIG_SYS_BMAN_CENA_SIZE)
  54. #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
  55. #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0x3E80
  56. #define CONFIG_SYS_QMAN_NUM_PORTALS 10
  57. #define CONFIG_SYS_QMAN_MEM_BASE 0x500000000
  58. #define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE
  59. #define CONFIG_SYS_QMAN_MEM_SIZE 0x08000000
  60. #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x10000
  61. #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x10000
  62. #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE
  63. #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
  64. #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \
  65. CONFIG_SYS_QMAN_CENA_SIZE)
  66. #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
  67. #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0x3680
  68. #define CONFIG_SYS_FSL_TIMER_ADDR 0x02b00000
  69. #define I2C1_BASE_ADDR (CONFIG_SYS_IMMR + 0x01180000)
  70. #define I2C2_BASE_ADDR (CONFIG_SYS_IMMR + 0x01190000)
  71. #define I2C3_BASE_ADDR (CONFIG_SYS_IMMR + 0x011a0000)
  72. #define I2C4_BASE_ADDR (CONFIG_SYS_IMMR + 0x011b0000)
  73. #define WDOG1_BASE_ADDR (CONFIG_SYS_IMMR + 0x01ad0000)
  74. #define QSPI0_BASE_ADDR (CONFIG_SYS_IMMR + 0x00550000)
  75. #define DSPI1_BASE_ADDR (CONFIG_SYS_IMMR + 0x01100000)
  76. #define GPIO1_BASE_ADDR (CONFIG_SYS_IMMR + 0x1300000)
  77. #define GPIO2_BASE_ADDR (CONFIG_SYS_IMMR + 0x1310000)
  78. #define GPIO3_BASE_ADDR (CONFIG_SYS_IMMR + 0x1320000)
  79. #define GPIO4_BASE_ADDR (CONFIG_SYS_IMMR + 0x1330000)
  80. #define QE_BASE_ADDR (CONFIG_SYS_IMMR + 0x1400000)
  81. #define LPUART_BASE (CONFIG_SYS_IMMR + 0x01950000)
  82. #define EDMA_BASE_ADDR (CONFIG_SYS_IMMR + 0x01c00000)
  83. #define AHCI_BASE_ADDR (CONFIG_SYS_IMMR + 0x02200000)
  84. #define QDMA_BASE_ADDR (CONFIG_SYS_IMMR + 0x07380000)
  85. #define QMAN_CQSIDR_REG 0x20a80
  86. #define CONFIG_SYS_PCIE1_PHYS_ADDR 0x4000000000ULL
  87. #define CONFIG_SYS_PCIE2_PHYS_ADDR 0x4800000000ULL
  88. #define CONFIG_SYS_PCIE3_PHYS_ADDR 0x5000000000ULL
  89. /* LUT registers */
  90. #ifdef CONFIG_ARCH_LS1012A
  91. #define PCIE_LUT_BASE 0xC0000
  92. #else
  93. #define PCIE_LUT_BASE 0x10000
  94. #endif
  95. #define PCIE_LUT_LCTRL0 0x7F8
  96. #define PCIE_LUT_DBG 0x7FC
  97. /* TZ Address Space Controller Definitions */
  98. #define TZASC1_BASE 0x01100000 /* as per CCSR map. */
  99. #define TZASC2_BASE 0x01110000 /* as per CCSR map. */
  100. #define TZASC3_BASE 0x01120000 /* as per CCSR map. */
  101. #define TZASC4_BASE 0x01130000 /* as per CCSR map. */
  102. #define TZASC_BUILD_CONFIG_REG(x) ((TZASC1_BASE + (x * 0x10000)))
  103. #define TZASC_ACTION_REG(x) ((TZASC1_BASE + (x * 0x10000)) + 0x004)
  104. #define TZASC_GATE_KEEPER(x) ((TZASC1_BASE + (x * 0x10000)) + 0x008)
  105. #define TZASC_REGION_BASE_LOW_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x100)
  106. #define TZASC_REGION_BASE_HIGH_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x104)
  107. #define TZASC_REGION_TOP_LOW_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x108)
  108. #define TZASC_REGION_TOP_HIGH_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x10C)
  109. #define TZASC_REGION_ATTRIBUTES_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x110)
  110. #define TZASC_REGION_ID_ACCESS_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x114)
  111. #define TP_ITYP_AV 0x00000001 /* Initiator available */
  112. #define TP_ITYP_TYPE(x) (((x) & 0x6) >> 1) /* Initiator Type */
  113. #define TP_ITYP_TYPE_ARM 0x0
  114. #define TP_ITYP_TYPE_PPC 0x1 /* PowerPC */
  115. #define TP_ITYP_TYPE_OTHER 0x2 /* StarCore DSP */
  116. #define TP_ITYP_TYPE_HA 0x3 /* HW Accelerator */
  117. #define TP_ITYP_THDS(x) (((x) & 0x18) >> 3) /* # threads */
  118. #define TP_ITYP_VER(x) (((x) & 0xe0) >> 5) /* Initiator Version */
  119. #define TY_ITYP_VER_A7 0x1
  120. #define TY_ITYP_VER_A53 0x2
  121. #define TY_ITYP_VER_A57 0x3
  122. #define TY_ITYP_VER_A72 0x4
  123. #define TP_CLUSTER_EOC 0xc0000000 /* end of clusters */
  124. #define TP_CLUSTER_INIT_MASK 0x0000003f /* initiator mask */
  125. #define TP_INIT_PER_CLUSTER 4
  126. /*
  127. * Define default values for some CCSR macros to make header files cleaner*
  128. *
  129. * To completely disable CCSR relocation in a board header file, define
  130. * CONFIG_SYS_CCSR_DO_NOT_RELOCATE. This will force CONFIG_SYS_CCSRBAR_PHYS
  131. * to a value that is the same as CONFIG_SYS_CCSRBAR.
  132. */
  133. #ifdef CONFIG_SYS_CCSRBAR_PHYS
  134. #error "Do not define CONFIG_SYS_CCSRBAR_PHYS directly. Use \
  135. CONFIG_SYS_CCSRBAR_PHYS_LOW and/or CONFIG_SYS_CCSRBAR_PHYS_HIGH instead."
  136. #endif
  137. #ifdef CONFIG_SYS_CCSR_DO_NOT_RELOCATE
  138. #undef CONFIG_SYS_CCSRBAR_PHYS_HIGH
  139. #undef CONFIG_SYS_CCSRBAR_PHYS_LOW
  140. #define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0
  141. #endif
  142. #ifndef CONFIG_SYS_CCSRBAR
  143. #define CONFIG_SYS_CCSRBAR 0x01000000
  144. #endif
  145. #ifndef CONFIG_SYS_CCSRBAR_PHYS_HIGH
  146. #define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0
  147. #endif
  148. #ifndef CONFIG_SYS_CCSRBAR_PHYS_LOW
  149. #define CONFIG_SYS_CCSRBAR_PHYS_LOW 0x01000000
  150. #endif
  151. #define CONFIG_SYS_CCSRBAR_PHYS ((CONFIG_SYS_CCSRBAR_PHYS_HIGH * 1ull) << 32 | \
  152. CONFIG_SYS_CCSRBAR_PHYS_LOW)
  153. struct sys_info {
  154. unsigned long freq_processor[CONFIG_MAX_CPUS];
  155. /* frequency of platform PLL */
  156. unsigned long freq_systembus;
  157. unsigned long freq_ddrbus;
  158. unsigned long freq_localbus;
  159. unsigned long freq_cga_m2;
  160. #ifdef CONFIG_SYS_DPAA_FMAN
  161. unsigned long freq_fman[CONFIG_SYS_NUM_FMAN];
  162. #endif
  163. unsigned long freq_qman;
  164. };
  165. #define CONFIG_SYS_FSL_FM1_OFFSET 0xa00000
  166. #define CONFIG_SYS_FSL_FM1_RX0_1G_OFFSET 0xa88000
  167. #define CONFIG_SYS_FSL_FM1_RX1_1G_OFFSET 0xa89000
  168. #define CONFIG_SYS_FSL_FM1_RX2_1G_OFFSET 0xa8a000
  169. #define CONFIG_SYS_FSL_FM1_RX3_1G_OFFSET 0xa8b000
  170. #define CONFIG_SYS_FSL_FM1_RX4_1G_OFFSET 0xa8c000
  171. #define CONFIG_SYS_FSL_FM1_RX5_1G_OFFSET 0xa8d000
  172. #define CONFIG_SYS_FSL_FM1_DTSEC1_OFFSET 0xae0000
  173. #define CONFIG_SYS_FSL_FM1_ADDR \
  174. (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_FM1_OFFSET)
  175. #define CONFIG_SYS_FSL_FM1_DTSEC1_ADDR \
  176. (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_FM1_DTSEC1_OFFSET)
  177. #define CONFIG_SYS_FSL_SEC_OFFSET 0x700000ull
  178. #define CONFIG_SYS_FSL_JR0_OFFSET 0x710000ull
  179. #define FSL_SEC_JR0_OFFSET CONFIG_SYS_FSL_JR0_OFFSET
  180. #define FSL_SEC_JR1_OFFSET 0x720000ull
  181. #define FSL_SEC_JR2_OFFSET 0x730000ull
  182. #define FSL_SEC_JR3_OFFSET 0x740000ull
  183. #define CONFIG_SYS_FSL_SEC_ADDR \
  184. (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_SEC_OFFSET)
  185. #define CONFIG_SYS_FSL_JR0_ADDR \
  186. (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_JR0_OFFSET)
  187. #define FSL_SEC_JR0_BASE_ADDR (CONFIG_SYS_IMMR + FSL_SEC_JR0_OFFSET)
  188. #define FSL_SEC_JR1_BASE_ADDR (CONFIG_SYS_IMMR + FSL_SEC_JR1_OFFSET)
  189. #define FSL_SEC_JR2_BASE_ADDR (CONFIG_SYS_IMMR + FSL_SEC_JR2_OFFSET)
  190. #define FSL_SEC_JR3_BASE_ADDR (CONFIG_SYS_IMMR + FSL_SEC_JR3_OFFSET)
  191. /* Device Configuration and Pin Control */
  192. #define DCFG_DCSR_PORCR1 0x0
  193. #define DCFG_DCSR_ECCCR2 0x524
  194. #define DISABLE_PFE_ECC BIT(13)
  195. struct ccsr_gur {
  196. u32 porsr1; /* POR status 1 */
  197. #define FSL_CHASSIS2_CCSR_PORSR1_RCW_MASK 0xFF800000
  198. u32 porsr2; /* POR status 2 */
  199. u8 res_008[0x20-0x8];
  200. u32 gpporcr1; /* General-purpose POR configuration */
  201. u32 gpporcr2;
  202. #define FSL_CHASSIS2_DCFG_FUSESR_VID_SHIFT 25
  203. #define FSL_CHASSIS2_DCFG_FUSESR_VID_MASK 0x1F
  204. #define FSL_CHASSIS2_DCFG_FUSESR_ALTVID_SHIFT 20
  205. #define FSL_CHASSIS2_DCFG_FUSESR_ALTVID_MASK 0x1F
  206. u32 dcfg_fusesr; /* Fuse status register */
  207. u8 res_02c[0x70-0x2c];
  208. u32 devdisr; /* Device disable control */
  209. #define FSL_CHASSIS2_DEVDISR2_DTSEC1_1 0x80000000
  210. #define FSL_CHASSIS2_DEVDISR2_DTSEC1_2 0x40000000
  211. #define FSL_CHASSIS2_DEVDISR2_DTSEC1_3 0x20000000
  212. #define FSL_CHASSIS2_DEVDISR2_DTSEC1_4 0x10000000
  213. #define FSL_CHASSIS2_DEVDISR2_DTSEC1_5 0x08000000
  214. #define FSL_CHASSIS2_DEVDISR2_DTSEC1_6 0x04000000
  215. #define FSL_CHASSIS2_DEVDISR2_DTSEC1_9 0x00800000
  216. #define FSL_CHASSIS2_DEVDISR2_DTSEC1_10 0x00400000
  217. #define FSL_CHASSIS2_DEVDISR2_10GEC1_1 0x00800000
  218. #define FSL_CHASSIS2_DEVDISR2_10GEC1_2 0x00400000
  219. #define FSL_CHASSIS2_DEVDISR2_10GEC1_3 0x80000000
  220. #define FSL_CHASSIS2_DEVDISR2_10GEC1_4 0x40000000
  221. u32 devdisr2; /* Device disable control 2 */
  222. u32 devdisr3; /* Device disable control 3 */
  223. u32 devdisr4; /* Device disable control 4 */
  224. u32 devdisr5; /* Device disable control 5 */
  225. u32 devdisr6; /* Device disable control 6 */
  226. u32 devdisr7; /* Device disable control 7 */
  227. u8 res_08c[0x94-0x8c];
  228. u32 coredisru; /* uppper portion for support of 64 cores */
  229. u32 coredisrl; /* lower portion for support of 64 cores */
  230. u8 res_09c[0xa0-0x9c];
  231. u32 pvr; /* Processor version */
  232. u32 svr; /* System version */
  233. u32 mvr; /* Manufacturing version */
  234. u8 res_0ac[0xb0-0xac];
  235. u32 rstcr; /* Reset control */
  236. u32 rstrqpblsr; /* Reset request preboot loader status */
  237. u8 res_0b8[0xc0-0xb8];
  238. u32 rstrqmr1; /* Reset request mask */
  239. u8 res_0c4[0xc8-0xc4];
  240. u32 rstrqsr1; /* Reset request status */
  241. u8 res_0cc[0xd4-0xcc];
  242. u32 rstrqwdtmrl; /* Reset request WDT mask */
  243. u8 res_0d8[0xdc-0xd8];
  244. u32 rstrqwdtsrl; /* Reset request WDT status */
  245. u8 res_0e0[0xe4-0xe0];
  246. u32 brrl; /* Boot release */
  247. u8 res_0e8[0x100-0xe8];
  248. u32 rcwsr[16]; /* Reset control word status */
  249. #define FSL_CHASSIS2_RCWSR0_SYS_PLL_RAT_SHIFT 25
  250. #define FSL_CHASSIS2_RCWSR0_SYS_PLL_RAT_MASK 0x1f
  251. #define FSL_CHASSIS2_RCWSR0_MEM_PLL_RAT_SHIFT 16
  252. #define FSL_CHASSIS2_RCWSR0_MEM_PLL_RAT_MASK 0x3f
  253. #define FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK 0xffff0000
  254. #define FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT 16
  255. #define FSL_CHASSIS2_RCWSR4_SRDS2_PRTCL_MASK 0x0000ffff
  256. #define FSL_CHASSIS2_RCWSR4_SRDS2_PRTCL_SHIFT 0
  257. #define RCW_SB_EN_REG_INDEX 7
  258. #define RCW_SB_EN_MASK 0x00200000
  259. u8 res_140[0x200-0x140];
  260. u32 scratchrw[4]; /* Scratch Read/Write */
  261. u8 res_210[0x300-0x210];
  262. u32 scratchw1r[4]; /* Scratch Read (Write once) */
  263. u8 res_310[0x400-0x310];
  264. u32 crstsr[12];
  265. u8 res_430[0x500-0x430];
  266. /* PCI Express n Logical I/O Device Number register */
  267. u32 dcfg_ccsr_pex1liodnr;
  268. u32 dcfg_ccsr_pex2liodnr;
  269. u32 dcfg_ccsr_pex3liodnr;
  270. u32 dcfg_ccsr_pex4liodnr;
  271. /* RIO n Logical I/O Device Number register */
  272. u32 dcfg_ccsr_rio1liodnr;
  273. u32 dcfg_ccsr_rio2liodnr;
  274. u32 dcfg_ccsr_rio3liodnr;
  275. u32 dcfg_ccsr_rio4liodnr;
  276. /* USB Logical I/O Device Number register */
  277. u32 dcfg_ccsr_usb1liodnr;
  278. u32 dcfg_ccsr_usb2liodnr;
  279. u32 dcfg_ccsr_usb3liodnr;
  280. u32 dcfg_ccsr_usb4liodnr;
  281. /* SD/MMC Logical I/O Device Number register */
  282. u32 dcfg_ccsr_sdmmc1liodnr;
  283. u32 dcfg_ccsr_sdmmc2liodnr;
  284. u32 dcfg_ccsr_sdmmc3liodnr;
  285. u32 dcfg_ccsr_sdmmc4liodnr;
  286. /* RIO Message Unit Logical I/O Device Number register */
  287. u32 dcfg_ccsr_riomaintliodnr;
  288. u8 res_544[0x550-0x544];
  289. u32 sataliodnr[4];
  290. u8 res_560[0x570-0x560];
  291. u32 dcfg_ccsr_misc1liodnr;
  292. u32 dcfg_ccsr_misc2liodnr;
  293. u32 dcfg_ccsr_misc3liodnr;
  294. u32 dcfg_ccsr_misc4liodnr;
  295. u32 dcfg_ccsr_dma1liodnr;
  296. u32 dcfg_ccsr_dma2liodnr;
  297. u32 dcfg_ccsr_dma3liodnr;
  298. u32 dcfg_ccsr_dma4liodnr;
  299. u32 dcfg_ccsr_spare1liodnr;
  300. u32 dcfg_ccsr_spare2liodnr;
  301. u32 dcfg_ccsr_spare3liodnr;
  302. u32 dcfg_ccsr_spare4liodnr;
  303. u8 res_5a0[0x600-0x5a0];
  304. u32 dcfg_ccsr_pblsr;
  305. u32 pamubypenr;
  306. u32 dmacr1;
  307. u8 res_60c[0x610-0x60c];
  308. u32 dcfg_ccsr_gensr1;
  309. u32 dcfg_ccsr_gensr2;
  310. u32 dcfg_ccsr_gensr3;
  311. u32 dcfg_ccsr_gensr4;
  312. u32 dcfg_ccsr_gencr1;
  313. u32 dcfg_ccsr_gencr2;
  314. u32 dcfg_ccsr_gencr3;
  315. u32 dcfg_ccsr_gencr4;
  316. u32 dcfg_ccsr_gencr5;
  317. u32 dcfg_ccsr_gencr6;
  318. u32 dcfg_ccsr_gencr7;
  319. u8 res_63c[0x658-0x63c];
  320. u32 dcfg_ccsr_cgensr1;
  321. u32 dcfg_ccsr_cgensr0;
  322. u8 res_660[0x678-0x660];
  323. u32 dcfg_ccsr_cgencr1;
  324. u32 dcfg_ccsr_cgencr0;
  325. u8 res_680[0x700-0x680];
  326. u32 dcfg_ccsr_sriopstecr;
  327. u32 dcfg_ccsr_dcsrcr;
  328. u8 res_708[0x740-0x708]; /* add more registers when needed */
  329. u32 tp_ityp[64]; /* Topology Initiator Type Register */
  330. struct {
  331. u32 upper;
  332. u32 lower;
  333. } tp_cluster[16];
  334. u8 res_8c0[0xa00-0x8c0]; /* add more registers when needed */
  335. u32 dcfg_ccsr_qmbm_warmrst;
  336. u8 res_a04[0xa20-0xa04]; /* add more registers when needed */
  337. u32 dcfg_ccsr_reserved0;
  338. u32 dcfg_ccsr_reserved1;
  339. };
  340. #define SCFG_QSPI_CLKSEL 0x40100000
  341. #define SCFG_USBDRVVBUS_SELCR_USB1 0x00000000
  342. #define SCFG_USBDRVVBUS_SELCR_USB2 0x00000001
  343. #define SCFG_USBDRVVBUS_SELCR_USB3 0x00000002
  344. #define SCFG_USBPWRFAULT_INACTIVE 0x00000000
  345. #define SCFG_USBPWRFAULT_SHARED 0x00000001
  346. #define SCFG_USBPWRFAULT_DEDICATED 0x00000002
  347. #define SCFG_USBPWRFAULT_USB3_SHIFT 4
  348. #define SCFG_USBPWRFAULT_USB2_SHIFT 2
  349. #define SCFG_USBPWRFAULT_USB1_SHIFT 0
  350. #define SCFG_BASE 0x01570000
  351. #define SCFG_USB3PRM1CR_USB1 0x070
  352. #define SCFG_USB3PRM2CR_USB1 0x074
  353. #define SCFG_USB3PRM1CR_USB2 0x07C
  354. #define SCFG_USB3PRM2CR_USB2 0x080
  355. #define SCFG_USB3PRM1CR_USB3 0x088
  356. #define SCFG_USB3PRM2CR_USB3 0x08c
  357. #define SCFG_USB_TXVREFTUNE 0x9
  358. #define SCFG_USB_SQRXTUNE_MASK 0x7
  359. #define SCFG_USB_PCSTXSWINGFULL 0x47
  360. #define SCFG_USB_PHY1 0x084F0000
  361. #define SCFG_USB_PHY2 0x08500000
  362. #define SCFG_USB_PHY3 0x08510000
  363. #define SCFG_USB_PHY_RX_OVRD_IN_HI 0x200c
  364. #define USB_PHY_RX_EQ_VAL_1 0x0000
  365. #define USB_PHY_RX_EQ_VAL_2 0x0080
  366. #define USB_PHY_RX_EQ_VAL_3 0x0380
  367. #define USB_PHY_RX_EQ_VAL_4 0x0b80
  368. #define SCFG_SNPCNFGCR_SECRDSNP 0x80000000
  369. #define SCFG_SNPCNFGCR_SECWRSNP 0x40000000
  370. #define SCFG_SNPCNFGCR_SATARDSNP 0x00800000
  371. #define SCFG_SNPCNFGCR_SATAWRSNP 0x00400000
  372. #define SCFG_SNPCNFGCR_USB1RDSNP 0x00200000
  373. #define SCFG_SNPCNFGCR_USB1WRSNP 0x00100000
  374. #define SCFG_SNPCNFGCR_USB2RDSNP 0x00008000
  375. #define SCFG_SNPCNFGCR_USB2WRSNP 0x00010000
  376. #define SCFG_SNPCNFGCR_USB3RDSNP 0x00002000
  377. #define SCFG_SNPCNFGCR_USB3WRSNP 0x00004000
  378. /* RGMIIPCR bit definitions*/
  379. #define SCFG_RGMIIPCR_EN_AUTO BIT(3)
  380. #define SCFG_RGMIIPCR_SETSP_1000M BIT(2)
  381. #define SCFG_RGMIIPCR_SETSP_100M 0
  382. #define SCFG_RGMIIPCR_SETSP_10M BIT(1)
  383. #define SCFG_RGMIIPCR_SETFD BIT(0)
  384. /* PFEASBCR bit definitions */
  385. #define SCFG_PFEASBCR_ARCACHE0 BIT(31)
  386. #define SCFG_PFEASBCR_AWCACHE0 BIT(30)
  387. #define SCFG_PFEASBCR_ARCACHE1 BIT(29)
  388. #define SCFG_PFEASBCR_AWCACHE1 BIT(28)
  389. #define SCFG_PFEASBCR_ARSNP BIT(27)
  390. #define SCFG_PFEASBCR_AWSNP BIT(26)
  391. /* WR_QoS1 PFE bit definitions */
  392. #define SCFG_WR_QOS1_PFE1_QOS GENMASK(27, 24)
  393. #define SCFG_WR_QOS1_PFE2_QOS GENMASK(23, 20)
  394. /* RD_QoS1 PFE bit definitions */
  395. #define SCFG_RD_QOS1_PFE1_QOS GENMASK(27, 24)
  396. #define SCFG_RD_QOS1_PFE2_QOS GENMASK(23, 20)
  397. /* Supplemental Configuration Unit */
  398. struct ccsr_scfg {
  399. u8 res_000[0x100-0x000];
  400. u32 usb2_icid;
  401. u32 usb3_icid;
  402. u8 res_108[0x114-0x108];
  403. u32 dma_icid;
  404. u32 sata_icid;
  405. u32 usb1_icid;
  406. u32 qe_icid;
  407. u32 sdhc_icid;
  408. u32 edma_icid;
  409. u32 etr_icid;
  410. u32 core_sft_rst[4];
  411. u8 res_140[0x158-0x140];
  412. u32 altcbar;
  413. u32 qspi_cfg;
  414. u8 res_160[0x164 - 0x160];
  415. u32 wr_qos1;
  416. u32 wr_qos2;
  417. u32 rd_qos1;
  418. u32 rd_qos2;
  419. u8 res_174[0x180 - 0x174];
  420. u32 dmamcr;
  421. u8 res_184[0x188-0x184];
  422. u32 gic_align;
  423. u32 debug_icid;
  424. u8 res_190[0x1a4-0x190];
  425. u32 snpcnfgcr;
  426. u8 res_1a8[0x1ac-0x1a8];
  427. u32 intpcr;
  428. u8 res_1b0[0x204-0x1b0];
  429. u32 coresrencr;
  430. u8 res_208[0x220-0x208];
  431. u32 rvbar0_0;
  432. u32 rvbar0_1;
  433. u32 rvbar1_0;
  434. u32 rvbar1_1;
  435. u32 rvbar2_0;
  436. u32 rvbar2_1;
  437. u32 rvbar3_0;
  438. u32 rvbar3_1;
  439. u32 lpmcsr;
  440. u8 res_244[0x400-0x244];
  441. u32 qspidqscr;
  442. u32 ecgtxcmcr;
  443. u32 sdhciovselcr;
  444. u32 rcwpmuxcr0;
  445. u32 usbdrvvbus_selcr;
  446. u32 usbpwrfault_selcr;
  447. u32 usb_refclk_selcr1;
  448. u32 usb_refclk_selcr2;
  449. u32 usb_refclk_selcr3;
  450. u8 res_424[0x434 - 0x424];
  451. u32 rgmiipcr;
  452. u32 res_438;
  453. u32 rgmiipsr;
  454. u32 pfepfcssr1;
  455. u32 pfeintencr1;
  456. u32 pfepfcssr2;
  457. u32 pfeintencr2;
  458. u32 pfeerrcr;
  459. u32 pfeeerrintencr;
  460. u32 pfeasbcr;
  461. u32 pfebsbcr;
  462. u8 res_460[0x484 - 0x460];
  463. u32 mdioselcr;
  464. u8 res_468[0x600 - 0x488];
  465. u32 scratchrw[4];
  466. u8 res_610[0x680-0x610];
  467. u32 corebcr;
  468. u8 res_684[0x1000-0x684];
  469. u32 pex1msiir;
  470. u32 pex1msir;
  471. u8 res_1008[0x2000-0x1008];
  472. u32 pex2;
  473. u32 pex2msir;
  474. u8 res_2008[0x3000-0x2008];
  475. u32 pex3msiir;
  476. u32 pex3msir;
  477. };
  478. /* Clocking */
  479. struct ccsr_clk {
  480. struct {
  481. u32 clkcncsr; /* core cluster n clock control status */
  482. u8 res_004[0x0c];
  483. u32 clkcghwacsr; /* Clock generator n hardware accelerator */
  484. u8 res_014[0x0c];
  485. } clkcsr[4];
  486. u8 res_040[0x780]; /* 0x100 */
  487. struct {
  488. u32 pllcngsr;
  489. u8 res_804[0x1c];
  490. } pllcgsr[2];
  491. u8 res_840[0x1c0];
  492. u32 clkpcsr; /* 0xa00 Platform clock domain control/status */
  493. u8 res_a04[0x1fc];
  494. u32 pllpgsr; /* 0xc00 Platform PLL General Status */
  495. u8 res_c04[0x1c];
  496. u32 plldgsr; /* 0xc20 DDR PLL General Status */
  497. u8 res_c24[0x3dc];
  498. };
  499. /* System Counter */
  500. struct sctr_regs {
  501. u32 cntcr;
  502. u32 cntsr;
  503. u32 cntcv1;
  504. u32 cntcv2;
  505. u32 resv1[4];
  506. u32 cntfid0;
  507. u32 cntfid1;
  508. u32 resv2[1002];
  509. u32 counterid[12];
  510. };
  511. #define SRDS_MAX_LANES 4
  512. struct ccsr_serdes {
  513. struct {
  514. u32 rstctl; /* Reset Control Register */
  515. #define SRDS_RSTCTL_RST 0x80000000
  516. #define SRDS_RSTCTL_RSTDONE 0x40000000
  517. #define SRDS_RSTCTL_RSTERR 0x20000000
  518. #define SRDS_RSTCTL_SWRST 0x10000000
  519. #define SRDS_RSTCTL_SDEN 0x00000020
  520. #define SRDS_RSTCTL_SDRST_B 0x00000040
  521. #define SRDS_RSTCTL_PLLRST_B 0x00000080
  522. u32 pllcr0; /* PLL Control Register 0 */
  523. #define SRDS_PLLCR0_POFF 0x80000000
  524. #define SRDS_PLLCR0_RFCK_SEL_MASK 0x70000000
  525. #define SRDS_PLLCR0_RFCK_SEL_100 0x00000000
  526. #define SRDS_PLLCR0_RFCK_SEL_125 0x10000000
  527. #define SRDS_PLLCR0_RFCK_SEL_156_25 0x20000000
  528. #define SRDS_PLLCR0_RFCK_SEL_150 0x30000000
  529. #define SRDS_PLLCR0_RFCK_SEL_161_13 0x40000000
  530. #define SRDS_PLLCR0_RFCK_SEL_122_88 0x50000000
  531. #define SRDS_PLLCR0_PLL_LCK 0x00800000
  532. #define SRDS_PLLCR0_FRATE_SEL_MASK 0x000f0000
  533. #define SRDS_PLLCR0_FRATE_SEL_5 0x00000000
  534. #define SRDS_PLLCR0_FRATE_SEL_3_75 0x00050000
  535. #define SRDS_PLLCR0_FRATE_SEL_5_15 0x00060000
  536. #define SRDS_PLLCR0_FRATE_SEL_4 0x00070000
  537. #define SRDS_PLLCR0_FRATE_SEL_3_12 0x00090000
  538. #define SRDS_PLLCR0_FRATE_SEL_3 0x000a0000
  539. u32 pllcr1; /* PLL Control Register 1 */
  540. #define SRDS_PLLCR1_PLL_BWSEL 0x08000000
  541. u32 res_0c; /* 0x00c */
  542. u32 pllcr3;
  543. u32 pllcr4;
  544. u32 pllcr5; /* 0x018 SerDes PLL1 Control 5 */
  545. u8 res_1c[0x20-0x1c];
  546. } bank[2];
  547. u8 res_40[0x90-0x40];
  548. u32 srdstcalcr; /* 0x90 TX Calibration Control */
  549. u8 res_94[0xa0-0x94];
  550. u32 srdsrcalcr; /* 0xa0 RX Calibration Control */
  551. u8 res_a4[0xb0-0xa4];
  552. u32 srdsgr0; /* 0xb0 General Register 0 */
  553. u8 res_b4[0x100-0xb4];
  554. struct {
  555. u32 lnpssr0; /* 0x100, 0x120, 0x140, 0x160 */
  556. u8 res_104[0x120-0x104];
  557. } lnpssr[4]; /* Lane A, B, C, D */
  558. u8 res_180[0x200-0x180];
  559. u32 srdspccr0; /* 0x200 Protocol Configuration 0 */
  560. u32 srdspccr1; /* 0x204 Protocol Configuration 1 */
  561. u32 srdspccr2; /* 0x208 Protocol Configuration 2 */
  562. u32 srdspccr3; /* 0x20c Protocol Configuration 3 */
  563. u32 srdspccr4; /* 0x210 Protocol Configuration 4 */
  564. u32 srdspccr5; /* 0x214 Protocol Configuration 5 */
  565. u32 srdspccr6; /* 0x218 Protocol Configuration 6 */
  566. u32 srdspccr7; /* 0x21c Protocol Configuration 7 */
  567. u32 srdspccr8; /* 0x220 Protocol Configuration 8 */
  568. u32 srdspccr9; /* 0x224 Protocol Configuration 9 */
  569. u32 srdspccra; /* 0x228 Protocol Configuration A */
  570. u32 srdspccrb; /* 0x22c Protocol Configuration B */
  571. u8 res_230[0x800-0x230];
  572. struct {
  573. u32 gcr0; /* 0x800 General Control Register 0 */
  574. u32 gcr1; /* 0x804 General Control Register 1 */
  575. u32 gcr2; /* 0x808 General Control Register 2 */
  576. u32 sscr0;
  577. u32 recr0; /* 0x810 Receive Equalization Control */
  578. u32 recr1;
  579. u32 tecr0; /* 0x818 Transmit Equalization Control */
  580. u32 sscr1;
  581. u32 ttlcr0; /* 0x820 Transition Tracking Loop Ctrl 0 */
  582. u8 res_824[0x83c-0x824];
  583. u32 tcsr3;
  584. } lane[4]; /* Lane A, B, C, D */
  585. u8 res_900[0x1000-0x900]; /* from 0x900 to 0xfff */
  586. struct {
  587. u32 srdspexcr0; /* 0x1000, 0x1040, 0x1080 */
  588. u8 res_1004[0x1040-0x1004];
  589. } pcie[3];
  590. u8 res_10c0[0x1800-0x10c0];
  591. struct {
  592. u8 res_1800[0x1804-0x1800];
  593. u32 srdssgmiicr1; /* 0x1804 SGMII Protocol Control 1 */
  594. u8 res_1808[0x180c-0x1808];
  595. u32 srdssgmiicr3; /* 0x180c SGMII Protocol Control 3 */
  596. } sgmii[4]; /* Lane A, B, C, D */
  597. u8 res_1840[0x1880-0x1840];
  598. struct {
  599. u8 res_1880[0x1884-0x1880];
  600. u32 srdsqsgmiicr1; /* 0x1884 QSGMII Protocol Control 1 */
  601. u8 res_1888[0x188c-0x1888];
  602. u32 srdsqsgmiicr3; /* 0x188c QSGMII Protocol Control 3 */
  603. } qsgmii[2]; /* Lane A, B */
  604. u8 res_18a0[0x1980-0x18a0];
  605. struct {
  606. u8 res_1980[0x1984-0x1980];
  607. u32 srdsxficr1; /* 0x1984 XFI Protocol Control 1 */
  608. u8 res_1988[0x198c-0x1988];
  609. u32 srdsxficr3; /* 0x198c XFI Protocol Control 3 */
  610. } xfi[2]; /* Lane A, B */
  611. u8 res_19a0[0x2000-0x19a0]; /* from 0x19a0 to 0x1fff */
  612. };
  613. struct ccsr_gpio {
  614. u32 gpdir;
  615. u32 gpodr;
  616. u32 gpdat;
  617. u32 gpier;
  618. u32 gpimr;
  619. u32 gpicr;
  620. u32 gpibe;
  621. };
  622. /* MMU 500 */
  623. #define SMMU_SCR0 (SMMU_BASE + 0x0)
  624. #define SMMU_SCR1 (SMMU_BASE + 0x4)
  625. #define SMMU_SCR2 (SMMU_BASE + 0x8)
  626. #define SMMU_SACR (SMMU_BASE + 0x10)
  627. #define SMMU_IDR0 (SMMU_BASE + 0x20)
  628. #define SMMU_IDR1 (SMMU_BASE + 0x24)
  629. #define SMMU_NSCR0 (SMMU_BASE + 0x400)
  630. #define SMMU_NSCR2 (SMMU_BASE + 0x408)
  631. #define SMMU_NSACR (SMMU_BASE + 0x410)
  632. #define SCR0_CLIENTPD_MASK 0x00000001
  633. #define SCR0_USFCFG_MASK 0x00000400
  634. #ifdef CONFIG_TFABOOT
  635. #define RCW_SRC_MASK (0xFF800000)
  636. #define RCW_SRC_BIT 23
  637. /* RCW SRC NAND */
  638. #define RCW_SRC_NAND_MASK (0x100)
  639. #define RCW_SRC_NAND_VAL (0x100)
  640. #define NAND_RESERVED_MASK (0xFC)
  641. #define NAND_RESERVED_1 (0x0)
  642. #define NAND_RESERVED_2 (0x80)
  643. /* RCW SRC NOR */
  644. #define RCW_SRC_NOR_MASK (0x1F0)
  645. #define NOR_8B_VAL (0x10)
  646. #define NOR_16B_VAL (0x20)
  647. #define SD_VAL (0x40)
  648. #define QSPI_VAL1 (0x44)
  649. #define QSPI_VAL2 (0x45)
  650. #endif
  651. uint get_svr(void);
  652. #endif /* __ARCH_FSL_LSCH2_IMMAP_H__*/