clk_sandbox_ccf.c 6.4 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2019
  4. * Lukasz Majewski, DENX Software Engineering, lukma@denx.de
  5. *
  6. * Common Clock Framework [CCF] driver for Sandbox
  7. */
  8. #include <common.h>
  9. #include <dm.h>
  10. #include <clk.h>
  11. #include <malloc.h>
  12. #include <asm/clk.h>
  13. #include <clk-uclass.h>
  14. #include <dm/devres.h>
  15. #include <linux/bitops.h>
  16. #include <linux/clk-provider.h>
  17. #include <sandbox-clk.h>
  18. #include <linux/err.h>
  19. /*
  20. * Sandbox implementation of CCF primitives necessary for clk-uclass testing
  21. *
  22. * --- Sandbox PLLv3 ---
  23. */
  24. struct clk_pllv3 {
  25. struct clk clk;
  26. u32 div_mask;
  27. u32 div_shift;
  28. };
  29. int sandbox_clk_enable_count(struct clk *clk)
  30. {
  31. struct clk *clkp = NULL;
  32. int ret;
  33. ret = clk_get_by_id(clk->id, &clkp);
  34. if (ret)
  35. return 0;
  36. return clkp->enable_count;
  37. }
  38. static ulong clk_pllv3_get_rate(struct clk *clk)
  39. {
  40. unsigned long parent_rate = clk_get_parent_rate(clk);
  41. return parent_rate * 24;
  42. }
  43. static const struct clk_ops clk_pllv3_generic_ops = {
  44. .get_rate = clk_pllv3_get_rate,
  45. };
  46. struct clk *sandbox_clk_pllv3(enum sandbox_pllv3_type type, const char *name,
  47. const char *parent_name, void __iomem *base,
  48. u32 div_mask)
  49. {
  50. struct clk_pllv3 *pll;
  51. struct clk *clk;
  52. char *drv_name = "sandbox_clk_pllv3";
  53. int ret;
  54. pll = kzalloc(sizeof(*pll), GFP_KERNEL);
  55. if (!pll)
  56. return ERR_PTR(-ENOMEM);
  57. pll->div_mask = div_mask;
  58. clk = &pll->clk;
  59. ret = clk_register(clk, drv_name, name, parent_name);
  60. if (ret) {
  61. kfree(pll);
  62. return ERR_PTR(ret);
  63. }
  64. return clk;
  65. }
  66. U_BOOT_DRIVER(sandbox_clk_pll_generic) = {
  67. .name = "sandbox_clk_pllv3",
  68. .id = UCLASS_CLK,
  69. .ops = &clk_pllv3_generic_ops,
  70. };
  71. /* --- Sandbox PLLv3 --- */
  72. /* --- Sandbox Gate --- */
  73. struct clk_gate2 {
  74. struct clk clk;
  75. bool state;
  76. };
  77. #define to_clk_gate2(_clk) container_of(_clk, struct clk_gate2, clk)
  78. static int clk_gate2_enable(struct clk *clk)
  79. {
  80. struct clk_gate2 *gate = to_clk_gate2(dev_get_clk_ptr(clk->dev));
  81. gate->state = 1;
  82. return 0;
  83. }
  84. static int clk_gate2_disable(struct clk *clk)
  85. {
  86. struct clk_gate2 *gate = to_clk_gate2(dev_get_clk_ptr(clk->dev));
  87. gate->state = 0;
  88. return 0;
  89. }
  90. static const struct clk_ops clk_gate2_ops = {
  91. .enable = clk_gate2_enable,
  92. .disable = clk_gate2_disable,
  93. .get_rate = clk_generic_get_rate,
  94. };
  95. struct clk *sandbox_clk_register_gate2(struct device *dev, const char *name,
  96. const char *parent_name,
  97. unsigned long flags, void __iomem *reg,
  98. u8 bit_idx, u8 cgr_val,
  99. u8 clk_gate2_flags)
  100. {
  101. struct clk_gate2 *gate;
  102. struct clk *clk;
  103. int ret;
  104. gate = kzalloc(sizeof(*gate), GFP_KERNEL);
  105. if (!gate)
  106. return ERR_PTR(-ENOMEM);
  107. gate->state = 0;
  108. clk = &gate->clk;
  109. ret = clk_register(clk, "sandbox_clk_gate2", name, parent_name);
  110. if (ret) {
  111. kfree(gate);
  112. return ERR_PTR(ret);
  113. }
  114. return clk;
  115. }
  116. U_BOOT_DRIVER(sandbox_clk_gate2) = {
  117. .name = "sandbox_clk_gate2",
  118. .id = UCLASS_CLK,
  119. .ops = &clk_gate2_ops,
  120. };
  121. static unsigned long sandbox_clk_composite_divider_recalc_rate(struct clk *clk)
  122. {
  123. struct clk_divider *divider = (struct clk_divider *)to_clk_divider(clk);
  124. struct clk_composite *composite = (struct clk_composite *)clk->data;
  125. ulong parent_rate = clk_get_parent_rate(&composite->clk);
  126. unsigned int val;
  127. val = divider->io_divider_val;
  128. val >>= divider->shift;
  129. val &= clk_div_mask(divider->width);
  130. return divider_recalc_rate(clk, parent_rate, val, divider->table,
  131. divider->flags, divider->width);
  132. }
  133. static const struct clk_ops sandbox_clk_composite_divider_ops = {
  134. .get_rate = sandbox_clk_composite_divider_recalc_rate,
  135. };
  136. struct clk *sandbox_clk_composite(const char *name,
  137. const char * const *parent_names,
  138. int num_parents, void __iomem *reg,
  139. unsigned long flags)
  140. {
  141. struct clk *clk = ERR_PTR(-ENOMEM);
  142. struct clk_divider *div = NULL;
  143. struct clk_gate *gate = NULL;
  144. struct clk_mux *mux = NULL;
  145. mux = kzalloc(sizeof(*mux), GFP_KERNEL);
  146. if (!mux)
  147. goto fail;
  148. mux->reg = reg;
  149. mux->shift = 24;
  150. mux->mask = 0x7;
  151. mux->num_parents = num_parents;
  152. mux->flags = flags;
  153. mux->parent_names = parent_names;
  154. div = kzalloc(sizeof(*div), GFP_KERNEL);
  155. if (!div)
  156. goto fail;
  157. div->reg = reg;
  158. div->shift = 16;
  159. div->width = 3;
  160. div->flags = CLK_DIVIDER_ROUND_CLOSEST | flags;
  161. gate = kzalloc(sizeof(*gate), GFP_KERNEL);
  162. if (!gate)
  163. goto fail;
  164. gate->reg = reg;
  165. gate->bit_idx = 28;
  166. gate->flags = flags;
  167. clk = clk_register_composite(NULL, name,
  168. parent_names, num_parents,
  169. &mux->clk, &clk_mux_ops, &div->clk,
  170. &sandbox_clk_composite_divider_ops,
  171. &gate->clk, &clk_gate_ops, flags);
  172. if (IS_ERR(clk))
  173. goto fail;
  174. return clk;
  175. fail:
  176. kfree(gate);
  177. kfree(div);
  178. kfree(mux);
  179. return ERR_CAST(clk);
  180. }
  181. /* --- Sandbox Gate --- */
  182. /* The CCF core driver itself */
  183. static const struct udevice_id sandbox_clk_ccf_test_ids[] = {
  184. { .compatible = "sandbox,clk-ccf" },
  185. { }
  186. };
  187. static const char *const usdhc_sels[] = { "pll3_60m", "pll3_80m", };
  188. static const char *const i2c_sels[] = { "pll3_60m", "pll3_80m", };
  189. static int sandbox_clk_ccf_probe(struct udevice *dev)
  190. {
  191. void *base = NULL;
  192. u32 reg;
  193. clk_dm(SANDBOX_CLK_PLL3,
  194. sandbox_clk_pllv3(SANDBOX_PLLV3_USB, "pll3_usb_otg", "osc",
  195. base + 0x10, 0x3));
  196. clk_dm(SANDBOX_CLK_PLL3_60M,
  197. sandbox_clk_fixed_factor("pll3_60m", "pll3_usb_otg", 1, 8));
  198. clk_dm(SANDBOX_CLK_PLL3_80M,
  199. sandbox_clk_fixed_factor("pll3_80m", "pll3_usb_otg", 1, 6));
  200. /* The HW adds +1 to the divider value (2+1) is the divider */
  201. reg = (2 << 19);
  202. clk_dm(SANDBOX_CLK_ECSPI_ROOT,
  203. sandbox_clk_divider("ecspi_root", "pll3_60m", &reg, 19, 6));
  204. reg = 0;
  205. clk_dm(SANDBOX_CLK_ECSPI0,
  206. sandbox_clk_gate("ecspi0", "ecspi_root", &reg, 0, 0));
  207. clk_dm(SANDBOX_CLK_ECSPI1,
  208. sandbox_clk_gate2("ecspi1", "ecspi_root", base + 0x6c, 0));
  209. /* Select 'pll3_60m' */
  210. reg = 0;
  211. clk_dm(SANDBOX_CLK_USDHC1_SEL,
  212. sandbox_clk_mux("usdhc1_sel", &reg, 16, 1, usdhc_sels,
  213. ARRAY_SIZE(usdhc_sels)));
  214. /* Select 'pll3_80m' */
  215. reg = BIT(17);
  216. clk_dm(SANDBOX_CLK_USDHC2_SEL,
  217. sandbox_clk_mux("usdhc2_sel", &reg, 17, 1, usdhc_sels,
  218. ARRAY_SIZE(usdhc_sels)));
  219. reg = BIT(28) | BIT(24) | BIT(16);
  220. clk_dm(SANDBOX_CLK_I2C,
  221. sandbox_clk_composite("i2c", i2c_sels, ARRAY_SIZE(i2c_sels),
  222. &reg, 0));
  223. clk_dm(SANDBOX_CLK_I2C_ROOT,
  224. sandbox_clk_gate2("i2c_root", "i2c", base + 0x7c, 0));
  225. return 0;
  226. }
  227. U_BOOT_DRIVER(sandbox_clk_ccf) = {
  228. .name = "sandbox_clk_ccf",
  229. .id = UCLASS_CLK,
  230. .probe = sandbox_clk_ccf_probe,
  231. .of_match = sandbox_clk_ccf_test_ids,
  232. };