interrupts.c 6.2 KB

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  1. /*
  2. * (C) Copyright 2002
  3. * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
  4. * Marius Groeger <mgroeger@sysgo.de>
  5. *
  6. * (C) Copyright 2002
  7. * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
  8. * Alex Zuepke <azu@sysgo.de>
  9. *
  10. * See file CREDITS for list of people who contributed to this
  11. * project.
  12. *
  13. * This program is free software; you can redistribute it and/or
  14. * modify it under the terms of the GNU General Public License as
  15. * published by the Free Software Foundation; either version 2 of
  16. * the License, or (at your option) any later version.
  17. *
  18. * This program is distributed in the hope that it will be useful,
  19. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  20. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  21. * GNU General Public License for more details.
  22. *
  23. * You should have received a copy of the GNU General Public License
  24. * along with this program; if not, write to the Free Software
  25. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  26. * MA 02111-1307 USA
  27. */
  28. #include <common.h>
  29. #include <clps7111.h>
  30. #include <asm/proc-armv/ptrace.h>
  31. #ifdef CONFIG_NETARM
  32. #include <asm/arch/netarm_registers.h>
  33. #endif
  34. extern void reset_cpu(ulong addr);
  35. #ifndef CONFIG_NETARM
  36. /* we always count down the max. */
  37. #define TIMER_LOAD_VAL 0xffff
  38. /* macro to read the 16 bit timer */
  39. #define READ_TIMER (IO_TC1D & 0xffff)
  40. #else
  41. #define IRQEN (*(volatile unsigned int *)(NETARM_GEN_MODULE_BASE + NETARM_GEN_INTR_ENABLE))
  42. #define TM2CTRL (*(volatile unsigned int *)(NETARM_GEN_MODULE_BASE + NETARM_GEN_TIMER2_CONTROL))
  43. #define TM2STAT (*(volatile unsigned int *)(NETARM_GEN_MODULE_BASE + NETARM_GEN_TIMER2_STATUS))
  44. #define TIMER_LOAD_VAL NETARM_GEN_TSTAT_CTC_MASK
  45. #define READ_TIMER (TM2STAT & NETARM_GEN_TSTAT_CTC_MASK)
  46. #endif
  47. #ifdef CONFIG_USE_IRQ
  48. /* enable IRQ/FIQ interrupts */
  49. void enable_interrupts (void)
  50. {
  51. unsigned long temp;
  52. __asm__ __volatile__("mrs %0, cpsr\n"
  53. "bic %0, %0, #0x80\n"
  54. "msr cpsr_c, %0"
  55. : "=r" (temp)
  56. :
  57. : "memory");
  58. }
  59. /*
  60. * disable IRQ/FIQ interrupts
  61. * returns true if interrupts had been enabled before we disabled them
  62. */
  63. int disable_interrupts (void)
  64. {
  65. unsigned long old,temp;
  66. __asm__ __volatile__("mrs %0, cpsr\n"
  67. "orr %1, %0, #0x80\n"
  68. "msr cpsr_c, %1"
  69. : "=r" (old), "=r" (temp)
  70. :
  71. : "memory");
  72. return (old & 0x80) == 0;
  73. }
  74. #else
  75. void enable_interrupts (void)
  76. {
  77. return;
  78. }
  79. int disable_interrupts (void)
  80. {
  81. return 0;
  82. }
  83. #endif
  84. void bad_mode (void)
  85. {
  86. panic ("Resetting CPU ...\n");
  87. reset_cpu (0);
  88. }
  89. void show_regs (struct pt_regs *regs)
  90. {
  91. unsigned long flags;
  92. const char *processor_modes[] =
  93. { "USER_26", "FIQ_26", "IRQ_26", "SVC_26", "UK4_26", "UK5_26",
  94. "UK6_26", "UK7_26",
  95. "UK8_26", "UK9_26", "UK10_26", "UK11_26", "UK12_26", "UK13_26",
  96. "UK14_26", "UK15_26",
  97. "USER_32", "FIQ_32", "IRQ_32", "SVC_32", "UK4_32", "UK5_32",
  98. "UK6_32", "ABT_32",
  99. "UK8_32", "UK9_32", "UK10_32", "UND_32", "UK12_32", "UK13_32",
  100. "UK14_32", "SYS_32"
  101. };
  102. flags = condition_codes (regs);
  103. printf ("pc : [<%08lx>] lr : [<%08lx>]\n"
  104. "sp : %08lx ip : %08lx fp : %08lx\n",
  105. instruction_pointer (regs),
  106. regs->ARM_lr, regs->ARM_sp, regs->ARM_ip, regs->ARM_fp);
  107. printf ("r10: %08lx r9 : %08lx r8 : %08lx\n",
  108. regs->ARM_r10, regs->ARM_r9, regs->ARM_r8);
  109. printf ("r7 : %08lx r6 : %08lx r5 : %08lx r4 : %08lx\n",
  110. regs->ARM_r7, regs->ARM_r6, regs->ARM_r5, regs->ARM_r4);
  111. printf ("r3 : %08lx r2 : %08lx r1 : %08lx r0 : %08lx\n",
  112. regs->ARM_r3, regs->ARM_r2, regs->ARM_r1, regs->ARM_r0);
  113. printf ("Flags: %c%c%c%c",
  114. flags & CC_N_BIT ? 'N' : 'n',
  115. flags & CC_Z_BIT ? 'Z' : 'z',
  116. flags & CC_C_BIT ? 'C' : 'c', flags & CC_V_BIT ? 'V' : 'v');
  117. printf (" IRQs %s FIQs %s Mode %s%s\n",
  118. interrupts_enabled (regs) ? "on" : "off",
  119. fast_interrupts_enabled (regs) ? "on" : "off",
  120. processor_modes[processor_mode (regs)],
  121. thumb_mode (regs) ? " (T)" : "");
  122. }
  123. void do_undefined_instruction (struct pt_regs *pt_regs)
  124. {
  125. printf ("undefined instruction\n");
  126. show_regs (pt_regs);
  127. bad_mode ();
  128. }
  129. void do_software_interrupt (struct pt_regs *pt_regs)
  130. {
  131. printf ("software interrupt\n");
  132. show_regs (pt_regs);
  133. bad_mode ();
  134. }
  135. void do_prefetch_abort (struct pt_regs *pt_regs)
  136. {
  137. printf ("prefetch abort\n");
  138. show_regs (pt_regs);
  139. bad_mode ();
  140. }
  141. void do_data_abort (struct pt_regs *pt_regs)
  142. {
  143. printf ("data abort\n");
  144. show_regs (pt_regs);
  145. bad_mode ();
  146. }
  147. void do_not_used (struct pt_regs *pt_regs)
  148. {
  149. printf ("not used\n");
  150. show_regs (pt_regs);
  151. bad_mode ();
  152. }
  153. void do_fiq (struct pt_regs *pt_regs)
  154. {
  155. printf ("fast interrupt request\n");
  156. show_regs (pt_regs);
  157. bad_mode ();
  158. }
  159. void do_irq (struct pt_regs *pt_regs)
  160. {
  161. printf ("interrupt request\n");
  162. show_regs (pt_regs);
  163. bad_mode ();
  164. }
  165. static ulong timestamp;
  166. static ulong lastdec;
  167. int interrupt_init (void)
  168. {
  169. #ifdef CONFIG_NETARM
  170. /* disable all interrupts */
  171. IRQEN = 0;
  172. /* operate timer 2 in non-prescale mode */
  173. TM2CTRL = ( NETARM_GEN_TIMER_SET_HZ(CFG_HZ) |
  174. NETARM_GEN_TCTL_ENABLE |
  175. NETARM_GEN_TCTL_INIT_COUNT(TIMER_LOAD_VAL));
  176. /* set timer 2 counter */
  177. lastdec = TIMER_LOAD_VAL;
  178. #else
  179. /* disable all interrupts */
  180. IO_INTMR1 = 0;
  181. /* operate timer 1 in prescale mode */
  182. IO_SYSCON1 |= SYSCON1_TC1M;
  183. /* select 2kHz clock source for timer 1 */
  184. IO_SYSCON1 &= ~SYSCON1_TC1S;
  185. /* set timer 1 counter */
  186. lastdec = IO_TC1D = TIMER_LOAD_VAL;
  187. #endif
  188. timestamp = 0;
  189. return (0);
  190. }
  191. /*
  192. * timer without interrupts
  193. */
  194. void reset_timer (void)
  195. {
  196. reset_timer_masked ();
  197. }
  198. ulong get_timer (ulong base)
  199. {
  200. return get_timer_masked () - base;
  201. }
  202. void set_timer (ulong t)
  203. {
  204. timestamp = t;
  205. }
  206. void udelay (unsigned long usec)
  207. {
  208. ulong tmo;
  209. tmo = usec / 1000;
  210. tmo *= CFG_HZ;
  211. tmo /= 1000;
  212. tmo += get_timer (0);
  213. while (get_timer_masked () < tmo)
  214. /*NOP*/;
  215. }
  216. void reset_timer_masked (void)
  217. {
  218. /* reset time */
  219. lastdec = READ_TIMER;
  220. timestamp = 0;
  221. }
  222. ulong get_timer_masked (void)
  223. {
  224. ulong now = READ_TIMER;
  225. if (lastdec >= now) {
  226. /* normal mode */
  227. timestamp += lastdec - now;
  228. } else {
  229. /* we have an overflow ... */
  230. timestamp += lastdec + TIMER_LOAD_VAL - now;
  231. }
  232. lastdec = now;
  233. return timestamp;
  234. }
  235. void udelay_masked (unsigned long usec)
  236. {
  237. ulong tmo;
  238. tmo = usec / 1000;
  239. tmo *= CFG_HZ;
  240. tmo /= 1000;
  241. reset_timer_masked ();
  242. while (get_timer_masked () < tmo)
  243. /*NOP*/;
  244. }