init.S 7.4 KB

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  1. /******************************************************************************
  2. *
  3. * This source code has been made available to you by IBM on an AS-IS
  4. * basis. Anyone receiving this source is licensed under IBM
  5. * copyrights to use it in any way he or she deems fit, including
  6. * copying it, modifying it, compiling it, and redistributing it either
  7. * with or without modifications. No license under IBM patents or
  8. * patent applications is to be implied by the copyright license.
  9. *
  10. * Any user of this software should understand that IBM cannot provide
  11. * technical support for this software and will not be responsible for
  12. * any consequences resulting from the use of this software.
  13. *
  14. * Any person who transfers this source code or any derivative work
  15. * must include the IBM copyright notice, this paragraph, and the
  16. * preceding two paragraphs in the transferred software.
  17. *
  18. * COPYRIGHT I B M CORPORATION 1995
  19. * LICENSED MATERIAL - PROGRAM PROPERTY OF I B M
  20. *
  21. *****************************************************************************/
  22. #include <config.h>
  23. #include <ppc4xx.h>
  24. #define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */
  25. #include <ppc_asm.tmpl>
  26. #include <ppc_defs.h>
  27. #include <asm/cache.h>
  28. #include <asm/mmu.h>
  29. #define LI32(reg,val) \
  30. addis reg,0,val@h;\
  31. ori reg,reg,val@l
  32. #define WDCR_EBC(reg,val) \
  33. addi r4,0,reg;\
  34. mtdcr ebccfga,r4;\
  35. addis r4,0,val@h;\
  36. ori r4,r4,val@l;\
  37. mtdcr ebccfgd,r4
  38. #define WDCR_SDRAM(reg,val) \
  39. addi r4,0,reg;\
  40. mtdcr memcfga,r4;\
  41. addis r4,0,val@h;\
  42. ori r4,r4,val@l;\
  43. mtdcr memcfgd,r4
  44. /******************************************************************************
  45. * Function: ext_bus_cntlr_init
  46. *
  47. * Description: Configures EBC Controller and a few basic chip selects.
  48. *
  49. * CS0 is setup to get the Boot Flash out of the addresss range
  50. * so that we may setup a stack. CS7 is setup so that we can
  51. * access and reset the hardware watchdog.
  52. *
  53. * IMPORTANT: For pass1 this code must run from
  54. * cache since you can not reliably change a peripheral banks
  55. * timing register (pbxap) while running code from that bank.
  56. * For ex., since we are running from ROM on bank 0, we can NOT
  57. * execute the code that modifies bank 0 timings from ROM, so
  58. * we run it from cache.
  59. *
  60. * Notes: Does NOT use the stack.
  61. *****************************************************************************/
  62. .section ".text"
  63. .align 2
  64. .globl ext_bus_cntlr_init
  65. .type ext_bus_cntlr_init, @function
  66. ext_bus_cntlr_init:
  67. mflr r0
  68. /********************************************************************
  69. * Prefetch entire ext_bus_cntrl_init function into the icache.
  70. * This is necessary because we are going to change the same CS we
  71. * are executing from. Otherwise a CPU lockup may occur.
  72. *******************************************************************/
  73. bl ..getAddr
  74. ..getAddr:
  75. mflr r3 /* get address of ..getAddr */
  76. /* Calculate number of cache lines for this function */
  77. addi r4, 0, (((.Lfe0 - ..getAddr) / CFG_CACHELINE_SIZE) + 2)
  78. mtctr r4
  79. ..ebcloop:
  80. icbt r0, r3 /* prefetch cache line for addr in r3*/
  81. addi r3, r3, CFG_CACHELINE_SIZE /* move to next cache line */
  82. bdnz ..ebcloop /* continue for $CTR cache lines */
  83. /********************************************************************
  84. * Delay to ensure all accesses to ROM are complete before changing
  85. * bank 0 timings. 200usec should be enough.
  86. * 200,000,000 (cycles/sec) X .000200 (sec) = 0x9C40 cycles.
  87. *******************************************************************/
  88. addis r3, 0, 0x0
  89. ori r3, r3, 0xA000 /* wait 200us from reset */
  90. mtctr r3
  91. ..spinlp:
  92. bdnz ..spinlp /* spin loop */
  93. /********************************************************************
  94. * SETUP CPC0_CR0
  95. *******************************************************************/
  96. LI32(r4, 0x007000c0)
  97. mtdcr cntrl0, r4
  98. /********************************************************************
  99. * Setup CPC0_CR1: Change PCIINT signal to PerWE
  100. *******************************************************************/
  101. mfdcr r4, cntrl1
  102. ori r4, r4, 0x4000
  103. mtdcr cntrl1, r4
  104. /********************************************************************
  105. * Setup External Bus Controller (EBC).
  106. *******************************************************************/
  107. WDCR_EBC(epcr, 0xd84c0000)
  108. /********************************************************************
  109. * Memory Bank 0 (Intel 28F128J3 Flash) initialization
  110. *******************************************************************/
  111. /*WDCR_EBC(pb0ap, 0x02869200)*/
  112. WDCR_EBC(pb0ap, 0x07869200)
  113. WDCR_EBC(pb0cr, 0xfe0bc000)
  114. /********************************************************************
  115. * Memory Bank 1 (Holtek HT6542B PS/2) initialization
  116. *******************************************************************/
  117. WDCR_EBC(pb1ap, 0x1f869200)
  118. WDCR_EBC(pb1cr, 0xf0818000)
  119. /********************************************************************
  120. * Memory Bank 2 (Epson S1D13506) initialization
  121. *******************************************************************/
  122. WDCR_EBC(pb2ap, 0x05860300)
  123. WDCR_EBC(pb2cr, 0xf045a000)
  124. /********************************************************************
  125. * Memory Bank 3 (Philips SJA1000 CAN Controllers) initialization
  126. *******************************************************************/
  127. WDCR_EBC(pb3ap, 0x0387d200)
  128. WDCR_EBC(pb3cr, 0xf021c000)
  129. /********************************************************************
  130. * Memory Bank 4-7 (Unused) initialization
  131. *******************************************************************/
  132. WDCR_EBC(pb4ap, 0)
  133. WDCR_EBC(pb4cr, 0)
  134. WDCR_EBC(pb5ap, 0)
  135. WDCR_EBC(pb5cr, 0)
  136. WDCR_EBC(pb6ap, 0)
  137. WDCR_EBC(pb6cr, 0)
  138. WDCR_EBC(pb7ap, 0)
  139. WDCR_EBC(pb7cr, 0)
  140. /* We are all done */
  141. mtlr r0 /* Restore link register */
  142. blr /* Return to calling function */
  143. .Lfe0: .size ext_bus_cntlr_init,.Lfe0-ext_bus_cntlr_init
  144. /* end ext_bus_cntlr_init() */
  145. /******************************************************************************
  146. * Function: sdram_init
  147. *
  148. * Description: Configures SDRAM memory banks.
  149. *
  150. * Notes: Does NOT use the stack.
  151. *****************************************************************************/
  152. .section ".text"
  153. .align 2
  154. .globl sdram_init
  155. .type sdram_init, @function
  156. sdram_init:
  157. /*
  158. * Disable memory controller to allow
  159. * values to be changed.
  160. */
  161. WDCR_SDRAM(mem_mcopt1, 0x00000000)
  162. /*
  163. * Configure Memory Banks
  164. */
  165. WDCR_SDRAM(mem_mb0cf, 0x00084001)
  166. WDCR_SDRAM(mem_mb1cf, 0x00000000)
  167. WDCR_SDRAM(mem_mb2cf, 0x00000000)
  168. WDCR_SDRAM(mem_mb3cf, 0x00000000)
  169. /*
  170. * Set up SDTR1 (SDRAM Timing Register)
  171. */
  172. WDCR_SDRAM(mem_sdtr1, 0x00854009)
  173. /*
  174. * Set RTR (Refresh Timing Register)
  175. */
  176. WDCR_SDRAM(mem_rtr, 0x10000000)
  177. /* WDCR_SDRAM(mem_rtr, 0x05f00000) */
  178. /********************************************************************
  179. * Delay to ensure 200usec have elapsed since reset. Assume worst
  180. * case that the core is running 200Mhz:
  181. * 200,000,000 (cycles/sec) X .000200 (sec) = 0x9C40 cycles
  182. *******************************************************************/
  183. addis r3, 0, 0x0000
  184. ori r3, r3, 0xA000 /* Wait >200us from reset */
  185. mtctr r3
  186. ..spinlp2:
  187. bdnz ..spinlp2 /* spin loop */
  188. /********************************************************************
  189. * Set memory controller options reg, MCOPT1.
  190. *******************************************************************/
  191. WDCR_SDRAM(mem_mcopt1,0x80800000)
  192. ..sdri_done:
  193. blr /* Return to calling function */
  194. .Lfe1: .size sdram_init,.Lfe1-sdram_init
  195. /* end sdram_init() */