IxNpeDlNpeMgrEcRegisters_p.h 24 KB

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  1. /**
  2. * @file IxNpeDlNpeMgrEcRegisters_p.h
  3. *
  4. * @author Intel Corporation
  5. * @date 14 December 2001
  6. *
  7. * @par
  8. * IXP400 SW Release version 2.0
  9. *
  10. * -- Copyright Notice --
  11. *
  12. * @par
  13. * Copyright 2001-2005, Intel Corporation.
  14. * All rights reserved.
  15. *
  16. * @par
  17. * SPDX-License-Identifier: BSD-3-Clause
  18. * @par
  19. * -- End of Copyright Notice --
  20. */
  21. #ifndef IXNPEDLNPEMGRECREGISTERS_P_H
  22. #define IXNPEDLNPEMGRECREGISTERS_P_H
  23. #include "IxOsal.h"
  24. /*
  25. * Base Memory Addresses for accessing NPE registers
  26. */
  27. #define IX_NPEDL_NPE_BASE (IX_OSAL_IXP400_PERIPHERAL_PHYS_BASE)
  28. #define IX_NPEDL_NPEA_OFFSET (0x6000) /**< NPE-A register base offset */
  29. #define IX_NPEDL_NPEB_OFFSET (0x7000) /**< NPE-B register base offset */
  30. #define IX_NPEDL_NPEC_OFFSET (0x8000) /**< NPE-C register base offset */
  31. /**
  32. * @def IX_NPEDL_NPEBASEADDRESS_NPEA
  33. * @brief Base Memory Address of NPE-A Configuration Bus registers
  34. */
  35. #define IX_NPEDL_NPEBASEADDRESS_NPEA (IX_NPEDL_NPE_BASE + IX_NPEDL_NPEA_OFFSET)
  36. /**
  37. * @def IX_NPEDL_NPEBASEADDRESS_NPEB
  38. * @brief Base Memory Address of NPE-B Configuration Bus registers
  39. */
  40. #define IX_NPEDL_NPEBASEADDRESS_NPEB (IX_NPEDL_NPE_BASE + IX_NPEDL_NPEB_OFFSET)
  41. /**
  42. * @def IX_NPEDL_NPEBASEADDRESS_NPEC
  43. * @brief Base Memory Address of NPE-C Configuration Bus registers
  44. */
  45. #define IX_NPEDL_NPEBASEADDRESS_NPEC (IX_NPEDL_NPE_BASE + IX_NPEDL_NPEC_OFFSET)
  46. /*
  47. * Instruction Memory Size (in words) for each NPE
  48. */
  49. /**
  50. * @def IX_NPEDL_INS_MEMSIZE_WORDS_NPEA
  51. * @brief Size (in words) of NPE-A Instruction Memory
  52. */
  53. #define IX_NPEDL_INS_MEMSIZE_WORDS_NPEA 4096
  54. /**
  55. * @def IX_NPEDL_INS_MEMSIZE_WORDS_NPEB
  56. * @brief Size (in words) of NPE-B Instruction Memory
  57. */
  58. #define IX_NPEDL_INS_MEMSIZE_WORDS_NPEB 2048
  59. /**
  60. * @def IX_NPEDL_INS_MEMSIZE_WORDS_NPEC
  61. * @brief Size (in words) of NPE-B Instruction Memory
  62. */
  63. #define IX_NPEDL_INS_MEMSIZE_WORDS_NPEC 2048
  64. /*
  65. * Data Memory Size (in words) for each NPE
  66. */
  67. /**
  68. * @def IX_NPEDL_DATA_MEMSIZE_WORDS_NPEA
  69. * @brief Size (in words) of NPE-A Data Memory
  70. */
  71. #define IX_NPEDL_DATA_MEMSIZE_WORDS_NPEA 2048
  72. /**
  73. * @def IX_NPEDL_DATA_MEMSIZE_WORDS_NPEB
  74. * @brief Size (in words) of NPE-B Data Memory
  75. */
  76. #define IX_NPEDL_DATA_MEMSIZE_WORDS_NPEB 2048
  77. /**
  78. * @def IX_NPEDL_DATA_MEMSIZE_WORDS_NPEC
  79. * @brief Size (in words) of NPE-C Data Memory
  80. */
  81. #define IX_NPEDL_DATA_MEMSIZE_WORDS_NPEC 2048
  82. /*
  83. * Configuration Bus Register offsets (in bytes) from NPE Base Address
  84. */
  85. /**
  86. * @def IX_NPEDL_REG_OFFSET_EXAD
  87. * @brief Offset (in bytes) of EXAD (Execution Address) register from NPE Base
  88. * Address
  89. */
  90. #define IX_NPEDL_REG_OFFSET_EXAD 0x00000000
  91. /**
  92. * @def IX_NPEDL_REG_OFFSET_EXDATA
  93. * @brief Offset (in bytes) of EXDATA (Execution Data) register from NPE Base
  94. * Address
  95. */
  96. #define IX_NPEDL_REG_OFFSET_EXDATA 0x00000004
  97. /**
  98. * @def IX_NPEDL_REG_OFFSET_EXCTL
  99. * @brief Offset (in bytes) of EXCTL (Execution Control) register from NPE Base
  100. * Address
  101. */
  102. #define IX_NPEDL_REG_OFFSET_EXCTL 0x00000008
  103. /**
  104. * @def IX_NPEDL_REG_OFFSET_EXCT
  105. * @brief Offset (in bytes) of EXCT (Execution Count) register from NPE Base
  106. * Address
  107. */
  108. #define IX_NPEDL_REG_OFFSET_EXCT 0x0000000C
  109. /**
  110. * @def IX_NPEDL_REG_OFFSET_AP0
  111. * @brief Offset (in bytes) of AP0 (Action Point 0) register from NPE Base
  112. * Address
  113. */
  114. #define IX_NPEDL_REG_OFFSET_AP0 0x00000010
  115. /**
  116. * @def IX_NPEDL_REG_OFFSET_AP1
  117. * @brief Offset (in bytes) of AP1 (Action Point 1) register from NPE Base
  118. * Address
  119. */
  120. #define IX_NPEDL_REG_OFFSET_AP1 0x00000014
  121. /**
  122. * @def IX_NPEDL_REG_OFFSET_AP2
  123. * @brief Offset (in bytes) of AP2 (Action Point 2) register from NPE Base
  124. * Address
  125. */
  126. #define IX_NPEDL_REG_OFFSET_AP2 0x00000018
  127. /**
  128. * @def IX_NPEDL_REG_OFFSET_AP3
  129. * @brief Offset (in bytes) of AP3 (Action Point 3) register from NPE Base
  130. * Address
  131. */
  132. #define IX_NPEDL_REG_OFFSET_AP3 0x0000001C
  133. /**
  134. * @def IX_NPEDL_REG_OFFSET_WFIFO
  135. * @brief Offset (in bytes) of WFIFO (Watchpoint FIFO) register from NPE Base
  136. * Address
  137. */
  138. #define IX_NPEDL_REG_OFFSET_WFIFO 0x00000020
  139. /**
  140. * @def IX_NPEDL_REG_OFFSET_WC
  141. * @brief Offset (in bytes) of WC (Watch Count) register from NPE Base
  142. * Address
  143. */
  144. #define IX_NPEDL_REG_OFFSET_WC 0x00000024
  145. /**
  146. * @def IX_NPEDL_REG_OFFSET_PROFCT
  147. * @brief Offset (in bytes) of PROFCT (Profile Count) register from NPE Base
  148. * Address
  149. */
  150. #define IX_NPEDL_REG_OFFSET_PROFCT 0x00000028
  151. /**
  152. * @def IX_NPEDL_REG_OFFSET_STAT
  153. * @brief Offset (in bytes) of STAT (Messaging Status) register from NPE Base
  154. * Address
  155. */
  156. #define IX_NPEDL_REG_OFFSET_STAT 0x0000002C
  157. /**
  158. * @def IX_NPEDL_REG_OFFSET_CTL
  159. * @brief Offset (in bytes) of CTL (Messaging Control) register from NPE Base
  160. * Address
  161. */
  162. #define IX_NPEDL_REG_OFFSET_CTL 0x00000030
  163. /**
  164. * @def IX_NPEDL_REG_OFFSET_MBST
  165. * @brief Offset (in bytes) of MBST (Mailbox Status) register from NPE Base
  166. * Address
  167. */
  168. #define IX_NPEDL_REG_OFFSET_MBST 0x00000034
  169. /**
  170. * @def IX_NPEDL_REG_OFFSET_FIFO
  171. * @brief Offset (in bytes) of FIFO (messaging in/out FIFO) register from NPE
  172. * Base Address
  173. */
  174. #define IX_NPEDL_REG_OFFSET_FIFO 0x00000038
  175. /*
  176. * Non-zero reset values for the Configuration Bus registers
  177. */
  178. /**
  179. * @def IX_NPEDL_REG_RESET_FIFO
  180. * @brief Reset value for Mailbox (MBST) register
  181. * NOTE that if used, it should be complemented with an NPE intruction
  182. * to clear the Mailbox at the NPE side as well
  183. */
  184. #define IX_NPEDL_REG_RESET_MBST 0x0000F0F0
  185. /*
  186. * Bit-masks used to read/write particular bits in Configuration Bus registers
  187. */
  188. /**
  189. * @def IX_NPEDL_MASK_WFIFO_VALID
  190. * @brief Masks the VALID bit in the WFIFO register
  191. */
  192. #define IX_NPEDL_MASK_WFIFO_VALID 0x80000000
  193. /**
  194. * @def IX_NPEDL_MASK_STAT_OFNE
  195. * @brief Masks the OFNE bit in the STAT register
  196. */
  197. #define IX_NPEDL_MASK_STAT_OFNE 0x00010000
  198. /**
  199. * @def IX_NPEDL_MASK_STAT_IFNE
  200. * @brief Masks the IFNE bit in the STAT register
  201. */
  202. #define IX_NPEDL_MASK_STAT_IFNE 0x00080000
  203. /*
  204. * EXCTL (Execution Control) Register commands
  205. */
  206. /**
  207. * @def IX_NPEDL_EXCTL_CMD_NPE_STEP
  208. * @brief EXCTL Command to Step execution of an NPE Instruction
  209. */
  210. #define IX_NPEDL_EXCTL_CMD_NPE_STEP 0x01
  211. /**
  212. * @def IX_NPEDL_EXCTL_CMD_NPE_START
  213. * @brief EXCTL Command to Start NPE execution
  214. */
  215. #define IX_NPEDL_EXCTL_CMD_NPE_START 0x02
  216. /**
  217. * @def IX_NPEDL_EXCTL_CMD_NPE_STOP
  218. * @brief EXCTL Command to Stop NPE execution
  219. */
  220. #define IX_NPEDL_EXCTL_CMD_NPE_STOP 0x03
  221. /**
  222. * @def IX_NPEDL_EXCTL_CMD_NPE_CLR_PIPE
  223. * @brief EXCTL Command to Clear NPE instruction pipeline
  224. */
  225. #define IX_NPEDL_EXCTL_CMD_NPE_CLR_PIPE 0x04
  226. /**
  227. * @def IX_NPEDL_EXCTL_CMD_RD_INS_MEM
  228. * @brief EXCTL Command to read NPE instruction memory at address in EXAD
  229. * register and return value in EXDATA register
  230. */
  231. #define IX_NPEDL_EXCTL_CMD_RD_INS_MEM 0x10
  232. /**
  233. * @def IX_NPEDL_EXCTL_CMD_WR_INS_MEM
  234. * @brief EXCTL Command to write NPE instruction memory at address in EXAD
  235. * register with data in EXDATA register
  236. */
  237. #define IX_NPEDL_EXCTL_CMD_WR_INS_MEM 0x11
  238. /**
  239. * @def IX_NPEDL_EXCTL_CMD_RD_DATA_MEM
  240. * @brief EXCTL Command to read NPE data memory at address in EXAD
  241. * register and return value in EXDATA register
  242. */
  243. #define IX_NPEDL_EXCTL_CMD_RD_DATA_MEM 0x12
  244. /**
  245. * @def IX_NPEDL_EXCTL_CMD_WR_DATA_MEM
  246. * @brief EXCTL Command to write NPE data memory at address in EXAD
  247. * register with data in EXDATA register
  248. */
  249. #define IX_NPEDL_EXCTL_CMD_WR_DATA_MEM 0x13
  250. /**
  251. * @def IX_NPEDL_EXCTL_CMD_RD_ECS_REG
  252. * @brief EXCTL Command to read Execution Access register at address in EXAD
  253. * register and return value in EXDATA register
  254. */
  255. #define IX_NPEDL_EXCTL_CMD_RD_ECS_REG 0x14
  256. /**
  257. * @def IX_NPEDL_EXCTL_CMD_WR_ECS_REG
  258. * @brief EXCTL Command to write Execution Access register at address in EXAD
  259. * register with data in EXDATA register
  260. */
  261. #define IX_NPEDL_EXCTL_CMD_WR_ECS_REG 0x15
  262. /**
  263. * @def IX_NPEDL_EXCTL_CMD_CLR_PROFILE_CNT
  264. * @brief EXCTL Command to clear Profile Count register
  265. */
  266. #define IX_NPEDL_EXCTL_CMD_CLR_PROFILE_CNT 0x0C
  267. /*
  268. * EXCTL (Execution Control) Register status bit masks
  269. */
  270. /**
  271. * @def IX_NPEDL_EXCTL_STATUS_RUN
  272. * @brief Masks the RUN status bit in the EXCTL register
  273. */
  274. #define IX_NPEDL_EXCTL_STATUS_RUN 0x80000000
  275. /**
  276. * @def IX_NPEDL_EXCTL_STATUS_STOP
  277. * @brief Masks the STOP status bit in the EXCTL register
  278. */
  279. #define IX_NPEDL_EXCTL_STATUS_STOP 0x40000000
  280. /**
  281. * @def IX_NPEDL_EXCTL_STATUS_CLEAR
  282. * @brief Masks the CLEAR status bit in the EXCTL register
  283. */
  284. #define IX_NPEDL_EXCTL_STATUS_CLEAR 0x20000000
  285. /**
  286. * @def IX_NPEDL_EXCTL_STATUS_ECS_K
  287. * @brief Masks the K (pipeline Klean) status bit in the EXCTL register
  288. */
  289. #define IX_NPEDL_EXCTL_STATUS_ECS_K 0x00800000
  290. /*
  291. * Executing Context Stack (ECS) level registers
  292. */
  293. /**
  294. * @def IX_NPEDL_ECS_BG_CTXT_REG_0
  295. * @brief Execution Access register address for register 0 at Backgound
  296. * Executing Context Stack level
  297. */
  298. #define IX_NPEDL_ECS_BG_CTXT_REG_0 0x00
  299. /**
  300. * @def IX_NPEDL_ECS_BG_CTXT_REG_1
  301. * @brief Execution Access register address for register 1 at Backgound
  302. * Executing Context Stack level
  303. */
  304. #define IX_NPEDL_ECS_BG_CTXT_REG_1 0x01
  305. /**
  306. * @def IX_NPEDL_ECS_BG_CTXT_REG_2
  307. * @brief Execution Access register address for register 2 at Backgound
  308. * Executing Context Stack level
  309. */
  310. #define IX_NPEDL_ECS_BG_CTXT_REG_2 0x02
  311. /**
  312. * @def IX_NPEDL_ECS_PRI_1_CTXT_REG_0
  313. * @brief Execution Access register address for register 0 at Priority 1
  314. * Executing Context Stack level
  315. */
  316. #define IX_NPEDL_ECS_PRI_1_CTXT_REG_0 0x04
  317. /**
  318. * @def IX_NPEDL_ECS_PRI_1_CTXT_REG_1
  319. * @brief Execution Access register address for register 1 at Priority 1
  320. * Executing Context Stack level
  321. */
  322. #define IX_NPEDL_ECS_PRI_1_CTXT_REG_1 0x05
  323. /**
  324. * @def IX_NPEDL_ECS_PRI_1_CTXT_REG_2
  325. * @brief Execution Access register address for register 2 at Priority 1
  326. * Executing Context Stack level
  327. */
  328. #define IX_NPEDL_ECS_PRI_1_CTXT_REG_2 0x06
  329. /**
  330. * @def IX_NPEDL_ECS_PRI_2_CTXT_REG_0
  331. * @brief Execution Access register address for register 0 at Priority 2
  332. * Executing Context Stack level
  333. */
  334. #define IX_NPEDL_ECS_PRI_2_CTXT_REG_0 0x08
  335. /**
  336. * @def IX_NPEDL_ECS_PRI_2_CTXT_REG_1
  337. * @brief Execution Access register address for register 1 at Priority 2
  338. * Executing Context Stack level
  339. */
  340. #define IX_NPEDL_ECS_PRI_2_CTXT_REG_1 0x09
  341. /**
  342. * @def IX_NPEDL_ECS_PRI_2_CTXT_REG_2
  343. * @brief Execution Access register address for register 2 at Priority 2
  344. * Executing Context Stack level
  345. */
  346. #define IX_NPEDL_ECS_PRI_2_CTXT_REG_2 0x0A
  347. /**
  348. * @def IX_NPEDL_ECS_DBG_CTXT_REG_0
  349. * @brief Execution Access register address for register 0 at Debug
  350. * Executing Context Stack level
  351. */
  352. #define IX_NPEDL_ECS_DBG_CTXT_REG_0 0x0C
  353. /**
  354. * @def IX_NPEDL_ECS_DBG_CTXT_REG_1
  355. * @brief Execution Access register address for register 1 at Debug
  356. * Executing Context Stack level
  357. */
  358. #define IX_NPEDL_ECS_DBG_CTXT_REG_1 0x0D
  359. /**
  360. * @def IX_NPEDL_ECS_DBG_CTXT_REG_2
  361. * @brief Execution Access register address for register 2 at Debug
  362. * Executing Context Stack level
  363. */
  364. #define IX_NPEDL_ECS_DBG_CTXT_REG_2 0x0E
  365. /**
  366. * @def IX_NPEDL_ECS_INSTRUCT_REG
  367. * @brief Execution Access register address for NPE Instruction Register
  368. */
  369. #define IX_NPEDL_ECS_INSTRUCT_REG 0x11
  370. /*
  371. * Execution Access register reset values
  372. */
  373. /**
  374. * @def IX_NPEDL_ECS_BG_CTXT_REG_0_RESET
  375. * @brief Reset value for Execution Access Background ECS level register 0
  376. */
  377. #define IX_NPEDL_ECS_BG_CTXT_REG_0_RESET 0xA0000000
  378. /**
  379. * @def IX_NPEDL_ECS_BG_CTXT_REG_1_RESET
  380. * @brief Reset value for Execution Access Background ECS level register 1
  381. */
  382. #define IX_NPEDL_ECS_BG_CTXT_REG_1_RESET 0x01000000
  383. /**
  384. * @def IX_NPEDL_ECS_BG_CTXT_REG_2_RESET
  385. * @brief Reset value for Execution Access Background ECS level register 2
  386. */
  387. #define IX_NPEDL_ECS_BG_CTXT_REG_2_RESET 0x00008000
  388. /**
  389. * @def IX_NPEDL_ECS_PRI_1_CTXT_REG_0_RESET
  390. * @brief Reset value for Execution Access Priority 1 ECS level register 0
  391. */
  392. #define IX_NPEDL_ECS_PRI_1_CTXT_REG_0_RESET 0x20000080
  393. /**
  394. * @def IX_NPEDL_ECS_PRI_1_CTXT_REG_1_RESET
  395. * @brief Reset value for Execution Access Priority 1 ECS level register 1
  396. */
  397. #define IX_NPEDL_ECS_PRI_1_CTXT_REG_1_RESET 0x01000000
  398. /**
  399. * @def IX_NPEDL_ECS_PRI_1_CTXT_REG_2_RESET
  400. * @brief Reset value for Execution Access Priority 1 ECS level register 2
  401. */
  402. #define IX_NPEDL_ECS_PRI_1_CTXT_REG_2_RESET 0x00008000
  403. /**
  404. * @def IX_NPEDL_ECS_PRI_2_CTXT_REG_0_RESET
  405. * @brief Reset value for Execution Access Priority 2 ECS level register 0
  406. */
  407. #define IX_NPEDL_ECS_PRI_2_CTXT_REG_0_RESET 0x20000080
  408. /**
  409. * @def IX_NPEDL_ECS_PRI_2_CTXT_REG_1_RESET
  410. * @brief Reset value for Execution Access Priority 2 ECS level register 1
  411. */
  412. #define IX_NPEDL_ECS_PRI_2_CTXT_REG_1_RESET 0x01000000
  413. /**
  414. * @def IX_NPEDL_ECS_PRI_2_CTXT_REG_2_RESET
  415. * @brief Reset value for Execution Access Priority 2 ECS level register 2
  416. */
  417. #define IX_NPEDL_ECS_PRI_2_CTXT_REG_2_RESET 0x00008000
  418. /**
  419. * @def IX_NPEDL_ECS_DBG_CTXT_REG_0_RESET
  420. * @brief Reset value for Execution Access Debug ECS level register 0
  421. */
  422. #define IX_NPEDL_ECS_DBG_CTXT_REG_0_RESET 0x20000000
  423. /**
  424. * @def IX_NPEDL_ECS_DBG_CTXT_REG_1_RESET
  425. * @brief Reset value for Execution Access Debug ECS level register 1
  426. */
  427. #define IX_NPEDL_ECS_DBG_CTXT_REG_1_RESET 0x00000000
  428. /**
  429. * @def IX_NPEDL_ECS_DBG_CTXT_REG_2_RESET
  430. * @brief Reset value for Execution Access Debug ECS level register 2
  431. */
  432. #define IX_NPEDL_ECS_DBG_CTXT_REG_2_RESET 0x001E0000
  433. /**
  434. * @def IX_NPEDL_ECS_INSTRUCT_REG_RESET
  435. * @brief Reset value for Execution Access NPE Instruction Register
  436. */
  437. #define IX_NPEDL_ECS_INSTRUCT_REG_RESET 0x1003C00F
  438. /*
  439. * masks used to read/write particular bits in Execution Access registers
  440. */
  441. /**
  442. * @def IX_NPEDL_MASK_ECS_REG_0_ACTIVE
  443. * @brief Mask the A (Active) bit in Execution Access Register 0 of all ECS
  444. * levels
  445. */
  446. #define IX_NPEDL_MASK_ECS_REG_0_ACTIVE 0x80000000
  447. /**
  448. * @def IX_NPEDL_MASK_ECS_REG_0_NEXTPC
  449. * @brief Mask the NextPC bits in Execution Access Register 0 of all ECS
  450. * levels (except Debug ECS level)
  451. */
  452. #define IX_NPEDL_MASK_ECS_REG_0_NEXTPC 0x1FFF0000
  453. /**
  454. * @def IX_NPEDL_MASK_ECS_REG_0_LDUR
  455. * @brief Mask the LDUR bits in Execution Access Register 0 of all ECS levels
  456. */
  457. #define IX_NPEDL_MASK_ECS_REG_0_LDUR 0x00000700
  458. /**
  459. * @def IX_NPEDL_MASK_ECS_REG_1_CCTXT
  460. * @brief Mask the NextPC bits in Execution Access Register 1 of all ECS levels
  461. */
  462. #define IX_NPEDL_MASK_ECS_REG_1_CCTXT 0x000F0000
  463. /**
  464. * @def IX_NPEDL_MASK_ECS_REG_1_SELCTXT
  465. * @brief Mask the NextPC bits in Execution Access Register 1 of all ECS levels
  466. */
  467. #define IX_NPEDL_MASK_ECS_REG_1_SELCTXT 0x0000000F
  468. /**
  469. * @def IX_NPEDL_MASK_ECS_DBG_REG_2_IF
  470. * @brief Mask the IF bit in Execution Access Register 2 of Debug ECS level
  471. */
  472. #define IX_NPEDL_MASK_ECS_DBG_REG_2_IF 0x00100000
  473. /**
  474. * @def IX_NPEDL_MASK_ECS_DBG_REG_2_IE
  475. * @brief Mask the IE bit in Execution Access Register 2 of Debug ECS level
  476. */
  477. #define IX_NPEDL_MASK_ECS_DBG_REG_2_IE 0x00080000
  478. /*
  479. * Bit-Offsets from LSB of particular bit-fields in Execution Access registers
  480. */
  481. /**
  482. * @def IX_NPEDL_OFFSET_ECS_REG_0_NEXTPC
  483. * @brief LSB-offset of NextPC field in Execution Access Register 0 of all ECS
  484. * levels (except Debug ECS level)
  485. */
  486. #define IX_NPEDL_OFFSET_ECS_REG_0_NEXTPC 16
  487. /**
  488. * @def IX_NPEDL_OFFSET_ECS_REG_0_LDUR
  489. * @brief LSB-offset of LDUR field in Execution Access Register 0 of all ECS
  490. * levels
  491. */
  492. #define IX_NPEDL_OFFSET_ECS_REG_0_LDUR 8
  493. /**
  494. * @def IX_NPEDL_OFFSET_ECS_REG_1_CCTXT
  495. * @brief LSB-offset of CCTXT field in Execution Access Register 1 of all ECS
  496. * levels
  497. */
  498. #define IX_NPEDL_OFFSET_ECS_REG_1_CCTXT 16
  499. /**
  500. * @def IX_NPEDL_OFFSET_ECS_REG_1_SELCTXT
  501. * @brief LSB-offset of SELCTXT field in Execution Access Register 1 of all ECS
  502. * levels
  503. */
  504. #define IX_NPEDL_OFFSET_ECS_REG_1_SELCTXT 0
  505. /*
  506. * NPE core & co-processor instruction templates to load into NPE Instruction
  507. * Register, for read/write of NPE register file registers
  508. */
  509. /**
  510. * @def IX_NPEDL_INSTR_RD_REG_BYTE
  511. * @brief NPE Instruction, used to read an 8-bit NPE internal logical register
  512. * and return the value in the EXDATA register (aligned to MSB).
  513. * NPE Assembler instruction: "mov8 d0, d0 &&& DBG_WrExec"
  514. */
  515. #define IX_NPEDL_INSTR_RD_REG_BYTE 0x0FC00000
  516. /**
  517. * @def IX_NPEDL_INSTR_RD_REG_SHORT
  518. * @brief NPE Instruction, used to read a 16-bit NPE internal logical register
  519. * and return the value in the EXDATA register (aligned to MSB).
  520. * NPE Assembler instruction: "mov16 d0, d0 &&& DBG_WrExec"
  521. */
  522. #define IX_NPEDL_INSTR_RD_REG_SHORT 0x0FC08010
  523. /**
  524. * @def IX_NPEDL_INSTR_RD_REG_WORD
  525. * @brief NPE Instruction, used to read a 16-bit NPE internal logical register
  526. * and return the value in the EXDATA register.
  527. * NPE Assembler instruction: "mov32 d0, d0 &&& DBG_WrExec"
  528. */
  529. #define IX_NPEDL_INSTR_RD_REG_WORD 0x0FC08210
  530. /**
  531. * @def IX_NPEDL_INSTR_WR_REG_BYTE
  532. * @brief NPE Immediate-Mode Instruction, used to write an 8-bit NPE internal
  533. * logical register.
  534. * NPE Assembler instruction: "mov8 d0, #0"
  535. */
  536. #define IX_NPEDL_INSTR_WR_REG_BYTE 0x00004000
  537. /**
  538. * @def IX_NPEDL_INSTR_WR_REG_SHORT
  539. * @brief NPE Immediate-Mode Instruction, used to write a 16-bit NPE internal
  540. * logical register.
  541. * NPE Assembler instruction: "mov16 d0, #0"
  542. */
  543. #define IX_NPEDL_INSTR_WR_REG_SHORT 0x0000C000
  544. /**
  545. * @def IX_NPEDL_INSTR_RD_FIFO
  546. * @brief NPE Immediate-Mode Instruction, used to write a 16-bit NPE internal
  547. * logical register.
  548. * NPE Assembler instruction: "cprd32 d0 &&& DBG_RdInFIFO"
  549. */
  550. #define IX_NPEDL_INSTR_RD_FIFO 0x0F888220
  551. /**
  552. * @def IX_NPEDL_INSTR_RESET_MBOX
  553. * @brief NPE Instruction, used to reset Mailbox (MBST) register
  554. * NPE Assembler instruction: "mov32 d0, d0 &&& DBG_ClearM"
  555. */
  556. #define IX_NPEDL_INSTR_RESET_MBOX 0x0FAC8210
  557. /*
  558. * Bit-offsets from LSB, of particular bit-fields in an NPE instruction
  559. */
  560. /**
  561. * @def IX_NPEDL_OFFSET_INSTR_SRC
  562. * @brief LSB-offset to SRC (source operand) field of an NPE Instruction
  563. */
  564. #define IX_NPEDL_OFFSET_INSTR_SRC 4
  565. /**
  566. * @def IX_NPEDL_OFFSET_INSTR_DEST
  567. * @brief LSB-offset to DEST (destination operand) field of an NPE Instruction
  568. */
  569. #define IX_NPEDL_OFFSET_INSTR_DEST 9
  570. /**
  571. * @def IX_NPEDL_OFFSET_INSTR_COPROC
  572. * @brief LSB-offset to COPROC (coprocessor instruction) field of an NPE
  573. * Instruction
  574. */
  575. #define IX_NPEDL_OFFSET_INSTR_COPROC 18
  576. /*
  577. * masks used to read/write particular bits of an NPE Instruction
  578. */
  579. /**
  580. * @def IX_NPEDL_MASK_IMMED_INSTR_SRC_DATA
  581. * @brief Mask the bits of 16-bit data value (least-sig 5 bits) to be used in
  582. * SRC field of immediate-mode NPE instruction
  583. */
  584. #define IX_NPEDL_MASK_IMMED_INSTR_SRC_DATA 0x1F
  585. /**
  586. * @def IX_NPEDL_MASK_IMMED_INSTR_COPROC_DATA
  587. * @brief Mask the bits of 16-bit data value (most-sig 11 bits) to be used in
  588. * COPROC field of immediate-mode NPE instruction
  589. */
  590. #define IX_NPEDL_MASK_IMMED_INSTR_COPROC_DATA 0xFFE0
  591. /**
  592. * @def IX_NPEDL_OFFSET_IMMED_INSTR_COPROC_DATA
  593. * @brief LSB offset of the bit-field of 16-bit data value (most-sig 11 bits)
  594. * to be used in COPROC field of immediate-mode NPE instruction
  595. */
  596. #define IX_NPEDL_OFFSET_IMMED_INSTR_COPROC_DATA 5
  597. /**
  598. * @def IX_NPEDL_DISPLACE_IMMED_INSTR_COPROC_DATA
  599. * @brief Number of left-shifts required to align most-sig 11 bits of 16-bit
  600. * data value into COPROC field of immediate-mode NPE instruction
  601. */
  602. #define IX_NPEDL_DISPLACE_IMMED_INSTR_COPROC_DATA \
  603. (IX_NPEDL_OFFSET_INSTR_COPROC - IX_NPEDL_OFFSET_IMMED_INSTR_COPROC_DATA)
  604. /**
  605. * @def IX_NPEDL_WR_INSTR_LDUR
  606. * @brief LDUR value used with immediate-mode NPE Instructions by the NpeDl
  607. * for writing to NPE internal logical registers
  608. */
  609. #define IX_NPEDL_WR_INSTR_LDUR 1
  610. /**
  611. * @def IX_NPEDL_RD_INSTR_LDUR
  612. * @brief LDUR value used with NON-immediate-mode NPE Instructions by the NpeDl
  613. * for reading from NPE internal logical registers
  614. */
  615. #define IX_NPEDL_RD_INSTR_LDUR 0
  616. /**
  617. * @enum IxNpeDlCtxtRegNum
  618. * @brief Numeric values to identify the NPE internal Context Store registers
  619. */
  620. typedef enum
  621. {
  622. IX_NPEDL_CTXT_REG_STEVT = 0, /**< identifies STEVT */
  623. IX_NPEDL_CTXT_REG_STARTPC, /**< identifies STARTPC */
  624. IX_NPEDL_CTXT_REG_REGMAP, /**< identifies REGMAP */
  625. IX_NPEDL_CTXT_REG_CINDEX, /**< identifies CINDEX */
  626. IX_NPEDL_CTXT_REG_MAX /**< Total number of Context Store registers */
  627. } IxNpeDlCtxtRegNum;
  628. /*
  629. * NPE Context Store register logical addresses
  630. */
  631. /**
  632. * @def IX_NPEDL_CTXT_REG_ADDR_STEVT
  633. * @brief Logical address of STEVT NPE internal Context Store register
  634. */
  635. #define IX_NPEDL_CTXT_REG_ADDR_STEVT 0x0000001B
  636. /**
  637. * @def IX_NPEDL_CTXT_REG_ADDR_STARTPC
  638. * @brief Logical address of STARTPC NPE internal Context Store register
  639. */
  640. #define IX_NPEDL_CTXT_REG_ADDR_STARTPC 0x0000001C
  641. /**
  642. * @def IX_NPEDL_CTXT_REG_ADDR_REGMAP
  643. * @brief Logical address of REGMAP NPE internal Context Store register
  644. */
  645. #define IX_NPEDL_CTXT_REG_ADDR_REGMAP 0x0000001E
  646. /**
  647. * @def IX_NPEDL_CTXT_REG_ADDR_CINDEX
  648. * @brief Logical address of CINDEX NPE internal Context Store register
  649. */
  650. #define IX_NPEDL_CTXT_REG_ADDR_CINDEX 0x0000001F
  651. /*
  652. * NPE Context Store register reset values
  653. */
  654. /**
  655. * @def IX_NPEDL_CTXT_REG_RESET_STEVT
  656. * @brief Reset value of STEVT NPE internal Context Store register
  657. * (STEVT = off, 0x80)
  658. */
  659. #define IX_NPEDL_CTXT_REG_RESET_STEVT 0x80
  660. /**
  661. * @def IX_NPEDL_CTXT_REG_RESET_STARTPC
  662. * @brief Reset value of STARTPC NPE internal Context Store register
  663. * (STARTPC = 0x0000)
  664. */
  665. #define IX_NPEDL_CTXT_REG_RESET_STARTPC 0x0000
  666. /**
  667. * @def IX_NPEDL_CTXT_REG_RESET_REGMAP
  668. * @brief Reset value of REGMAP NPE internal Context Store register
  669. * (REGMAP = d0->p0, d8->p2, d16->p4)
  670. */
  671. #define IX_NPEDL_CTXT_REG_RESET_REGMAP 0x0820
  672. /**
  673. * @def IX_NPEDL_CTXT_REG_RESET_CINDEX
  674. * @brief Reset value of CINDEX NPE internal Context Store register
  675. * (CINDEX = 0)
  676. */
  677. #define IX_NPEDL_CTXT_REG_RESET_CINDEX 0x00
  678. /*
  679. * numeric range of context levels available on an NPE
  680. */
  681. /**
  682. * @def IX_NPEDL_CTXT_NUM_MIN
  683. * @brief Lowest NPE Context number in range
  684. */
  685. #define IX_NPEDL_CTXT_NUM_MIN 0
  686. /**
  687. * @def IX_NPEDL_CTXT_NUM_MAX
  688. * @brief Highest NPE Context number in range
  689. */
  690. #define IX_NPEDL_CTXT_NUM_MAX 15
  691. /*
  692. * Physical NPE internal registers
  693. */
  694. /**
  695. * @def IX_NPEDL_TOTAL_NUM_PHYS_REG
  696. * @brief Number of Physical registers currently supported
  697. * Initial NPE implementations will have a 32-word register file.
  698. * Later implementations may have a 64-word register file.
  699. */
  700. #define IX_NPEDL_TOTAL_NUM_PHYS_REG 32
  701. /**
  702. * @def IX_NPEDL_OFFSET_PHYS_REG_ADDR_REGMAP
  703. * @brief LSB-offset of Regmap number in Physical NPE register address, used
  704. * for Physical To Logical register address mapping in the NPE
  705. */
  706. #define IX_NPEDL_OFFSET_PHYS_REG_ADDR_REGMAP 1
  707. /**
  708. * @def IX_NPEDL_MASK_PHYS_REG_ADDR_LOGICAL_ADDR
  709. * @brief Mask to extract a logical NPE register address from a physical
  710. * register address, used for Physical To Logical address mapping
  711. */
  712. #define IX_NPEDL_MASK_PHYS_REG_ADDR_LOGICAL_ADDR 0x1
  713. #endif /* IXNPEDLNPEMGRECREGISTERS_P_H */